1 /*-
2 * Copyright (c) 2005 Nate Lawson
3 * Copyright (c) 2004 Colin Percival
4 * Copyright (c) 2004-2005 Bruno Durcot
5 * Copyright (c) 2004 FUKUDA Nobuhiko
6 * Copyright (c) 2009 Michael Reifenberger
7 * Copyright (c) 2009 Norikatsu Shigemura
8 * Copyright (c) 2008-2009 Gen Otsuji
9 *
10 * This code is depending on kern_cpu.c, est.c, powernow.c, p4tcc.c, smist.c
11 * in various parts. The authors of these files are Nate Lawson,
12 * Colin Percival, Bruno Durcot, and FUKUDA Nobuhiko.
13 * This code contains patches by Michael Reifenberger and Norikatsu Shigemura.
14 * Thank you.
15 *
16 * Redistribution and use in source and binary forms, with or without
17 * modification, are permitted providing that the following conditions
18 * are met:
19 * 1. Redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR``AS IS'' AND ANY EXPRESS OR
26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
27 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
29 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
33 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
34 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 /*
39 * For more info:
40 * BIOS and Kernel Developer's Guide(BKDG) for AMD Family 10h Processors
41 * 31116 Rev 3.20 February 04, 2009
42 * BIOS and Kernel Developer's Guide(BKDG) for AMD Family 11h Processors
43 * 41256 Rev 3.00 - July 07, 2008
44 */
45
46 #include <sys/cdefs.h>
47 __FBSDID("$FreeBSD$");
48
49 #include <sys/param.h>
50 #include <sys/bus.h>
51 #include <sys/cpu.h>
52 #include <sys/kernel.h>
53 #include <sys/module.h>
54 #include <sys/malloc.h>
55 #include <sys/proc.h>
56 #include <sys/pcpu.h>
57 #include <sys/smp.h>
58 #include <sys/sched.h>
59
60 #include <machine/md_var.h>
61 #include <machine/cputypes.h>
62 #include <machine/specialreg.h>
63
64 #include <contrib/dev/acpica/include/acpi.h>
65
66 #include <dev/acpica/acpivar.h>
67
68 #include "acpi_if.h"
69 #include "cpufreq_if.h"
70
71 #define MSR_AMD_10H_11H_LIMIT 0xc0010061
72 #define MSR_AMD_10H_11H_CONTROL 0xc0010062
73 #define MSR_AMD_10H_11H_STATUS 0xc0010063
74 #define MSR_AMD_10H_11H_CONFIG 0xc0010064
75
76 #define AMD_10H_11H_MAX_STATES 16
77
78 /* for MSR_AMD_10H_11H_LIMIT C001_0061 */
79 #define AMD_10H_11H_GET_PSTATE_MAX_VAL(msr) (((msr) >> 4) & 0x7)
80 #define AMD_10H_11H_GET_PSTATE_LIMIT(msr) (((msr)) & 0x7)
81 /* for MSR_AMD_10H_11H_CONFIG 10h:C001_0064:68 / 11h:C001_0064:6B */
82 #define AMD_10H_11H_CUR_VID(msr) (((msr) >> 9) & 0x7F)
83 #define AMD_10H_11H_CUR_DID(msr) (((msr) >> 6) & 0x07)
84 #define AMD_10H_11H_CUR_FID(msr) ((msr) & 0x3F)
85
86 #define HWPSTATE_DEBUG(dev, msg...) \
87 do{ \
88 if(hwpstate_verbose) \
89 device_printf(dev, msg); \
90 }while(0)
91
92 struct hwpstate_setting {
93 int freq; /* CPU clock in Mhz or 100ths of a percent. */
94 int volts; /* Voltage in mV. */
95 int power; /* Power consumed in mW. */
96 int lat; /* Transition latency in us. */
97 int pstate_id; /* P-State id */
98 };
99
100 struct hwpstate_softc {
101 device_t dev;
102 struct hwpstate_setting hwpstate_settings[AMD_10H_11H_MAX_STATES];
103 int cfnum;
104 };
105
106 static void hwpstate_identify(driver_t *driver, device_t parent);
107 static int hwpstate_probe(device_t dev);
108 static int hwpstate_attach(device_t dev);
109 static int hwpstate_detach(device_t dev);
110 static int hwpstate_set(device_t dev, const struct cf_setting *cf);
111 static int hwpstate_get(device_t dev, struct cf_setting *cf);
112 static int hwpstate_settings(device_t dev, struct cf_setting *sets, int *count);
113 static int hwpstate_type(device_t dev, int *type);
114 static int hwpstate_shutdown(device_t dev);
115 static int hwpstate_features(driver_t *driver, u_int *features);
116 static int hwpstate_get_info_from_acpi_perf(device_t dev, device_t perf_dev);
117 static int hwpstate_get_info_from_msr(device_t dev);
118 static int hwpstate_goto_pstate(device_t dev, int pstate_id);
119
120 static int hwpstate_verbose = 0;
121 SYSCTL_INT(_debug, OID_AUTO, hwpstate_verbose, CTLFLAG_RW | CTLFLAG_TUN,
122 &hwpstate_verbose, 0, "Debug hwpstate");
123 TUNABLE_INT("debug.hwpstate_verbose", &hwpstate_verbose);
124
125 static device_method_t hwpstate_methods[] = {
126 /* Device interface */
127 DEVMETHOD(device_identify, hwpstate_identify),
128 DEVMETHOD(device_probe, hwpstate_probe),
129 DEVMETHOD(device_attach, hwpstate_attach),
130 DEVMETHOD(device_detach, hwpstate_detach),
131 DEVMETHOD(device_shutdown, hwpstate_shutdown),
132
133 /* cpufreq interface */
134 DEVMETHOD(cpufreq_drv_set, hwpstate_set),
135 DEVMETHOD(cpufreq_drv_get, hwpstate_get),
136 DEVMETHOD(cpufreq_drv_settings, hwpstate_settings),
137 DEVMETHOD(cpufreq_drv_type, hwpstate_type),
138
139 /* ACPI interface */
140 DEVMETHOD(acpi_get_features, hwpstate_features),
141
142 {0, 0}
143 };
144
145 static devclass_t hwpstate_devclass;
146 static driver_t hwpstate_driver = {
147 "hwpstate",
148 hwpstate_methods,
149 sizeof(struct hwpstate_softc),
150 };
151
152 DRIVER_MODULE(hwpstate, cpu, hwpstate_driver, hwpstate_devclass, 0, 0);
153
154 /*
155 * Go to Px-state on all cpus considering the limit.
156 */
157 static int
158 hwpstate_goto_pstate(device_t dev, int pstate)
159 {
160 int i;
161 uint64_t msr;
162 int j;
163 int limit;
164 int id = pstate;
165 int error;
166
167 /* get the current pstate limit */
168 msr = rdmsr(MSR_AMD_10H_11H_LIMIT);
169 limit = AMD_10H_11H_GET_PSTATE_LIMIT(msr);
170 if(limit > id)
171 id = limit;
172
173 /*
174 * We are going to the same Px-state on all cpus.
175 * Probably should take _PSD into account.
176 */
177 error = 0;
178 CPU_FOREACH(i) {
179 /* Bind to each cpu. */
180 thread_lock(curthread);
181 sched_bind(curthread, i);
182 thread_unlock(curthread);
183 HWPSTATE_DEBUG(dev, "setting P%d-state on cpu%d\n",
184 id, PCPU_GET(cpuid));
185 /* Go To Px-state */
186 wrmsr(MSR_AMD_10H_11H_CONTROL, id);
187 /* wait loop (100*100 usec is enough ?) */
188 for(j = 0; j < 100; j++){
189 msr = rdmsr(MSR_AMD_10H_11H_STATUS);
190 if(msr == id){
191 break;
192 }
193 DELAY(100);
194 }
195 /* get the result. not assure msr=id */
196 msr = rdmsr(MSR_AMD_10H_11H_STATUS);
197 HWPSTATE_DEBUG(dev, "result P%d-state on cpu%d\n",
198 (int)msr, PCPU_GET(cpuid));
199 if (msr != id) {
200 HWPSTATE_DEBUG(dev, "error: loop is not enough.\n");
201 error = ENXIO;
202 }
203 }
204 thread_lock(curthread);
205 sched_unbind(curthread);
206 thread_unlock(curthread);
207 return (error);
208 }
209
210 static int
211 hwpstate_set(device_t dev, const struct cf_setting *cf)
212 {
213 struct hwpstate_softc *sc;
214 struct hwpstate_setting *set;
215 int i;
216
217 if (cf == NULL)
218 return (EINVAL);
219 sc = device_get_softc(dev);
220 set = sc->hwpstate_settings;
221 for (i = 0; i < sc->cfnum; i++)
222 if (CPUFREQ_CMP(cf->freq, set[i].freq))
223 break;
224 if (i == sc->cfnum)
225 return (EINVAL);
226
227 return (hwpstate_goto_pstate(dev, set[i].pstate_id));
228 }
229
230 static int
231 hwpstate_get(device_t dev, struct cf_setting *cf)
232 {
233 struct hwpstate_softc *sc;
234 struct hwpstate_setting set;
235 uint64_t msr;
236
237 sc = device_get_softc(dev);
238 if (cf == NULL)
239 return (EINVAL);
240 msr = rdmsr(MSR_AMD_10H_11H_STATUS);
241 if(msr >= sc->cfnum)
242 return (EINVAL);
243 set = sc->hwpstate_settings[msr];
244
245 cf->freq = set.freq;
246 cf->volts = set.volts;
247 cf->power = set.power;
248 cf->lat = set.lat;
249 cf->dev = dev;
250 return (0);
251 }
252
253 static int
254 hwpstate_settings(device_t dev, struct cf_setting *sets, int *count)
255 {
256 struct hwpstate_softc *sc;
257 struct hwpstate_setting set;
258 int i;
259
260 if (sets == NULL || count == NULL)
261 return (EINVAL);
262 sc = device_get_softc(dev);
263 if (*count < sc->cfnum)
264 return (E2BIG);
265 for (i = 0; i < sc->cfnum; i++, sets++) {
266 set = sc->hwpstate_settings[i];
267 sets->freq = set.freq;
268 sets->volts = set.volts;
269 sets->power = set.power;
270 sets->lat = set.lat;
271 sets->dev = dev;
272 }
273 *count = sc->cfnum;
274
275 return (0);
276 }
277
278 static int
279 hwpstate_type(device_t dev, int *type)
280 {
281
282 if (type == NULL)
283 return (EINVAL);
284
285 *type = CPUFREQ_TYPE_ABSOLUTE;
286 return (0);
287 }
288
289 static void
290 hwpstate_identify(driver_t *driver, device_t parent)
291 {
292
293 if (device_find_child(parent, "hwpstate", -1) != NULL)
294 return;
295
296 if (cpu_vendor_id != CPU_VENDOR_AMD || CPUID_TO_FAMILY(cpu_id) < 0x10)
297 return;
298
299 /*
300 * Check if hardware pstate enable bit is set.
301 */
302 if ((amd_pminfo & AMDPM_HW_PSTATE) == 0) {
303 HWPSTATE_DEBUG(parent, "hwpstate enable bit is not set.\n");
304 return;
305 }
306
307 if (resource_disabled("hwpstate", 0))
308 return;
309
310 if (BUS_ADD_CHILD(parent, 10, "hwpstate", -1) == NULL)
311 device_printf(parent, "hwpstate: add child failed\n");
312 }
313
314 static int
315 hwpstate_probe(device_t dev)
316 {
317 struct hwpstate_softc *sc;
318 device_t perf_dev;
319 uint64_t msr;
320 int error, type;
321
322 /*
323 * Only hwpstate0.
324 * It goes well with acpi_throttle.
325 */
326 if (device_get_unit(dev) != 0)
327 return (ENXIO);
328
329 sc = device_get_softc(dev);
330 sc->dev = dev;
331
332 /*
333 * Check if acpi_perf has INFO only flag.
334 */
335 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
336 error = TRUE;
337 if (perf_dev && device_is_attached(perf_dev)) {
338 error = CPUFREQ_DRV_TYPE(perf_dev, &type);
339 if (error == 0) {
340 if ((type & CPUFREQ_FLAG_INFO_ONLY) == 0) {
341 /*
342 * If acpi_perf doesn't have INFO_ONLY flag,
343 * it will take care of pstate transitions.
344 */
345 HWPSTATE_DEBUG(dev, "acpi_perf will take care of pstate transitions.\n");
346 return (ENXIO);
347 } else {
348 /*
349 * If acpi_perf has INFO_ONLY flag, (_PCT has FFixedHW)
350 * we can get _PSS info from acpi_perf
351 * without going into ACPI.
352 */
353 HWPSTATE_DEBUG(dev, "going to fetch info from acpi_perf\n");
354 error = hwpstate_get_info_from_acpi_perf(dev, perf_dev);
355 }
356 }
357 }
358
359 if (error == 0) {
360 /*
361 * Now we get _PSS info from acpi_perf without error.
362 * Let's check it.
363 */
364 msr = rdmsr(MSR_AMD_10H_11H_LIMIT);
365 if (sc->cfnum != 1 + AMD_10H_11H_GET_PSTATE_MAX_VAL(msr)) {
366 HWPSTATE_DEBUG(dev, "msr and acpi _PSS count mismatch.\n");
367 error = TRUE;
368 }
369 }
370
371 /*
372 * If we cannot get info from acpi_perf,
373 * Let's get info from MSRs.
374 */
375 if (error)
376 error = hwpstate_get_info_from_msr(dev);
377 if (error)
378 return (error);
379
380 device_set_desc(dev, "Cool`n'Quiet 2.0");
381 return (0);
382 }
383
384 static int
385 hwpstate_attach(device_t dev)
386 {
387
388 return (cpufreq_register(dev));
389 }
390
391 static int
392 hwpstate_get_info_from_msr(device_t dev)
393 {
394 struct hwpstate_softc *sc;
395 struct hwpstate_setting *hwpstate_set;
396 uint64_t msr;
397 int family, i, fid, did;
398
399 family = CPUID_TO_FAMILY(cpu_id);
400 sc = device_get_softc(dev);
401 /* Get pstate count */
402 msr = rdmsr(MSR_AMD_10H_11H_LIMIT);
403 sc->cfnum = 1 + AMD_10H_11H_GET_PSTATE_MAX_VAL(msr);
404 hwpstate_set = sc->hwpstate_settings;
405 for (i = 0; i < sc->cfnum; i++) {
406 msr = rdmsr(MSR_AMD_10H_11H_CONFIG + i);
407 if ((msr & ((uint64_t)1 << 63)) != ((uint64_t)1 << 63)) {
408 HWPSTATE_DEBUG(dev, "msr is not valid.\n");
409 return (ENXIO);
410 }
411 did = AMD_10H_11H_CUR_DID(msr);
412 fid = AMD_10H_11H_CUR_FID(msr);
413 switch(family) {
414 case 0x11:
415 /* fid/did to frequency */
416 hwpstate_set[i].freq = 100 * (fid + 0x08) / (1 << did);
417 break;
418 case 0x10:
419 /* fid/did to frequency */
420 hwpstate_set[i].freq = 100 * (fid + 0x10) / (1 << did);
421 break;
422 default:
423 HWPSTATE_DEBUG(dev, "get_info_from_msr: AMD family %d CPU's are not implemented yet. sorry.\n", family);
424 return (ENXIO);
425 break;
426 }
427 hwpstate_set[i].pstate_id = i;
428 /* There was volts calculation, but deleted it. */
429 hwpstate_set[i].volts = CPUFREQ_VAL_UNKNOWN;
430 hwpstate_set[i].power = CPUFREQ_VAL_UNKNOWN;
431 hwpstate_set[i].lat = CPUFREQ_VAL_UNKNOWN;
432 }
433 return (0);
434 }
435
436 static int
437 hwpstate_get_info_from_acpi_perf(device_t dev, device_t perf_dev)
438 {
439 struct hwpstate_softc *sc;
440 struct cf_setting *perf_set;
441 struct hwpstate_setting *hwpstate_set;
442 int count, error, i;
443
444 perf_set = malloc(MAX_SETTINGS * sizeof(*perf_set), M_TEMP, M_NOWAIT);
445 if (perf_set == NULL) {
446 HWPSTATE_DEBUG(dev, "nomem\n");
447 return (ENOMEM);
448 }
449 /*
450 * Fetch settings from acpi_perf.
451 * Now it is attached, and has info only flag.
452 */
453 count = MAX_SETTINGS;
454 error = CPUFREQ_DRV_SETTINGS(perf_dev, perf_set, &count);
455 if (error) {
456 HWPSTATE_DEBUG(dev, "error: CPUFREQ_DRV_SETTINGS.\n");
457 goto out;
458 }
459 sc = device_get_softc(dev);
460 sc->cfnum = count;
461 hwpstate_set = sc->hwpstate_settings;
462 for (i = 0; i < count; i++) {
463 if (i == perf_set[i].spec[0]) {
464 hwpstate_set[i].pstate_id = i;
465 hwpstate_set[i].freq = perf_set[i].freq;
466 hwpstate_set[i].volts = perf_set[i].volts;
467 hwpstate_set[i].power = perf_set[i].power;
468 hwpstate_set[i].lat = perf_set[i].lat;
469 } else {
470 HWPSTATE_DEBUG(dev, "ACPI _PSS object mismatch.\n");
471 error = ENXIO;
472 goto out;
473 }
474 }
475 out:
476 if (perf_set)
477 free(perf_set, M_TEMP);
478 return (error);
479 }
480
481 static int
482 hwpstate_detach(device_t dev)
483 {
484
485 hwpstate_goto_pstate(dev, 0);
486 return (cpufreq_unregister(dev));
487 }
488
489 static int
490 hwpstate_shutdown(device_t dev)
491 {
492
493 /* hwpstate_goto_pstate(dev, 0); */
494 return (0);
495 }
496
497 static int
498 hwpstate_features(driver_t *driver, u_int *features)
499 {
500
501 /* Notify the ACPI CPU that we support direct access to MSRs */
502 *features = ACPI_CAP_PERF_MSRS;
503 return (0);
504 }
Cache object: 94e25c386a06c81a473e1317d3ca748f
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