1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2005 Nate Lawson
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 /*
30 * Throttle clock frequency by using the thermal control circuit. This
31 * operates independently of SpeedStep and ACPI throttling and is supported
32 * on Pentium 4 and later models (feature TM).
33 *
34 * Reference: Intel Developer's manual v.3 #245472-012
35 *
36 * The original version of this driver was written by Ted Unangst for
37 * OpenBSD and imported by Maxim Sobolev. It was rewritten by Nate Lawson
38 * for use with the cpufreq framework.
39 */
40
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
43
44 #include <sys/param.h>
45 #include <sys/systm.h>
46 #include <sys/bus.h>
47 #include <sys/cpu.h>
48 #include <sys/kernel.h>
49 #include <sys/module.h>
50
51 #include <machine/md_var.h>
52 #include <machine/specialreg.h>
53
54 #include "cpufreq_if.h"
55
56 #include <contrib/dev/acpica/include/acpi.h>
57
58 #include <dev/acpica/acpivar.h>
59 #include "acpi_if.h"
60
61 struct p4tcc_softc {
62 device_t dev;
63 int set_count;
64 int lowest_val;
65 int auto_mode;
66 };
67
68 #define TCC_NUM_SETTINGS 8
69
70 #define TCC_ENABLE_ONDEMAND (1<<4)
71 #define TCC_REG_OFFSET 1
72 #define TCC_SPEED_PERCENT(x) ((10000 * (x)) / TCC_NUM_SETTINGS)
73
74 static int p4tcc_features(driver_t *driver, u_int *features);
75 static void p4tcc_identify(driver_t *driver, device_t parent);
76 static int p4tcc_probe(device_t dev);
77 static int p4tcc_attach(device_t dev);
78 static int p4tcc_detach(device_t dev);
79 static int p4tcc_settings(device_t dev, struct cf_setting *sets,
80 int *count);
81 static int p4tcc_set(device_t dev, const struct cf_setting *set);
82 static int p4tcc_get(device_t dev, struct cf_setting *set);
83 static int p4tcc_type(device_t dev, int *type);
84
85 static device_method_t p4tcc_methods[] = {
86 /* Device interface */
87 DEVMETHOD(device_identify, p4tcc_identify),
88 DEVMETHOD(device_probe, p4tcc_probe),
89 DEVMETHOD(device_attach, p4tcc_attach),
90 DEVMETHOD(device_detach, p4tcc_detach),
91
92 /* cpufreq interface */
93 DEVMETHOD(cpufreq_drv_set, p4tcc_set),
94 DEVMETHOD(cpufreq_drv_get, p4tcc_get),
95 DEVMETHOD(cpufreq_drv_type, p4tcc_type),
96 DEVMETHOD(cpufreq_drv_settings, p4tcc_settings),
97
98 /* ACPI interface */
99 DEVMETHOD(acpi_get_features, p4tcc_features),
100
101 {0, 0}
102 };
103
104 static driver_t p4tcc_driver = {
105 "p4tcc",
106 p4tcc_methods,
107 sizeof(struct p4tcc_softc),
108 };
109
110 static devclass_t p4tcc_devclass;
111 DRIVER_MODULE(p4tcc, cpu, p4tcc_driver, p4tcc_devclass, 0, 0);
112
113 static int
114 p4tcc_features(driver_t *driver, u_int *features)
115 {
116
117 /* Notify the ACPI CPU that we support direct access to MSRs */
118 *features = ACPI_CAP_THR_MSRS;
119 return (0);
120 }
121
122 static void
123 p4tcc_identify(driver_t *driver, device_t parent)
124 {
125
126 if ((cpu_feature & (CPUID_ACPI | CPUID_TM)) != (CPUID_ACPI | CPUID_TM))
127 return;
128
129 /* Make sure we're not being doubly invoked. */
130 if (device_find_child(parent, "p4tcc", -1) != NULL)
131 return;
132
133 /*
134 * We attach a p4tcc child for every CPU since settings need to
135 * be performed on every CPU in the SMP case. See section 13.15.3
136 * of the IA32 Intel Architecture Software Developer's Manual,
137 * Volume 3, for more info.
138 */
139 if (BUS_ADD_CHILD(parent, 10, "p4tcc", -1) == NULL)
140 device_printf(parent, "add p4tcc child failed\n");
141 }
142
143 static int
144 p4tcc_probe(device_t dev)
145 {
146
147 if (resource_disabled("p4tcc", 0))
148 return (ENXIO);
149
150 device_set_desc(dev, "CPU Frequency Thermal Control");
151 return (0);
152 }
153
154 static int
155 p4tcc_attach(device_t dev)
156 {
157 struct p4tcc_softc *sc;
158 struct cf_setting set;
159
160 sc = device_get_softc(dev);
161 sc->dev = dev;
162 sc->set_count = TCC_NUM_SETTINGS;
163
164 /*
165 * On boot, the TCC is usually in Automatic mode where reading the
166 * current performance level is likely to produce bogus results.
167 * We record that state here and don't trust the contents of the
168 * status MSR until we've set it ourselves.
169 */
170 sc->auto_mode = TRUE;
171
172 /*
173 * XXX: After a cursory glance at various Intel specification
174 * XXX: updates it seems like these tests for errata is bogus.
175 * XXX: As far as I can tell, the failure mode is benign, in
176 * XXX: that cpus with no errata will have their bottom two
177 * XXX: STPCLK# rates disabled, so rather than waste more time
178 * XXX: hunting down intel docs, just document it and punt. /phk
179 */
180 switch (cpu_id & 0xff) {
181 case 0x22:
182 case 0x24:
183 case 0x25:
184 case 0x27:
185 case 0x29:
186 /*
187 * These CPU models hang when set to 12.5%.
188 * See Errata O50, P44, and Z21.
189 */
190 sc->set_count -= 1;
191 break;
192 case 0x07: /* errata N44 and P18 */
193 case 0x0a:
194 case 0x12:
195 case 0x13:
196 case 0x62: /* Pentium D B1: errata AA21 */
197 case 0x64: /* Pentium D C1: errata AA21 */
198 case 0x65: /* Pentium D D0: errata AA21 */
199 /*
200 * These CPU models hang when set to 12.5% or 25%.
201 * See Errata N44, P18l and AA21.
202 */
203 sc->set_count -= 2;
204 break;
205 }
206 sc->lowest_val = TCC_NUM_SETTINGS - sc->set_count + 1;
207
208 /*
209 * Before we finish attach, switch to 100%. It's possible the BIOS
210 * set us to a lower rate. The user can override this after boot.
211 */
212 set.freq = 10000;
213 p4tcc_set(dev, &set);
214
215 cpufreq_register(dev);
216 return (0);
217 }
218
219 static int
220 p4tcc_detach(device_t dev)
221 {
222 struct cf_setting set;
223 int error;
224
225 error = cpufreq_unregister(dev);
226 if (error)
227 return (error);
228
229 /*
230 * Before we finish detach, switch to Automatic mode.
231 */
232 set.freq = 10000;
233 p4tcc_set(dev, &set);
234 return(0);
235 }
236
237 static int
238 p4tcc_settings(device_t dev, struct cf_setting *sets, int *count)
239 {
240 struct p4tcc_softc *sc;
241 int i, val;
242
243 sc = device_get_softc(dev);
244 if (sets == NULL || count == NULL)
245 return (EINVAL);
246 if (*count < sc->set_count)
247 return (E2BIG);
248
249 /* Return a list of valid settings for this driver. */
250 memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * sc->set_count);
251 val = TCC_NUM_SETTINGS;
252 for (i = 0; i < sc->set_count; i++, val--) {
253 sets[i].freq = TCC_SPEED_PERCENT(val);
254 sets[i].dev = dev;
255 }
256 *count = sc->set_count;
257
258 return (0);
259 }
260
261 static int
262 p4tcc_set(device_t dev, const struct cf_setting *set)
263 {
264 struct p4tcc_softc *sc;
265 uint64_t mask, msr;
266 int val;
267
268 if (set == NULL)
269 return (EINVAL);
270 sc = device_get_softc(dev);
271
272 /*
273 * Validate requested state converts to a setting that is an integer
274 * from [sc->lowest_val .. TCC_NUM_SETTINGS].
275 */
276 val = set->freq * TCC_NUM_SETTINGS / 10000;
277 if (val * 10000 != set->freq * TCC_NUM_SETTINGS ||
278 val < sc->lowest_val || val > TCC_NUM_SETTINGS)
279 return (EINVAL);
280
281 /*
282 * Read the current register and mask off the old setting and
283 * On-Demand bit. If the new val is < 100%, set it and the On-Demand
284 * bit, otherwise just return to Automatic mode.
285 */
286 msr = rdmsr(MSR_THERM_CONTROL);
287 mask = (TCC_NUM_SETTINGS - 1) << TCC_REG_OFFSET;
288 msr &= ~(mask | TCC_ENABLE_ONDEMAND);
289 if (val < TCC_NUM_SETTINGS)
290 msr |= (val << TCC_REG_OFFSET) | TCC_ENABLE_ONDEMAND;
291 wrmsr(MSR_THERM_CONTROL, msr);
292
293 /*
294 * Record whether we're now in Automatic or On-Demand mode. We have
295 * to cache this since there is no reliable way to check if TCC is in
296 * Automatic mode (i.e., at 100% or possibly 50%). Reading bit 4 of
297 * the ACPI Thermal Monitor Control Register produces 0 no matter
298 * what the current mode.
299 */
300 if (msr & TCC_ENABLE_ONDEMAND)
301 sc->auto_mode = FALSE;
302 else
303 sc->auto_mode = TRUE;
304
305 return (0);
306 }
307
308 static int
309 p4tcc_get(device_t dev, struct cf_setting *set)
310 {
311 struct p4tcc_softc *sc;
312 uint64_t msr;
313 int val;
314
315 if (set == NULL)
316 return (EINVAL);
317 sc = device_get_softc(dev);
318
319 /*
320 * Read the current register and extract the current setting. If
321 * in automatic mode, assume we're at TCC_NUM_SETTINGS (100%).
322 *
323 * XXX This is not completely reliable since at high temperatures
324 * the CPU may be automatically throttling to 50% but it's the best
325 * we can do.
326 */
327 if (!sc->auto_mode) {
328 msr = rdmsr(MSR_THERM_CONTROL);
329 val = (msr >> TCC_REG_OFFSET) & (TCC_NUM_SETTINGS - 1);
330 } else
331 val = TCC_NUM_SETTINGS;
332
333 memset(set, CPUFREQ_VAL_UNKNOWN, sizeof(*set));
334 set->freq = TCC_SPEED_PERCENT(val);
335 set->dev = dev;
336
337 return (0);
338 }
339
340 static int
341 p4tcc_type(device_t dev, int *type)
342 {
343
344 if (type == NULL)
345 return (EINVAL);
346
347 *type = CPUFREQ_TYPE_RELATIVE;
348 return (0);
349 }
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