1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2005 Nate Lawson
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 /*
30 * Throttle clock frequency by using the thermal control circuit. This
31 * operates independently of SpeedStep and ACPI throttling and is supported
32 * on Pentium 4 and later models (feature TM).
33 *
34 * Reference: Intel Developer's manual v.3 #245472-012
35 *
36 * The original version of this driver was written by Ted Unangst for
37 * OpenBSD and imported by Maxim Sobolev. It was rewritten by Nate Lawson
38 * for use with the cpufreq framework.
39 */
40
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
43
44 #include <sys/param.h>
45 #include <sys/systm.h>
46 #include <sys/bus.h>
47 #include <sys/cpu.h>
48 #include <sys/kernel.h>
49 #include <sys/module.h>
50
51 #include <machine/md_var.h>
52 #include <machine/specialreg.h>
53
54 #include "cpufreq_if.h"
55
56 #include <contrib/dev/acpica/include/acpi.h>
57
58 #include <dev/acpica/acpivar.h>
59 #include "acpi_if.h"
60
61 struct p4tcc_softc {
62 device_t dev;
63 int set_count;
64 int lowest_val;
65 int auto_mode;
66 };
67
68 #define TCC_NUM_SETTINGS 8
69
70 #define TCC_ENABLE_ONDEMAND (1<<4)
71 #define TCC_REG_OFFSET 1
72 #define TCC_SPEED_PERCENT(x) ((10000 * (x)) / TCC_NUM_SETTINGS)
73
74 static int p4tcc_features(driver_t *driver, u_int *features);
75 static void p4tcc_identify(driver_t *driver, device_t parent);
76 static int p4tcc_probe(device_t dev);
77 static int p4tcc_attach(device_t dev);
78 static int p4tcc_detach(device_t dev);
79 static int p4tcc_settings(device_t dev, struct cf_setting *sets,
80 int *count);
81 static int p4tcc_set(device_t dev, const struct cf_setting *set);
82 static int p4tcc_get(device_t dev, struct cf_setting *set);
83 static int p4tcc_type(device_t dev, int *type);
84
85 static device_method_t p4tcc_methods[] = {
86 /* Device interface */
87 DEVMETHOD(device_identify, p4tcc_identify),
88 DEVMETHOD(device_probe, p4tcc_probe),
89 DEVMETHOD(device_attach, p4tcc_attach),
90 DEVMETHOD(device_detach, p4tcc_detach),
91
92 /* cpufreq interface */
93 DEVMETHOD(cpufreq_drv_set, p4tcc_set),
94 DEVMETHOD(cpufreq_drv_get, p4tcc_get),
95 DEVMETHOD(cpufreq_drv_type, p4tcc_type),
96 DEVMETHOD(cpufreq_drv_settings, p4tcc_settings),
97
98 /* ACPI interface */
99 DEVMETHOD(acpi_get_features, p4tcc_features),
100 {0, 0}
101 };
102
103 static driver_t p4tcc_driver = {
104 "p4tcc",
105 p4tcc_methods,
106 sizeof(struct p4tcc_softc),
107 };
108
109 static devclass_t p4tcc_devclass;
110 DRIVER_MODULE(p4tcc, cpu, p4tcc_driver, p4tcc_devclass, 0, 0);
111
112 static int
113 p4tcc_features(driver_t *driver, u_int *features)
114 {
115
116 /* Notify the ACPI CPU that we support direct access to MSRs */
117 *features = ACPI_CAP_THR_MSRS;
118 return (0);
119 }
120
121 static void
122 p4tcc_identify(driver_t *driver, device_t parent)
123 {
124
125 if ((cpu_feature & (CPUID_ACPI | CPUID_TM)) != (CPUID_ACPI | CPUID_TM))
126 return;
127
128 /* Make sure we're not being doubly invoked. */
129 if (device_find_child(parent, "p4tcc", -1) != NULL)
130 return;
131
132 /*
133 * We attach a p4tcc child for every CPU since settings need to
134 * be performed on every CPU in the SMP case. See section 13.15.3
135 * of the IA32 Intel Architecture Software Developer's Manual,
136 * Volume 3, for more info.
137 */
138 if (BUS_ADD_CHILD(parent, 10, "p4tcc", -1) == NULL)
139 device_printf(parent, "add p4tcc child failed\n");
140 }
141
142 static int
143 p4tcc_probe(device_t dev)
144 {
145
146 if (resource_disabled("p4tcc", 0))
147 return (ENXIO);
148
149 device_set_desc(dev, "CPU Frequency Thermal Control");
150 return (0);
151 }
152
153 static int
154 p4tcc_attach(device_t dev)
155 {
156 struct p4tcc_softc *sc;
157 struct cf_setting set;
158
159 sc = device_get_softc(dev);
160 sc->dev = dev;
161 sc->set_count = TCC_NUM_SETTINGS;
162
163 /*
164 * On boot, the TCC is usually in Automatic mode where reading the
165 * current performance level is likely to produce bogus results.
166 * We record that state here and don't trust the contents of the
167 * status MSR until we've set it ourselves.
168 */
169 sc->auto_mode = TRUE;
170
171 /*
172 * XXX: After a cursory glance at various Intel specification
173 * XXX: updates it seems like these tests for errata is bogus.
174 * XXX: As far as I can tell, the failure mode is benign, in
175 * XXX: that cpus with no errata will have their bottom two
176 * XXX: STPCLK# rates disabled, so rather than waste more time
177 * XXX: hunting down intel docs, just document it and punt. /phk
178 */
179 switch (cpu_id & 0xff) {
180 case 0x22:
181 case 0x24:
182 case 0x25:
183 case 0x27:
184 case 0x29:
185 /*
186 * These CPU models hang when set to 12.5%.
187 * See Errata O50, P44, and Z21.
188 */
189 sc->set_count -= 1;
190 break;
191 case 0x07: /* errata N44 and P18 */
192 case 0x0a:
193 case 0x12:
194 case 0x13:
195 case 0x62: /* Pentium D B1: errata AA21 */
196 case 0x64: /* Pentium D C1: errata AA21 */
197 case 0x65: /* Pentium D D0: errata AA21 */
198 /*
199 * These CPU models hang when set to 12.5% or 25%.
200 * See Errata N44, P18l and AA21.
201 */
202 sc->set_count -= 2;
203 break;
204 }
205 sc->lowest_val = TCC_NUM_SETTINGS - sc->set_count + 1;
206
207 /*
208 * Before we finish attach, switch to 100%. It's possible the BIOS
209 * set us to a lower rate. The user can override this after boot.
210 */
211 set.freq = 10000;
212 p4tcc_set(dev, &set);
213
214 cpufreq_register(dev);
215 return (0);
216 }
217
218 static int
219 p4tcc_detach(device_t dev)
220 {
221 struct cf_setting set;
222 int error;
223
224 error = cpufreq_unregister(dev);
225 if (error)
226 return (error);
227
228 /*
229 * Before we finish detach, switch to Automatic mode.
230 */
231 set.freq = 10000;
232 p4tcc_set(dev, &set);
233 return(0);
234 }
235
236 static int
237 p4tcc_settings(device_t dev, struct cf_setting *sets, int *count)
238 {
239 struct p4tcc_softc *sc;
240 int i, val;
241
242 sc = device_get_softc(dev);
243 if (sets == NULL || count == NULL)
244 return (EINVAL);
245 if (*count < sc->set_count)
246 return (E2BIG);
247
248 /* Return a list of valid settings for this driver. */
249 memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * sc->set_count);
250 val = TCC_NUM_SETTINGS;
251 for (i = 0; i < sc->set_count; i++, val--) {
252 sets[i].freq = TCC_SPEED_PERCENT(val);
253 sets[i].dev = dev;
254 }
255 *count = sc->set_count;
256
257 return (0);
258 }
259
260 static int
261 p4tcc_set(device_t dev, const struct cf_setting *set)
262 {
263 struct p4tcc_softc *sc;
264 uint64_t mask, msr;
265 int val;
266
267 if (set == NULL)
268 return (EINVAL);
269 sc = device_get_softc(dev);
270
271 /*
272 * Validate requested state converts to a setting that is an integer
273 * from [sc->lowest_val .. TCC_NUM_SETTINGS].
274 */
275 val = set->freq * TCC_NUM_SETTINGS / 10000;
276 if (val * 10000 != set->freq * TCC_NUM_SETTINGS ||
277 val < sc->lowest_val || val > TCC_NUM_SETTINGS)
278 return (EINVAL);
279
280 /*
281 * Read the current register and mask off the old setting and
282 * On-Demand bit. If the new val is < 100%, set it and the On-Demand
283 * bit, otherwise just return to Automatic mode.
284 */
285 msr = rdmsr(MSR_THERM_CONTROL);
286 mask = (TCC_NUM_SETTINGS - 1) << TCC_REG_OFFSET;
287 msr &= ~(mask | TCC_ENABLE_ONDEMAND);
288 if (val < TCC_NUM_SETTINGS)
289 msr |= (val << TCC_REG_OFFSET) | TCC_ENABLE_ONDEMAND;
290 wrmsr(MSR_THERM_CONTROL, msr);
291
292 /*
293 * Record whether we're now in Automatic or On-Demand mode. We have
294 * to cache this since there is no reliable way to check if TCC is in
295 * Automatic mode (i.e., at 100% or possibly 50%). Reading bit 4 of
296 * the ACPI Thermal Monitor Control Register produces 0 no matter
297 * what the current mode.
298 */
299 if (msr & TCC_ENABLE_ONDEMAND)
300 sc->auto_mode = FALSE;
301 else
302 sc->auto_mode = TRUE;
303
304 return (0);
305 }
306
307 static int
308 p4tcc_get(device_t dev, struct cf_setting *set)
309 {
310 struct p4tcc_softc *sc;
311 uint64_t msr;
312 int val;
313
314 if (set == NULL)
315 return (EINVAL);
316 sc = device_get_softc(dev);
317
318 /*
319 * Read the current register and extract the current setting. If
320 * in automatic mode, assume we're at TCC_NUM_SETTINGS (100%).
321 *
322 * XXX This is not completely reliable since at high temperatures
323 * the CPU may be automatically throttling to 50% but it's the best
324 * we can do.
325 */
326 if (!sc->auto_mode) {
327 msr = rdmsr(MSR_THERM_CONTROL);
328 val = (msr >> TCC_REG_OFFSET) & (TCC_NUM_SETTINGS - 1);
329 } else
330 val = TCC_NUM_SETTINGS;
331
332 memset(set, CPUFREQ_VAL_UNKNOWN, sizeof(*set));
333 set->freq = TCC_SPEED_PERCENT(val);
334 set->dev = dev;
335
336 return (0);
337 }
338
339 static int
340 p4tcc_type(device_t dev, int *type)
341 {
342
343 if (type == NULL)
344 return (EINVAL);
345
346 *type = CPUFREQ_TYPE_RELATIVE;
347 return (0);
348 }
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