Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/x86/cpufreq/smist.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2005 Bruno Ducrot 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /* 28 * This driver is based upon information found by examining speedstep-0.5 29 * from Marc Lehman, which includes all the reverse engineering effort of 30 * Malik Martin (function 1 and 2 of the GSI). 31 * 32 * The correct way for the OS to take ownership from the BIOS was found by 33 * Hiroshi Miura (function 0 of the GSI). 34 * 35 * Finally, the int 15h call interface was (partially) documented by Intel. 36 * 37 * Many thanks to Jon Noack for testing and debugging this driver. 38 */ 39 40 #include <sys/cdefs.h> 41 __FBSDID("$FreeBSD$"); 42 43 #include <sys/param.h> 44 #include <sys/bus.h> 45 #include <sys/cpu.h> 46 #include <sys/kernel.h> 47 #include <sys/module.h> 48 #include <sys/mutex.h> 49 #include <sys/systm.h> 50 51 #include <machine/bus.h> 52 #include <machine/cputypes.h> 53 #include <machine/md_var.h> 54 #include <machine/vm86.h> 55 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcireg.h> 58 59 #include <vm/vm.h> 60 #include <vm/pmap.h> 61 62 #include "cpufreq_if.h" 63 64 #if 0 65 #define DPRINT(dev, x...) device_printf(dev, x) 66 #else 67 #define DPRINT(dev, x...) 68 #endif 69 70 struct smist_softc { 71 device_t dev; 72 int smi_cmd; 73 int smi_data; 74 int command; 75 int flags; 76 struct cf_setting sets[2]; /* Only two settings. */ 77 }; 78 79 static char smist_magic[] = "Copyright (c) 1999 Intel Corporation"; 80 81 static void smist_identify(driver_t *driver, device_t parent); 82 static int smist_probe(device_t dev); 83 static int smist_attach(device_t dev); 84 static int smist_detach(device_t dev); 85 static int smist_settings(device_t dev, struct cf_setting *sets, 86 int *count); 87 static int smist_set(device_t dev, const struct cf_setting *set); 88 static int smist_get(device_t dev, struct cf_setting *set); 89 static int smist_type(device_t dev, int *type); 90 91 static device_method_t smist_methods[] = { 92 /* Device interface */ 93 DEVMETHOD(device_identify, smist_identify), 94 DEVMETHOD(device_probe, smist_probe), 95 DEVMETHOD(device_attach, smist_attach), 96 DEVMETHOD(device_detach, smist_detach), 97 98 /* cpufreq interface */ 99 DEVMETHOD(cpufreq_drv_set, smist_set), 100 DEVMETHOD(cpufreq_drv_get, smist_get), 101 DEVMETHOD(cpufreq_drv_type, smist_type), 102 DEVMETHOD(cpufreq_drv_settings, smist_settings), 103 {0, 0} 104 }; 105 106 static driver_t smist_driver = { 107 "smist", smist_methods, sizeof(struct smist_softc) 108 }; 109 static devclass_t smist_devclass; 110 DRIVER_MODULE(smist, cpu, smist_driver, smist_devclass, 0, 0); 111 112 struct piix4_pci_device { 113 uint16_t vendor; 114 uint16_t device; 115 char *desc; 116 }; 117 118 static struct piix4_pci_device piix4_pci_devices[] = { 119 {0x8086, 0x7113, "Intel PIIX4 ISA bridge"}, 120 {0x8086, 0x719b, "Intel PIIX4 ISA bridge (embedded in MX440 chipset)"}, 121 122 {0, 0, NULL}, 123 }; 124 125 #define SET_OWNERSHIP 0 126 #define GET_STATE 1 127 #define SET_STATE 2 128 129 static int 130 int15_gsic_call(int *sig, int *smi_cmd, int *command, int *smi_data, int *flags) 131 { 132 struct vm86frame vmf; 133 134 bzero(&vmf, sizeof(vmf)); 135 vmf.vmf_eax = 0x0000E980; /* IST support */ 136 vmf.vmf_edx = 0x47534943; /* 'GSIC' in ASCII */ 137 vm86_intcall(0x15, &vmf); 138 139 if (vmf.vmf_eax == 0x47534943) { 140 *sig = vmf.vmf_eax; 141 *smi_cmd = vmf.vmf_ebx & 0xff; 142 *command = (vmf.vmf_ebx >> 16) & 0xff; 143 *smi_data = vmf.vmf_ecx; 144 *flags = vmf.vmf_edx; 145 } else { 146 *sig = -1; 147 *smi_cmd = -1; 148 *command = -1; 149 *smi_data = -1; 150 *flags = -1; 151 } 152 153 return (0); 154 } 155 156 /* Temporary structure to hold mapped page and status. */ 157 struct set_ownership_data { 158 int smi_cmd; 159 int command; 160 int result; 161 void *buf; 162 }; 163 164 /* Perform actual SMI call to enable SpeedStep. */ 165 static void 166 set_ownership_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 167 { 168 struct set_ownership_data *data; 169 170 data = arg; 171 if (error) { 172 data->result = error; 173 return; 174 } 175 176 /* Copy in the magic string and send it by writing to the SMI port. */ 177 strlcpy(data->buf, smist_magic, PAGE_SIZE); 178 __asm __volatile( 179 "movl $-1, %%edi\n\t" 180 "out %%al, (%%dx)\n" 181 : "=D" (data->result) 182 : "a" (data->command), 183 "b" (0), 184 "c" (0), 185 "d" (data->smi_cmd), 186 "S" ((uint32_t)segs[0].ds_addr) 187 ); 188 } 189 190 static int 191 set_ownership(device_t dev) 192 { 193 struct smist_softc *sc; 194 struct set_ownership_data cb_data; 195 bus_dma_tag_t tag; 196 bus_dmamap_t map; 197 198 /* 199 * Specify the region to store the magic string. Since its address is 200 * passed to the BIOS in a 32-bit register, we have to make sure it is 201 * located in a physical page below 4 GB (i.e., for PAE.) 202 */ 203 sc = device_get_softc(dev); 204 if (bus_dma_tag_create(/*parent*/ NULL, 205 /*alignment*/ PAGE_SIZE, /*no boundary*/ 0, 206 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, /*highaddr*/ BUS_SPACE_MAXADDR, 207 NULL, NULL, /*maxsize*/ PAGE_SIZE, /*segments*/ 1, 208 /*maxsegsize*/ PAGE_SIZE, 0, busdma_lock_mutex, &Giant, 209 &tag) != 0) { 210 device_printf(dev, "can't create mem tag\n"); 211 return (ENXIO); 212 } 213 if (bus_dmamem_alloc(tag, &cb_data.buf, BUS_DMA_NOWAIT, &map) != 0) { 214 bus_dma_tag_destroy(tag); 215 device_printf(dev, "can't alloc mapped mem\n"); 216 return (ENXIO); 217 } 218 219 /* Load the physical page map and take ownership in the callback. */ 220 cb_data.smi_cmd = sc->smi_cmd; 221 cb_data.command = sc->command; 222 if (bus_dmamap_load(tag, map, cb_data.buf, PAGE_SIZE, set_ownership_cb, 223 &cb_data, BUS_DMA_NOWAIT) != 0) { 224 bus_dmamem_free(tag, cb_data.buf, map); 225 bus_dma_tag_destroy(tag); 226 device_printf(dev, "can't load mem\n"); 227 return (ENXIO); 228 } 229 DPRINT(dev, "taking ownership over BIOS return %d\n", cb_data.result); 230 bus_dmamap_unload(tag, map); 231 bus_dmamem_free(tag, cb_data.buf, map); 232 bus_dma_tag_destroy(tag); 233 return (cb_data.result ? ENXIO : 0); 234 } 235 236 static int 237 getset_state(struct smist_softc *sc, int *state, int function) 238 { 239 int new_state; 240 int result; 241 int eax; 242 243 if (!sc) 244 return (ENXIO); 245 246 if (function != GET_STATE && function != SET_STATE) 247 return (EINVAL); 248 249 DPRINT(sc->dev, "calling GSI\n"); 250 251 __asm __volatile( 252 "movl $-1, %%edi\n\t" 253 "out %%al, (%%dx)\n" 254 : "=a" (eax), 255 "=b" (new_state), 256 "=D" (result) 257 : "a" (sc->command), 258 "b" (function), 259 "c" (*state), 260 "d" (sc->smi_cmd) 261 ); 262 263 DPRINT(sc->dev, "GSI returned: eax %.8x ebx %.8x edi %.8x\n", 264 eax, new_state, result); 265 266 *state = new_state & 1; 267 268 switch (function) { 269 case GET_STATE: 270 if (eax) 271 return (ENXIO); 272 break; 273 case SET_STATE: 274 if (result) 275 return (ENXIO); 276 break; 277 } 278 return (0); 279 } 280 281 static void 282 smist_identify(driver_t *driver, device_t parent) 283 { 284 struct piix4_pci_device *id; 285 device_t piix4 = NULL; 286 287 if (resource_disabled("ichst", 0)) 288 return; 289 290 /* Check for a supported processor */ 291 if (cpu_vendor_id != CPU_VENDOR_INTEL) 292 return; 293 switch (cpu_id & 0xff0) { 294 case 0x680: /* Pentium III [coppermine] */ 295 case 0x6a0: /* Pentium III [Tualatin] */ 296 break; 297 default: 298 return; 299 } 300 301 /* Check for a supported PCI-ISA bridge */ 302 for (id = piix4_pci_devices; id->desc != NULL; ++id) { 303 if ((piix4 = pci_find_device(id->vendor, id->device)) != NULL) 304 break; 305 } 306 if (!piix4) 307 return; 308 309 if (bootverbose) 310 printf("smist: found supported isa bridge %s\n", id->desc); 311 312 if (device_find_child(parent, "smist", -1) != NULL) 313 return; 314 if (BUS_ADD_CHILD(parent, 30, "smist", -1) == NULL) 315 device_printf(parent, "smist: add child failed\n"); 316 } 317 318 static int 319 smist_probe(device_t dev) 320 { 321 struct smist_softc *sc; 322 device_t ichss_dev, perf_dev; 323 int sig, smi_cmd, command, smi_data, flags; 324 int type; 325 int rv; 326 327 if (resource_disabled("smist", 0)) 328 return (ENXIO); 329 330 sc = device_get_softc(dev); 331 332 /* 333 * If the ACPI perf or ICH SpeedStep drivers have attached and not 334 * just offering info, let them manage things. 335 */ 336 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 337 if (perf_dev && device_is_attached(perf_dev)) { 338 rv = CPUFREQ_DRV_TYPE(perf_dev, &type); 339 if (rv == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0) 340 return (ENXIO); 341 } 342 ichss_dev = device_find_child(device_get_parent(dev), "ichss", -1); 343 if (ichss_dev && device_is_attached(ichss_dev)) 344 return (ENXIO); 345 346 int15_gsic_call(&sig, &smi_cmd, &command, &smi_data, &flags); 347 if (bootverbose) 348 device_printf(dev, "sig %.8x smi_cmd %.4x command %.2x " 349 "smi_data %.4x flags %.8x\n", 350 sig, smi_cmd, command, smi_data, flags); 351 352 if (sig != -1) { 353 sc->smi_cmd = smi_cmd; 354 sc->smi_data = smi_data; 355 356 /* 357 * Sometimes int 15h 'GSIC' returns 0x80 for command, when 358 * it is actually 0x82. The Windows driver will overwrite 359 * this value given by the registry. 360 */ 361 if (command == 0x80) { 362 device_printf(dev, 363 "GSIC returned cmd 0x80, should be 0x82\n"); 364 command = 0x82; 365 } 366 sc->command = (sig & 0xffffff00) | (command & 0xff); 367 sc->flags = flags; 368 } else { 369 /* Give some default values */ 370 sc->smi_cmd = 0xb2; 371 sc->smi_data = 0xb3; 372 sc->command = 0x47534982; 373 sc->flags = 0; 374 } 375 376 device_set_desc(dev, "SpeedStep SMI"); 377 378 return (-1500); 379 } 380 381 static int 382 smist_attach(device_t dev) 383 { 384 struct smist_softc *sc; 385 386 sc = device_get_softc(dev); 387 sc->dev = dev; 388 389 /* If we can't take ownership over BIOS, then bail out */ 390 if (set_ownership(dev) != 0) 391 return (ENXIO); 392 393 /* Setup some defaults for our exported settings. */ 394 sc->sets[0].freq = CPUFREQ_VAL_UNKNOWN; 395 sc->sets[0].volts = CPUFREQ_VAL_UNKNOWN; 396 sc->sets[0].power = CPUFREQ_VAL_UNKNOWN; 397 sc->sets[0].lat = 1000; 398 sc->sets[0].dev = dev; 399 sc->sets[1] = sc->sets[0]; 400 401 cpufreq_register(dev); 402 403 return (0); 404 } 405 406 static int 407 smist_detach(device_t dev) 408 { 409 410 return (cpufreq_unregister(dev)); 411 } 412 413 static int 414 smist_settings(device_t dev, struct cf_setting *sets, int *count) 415 { 416 struct smist_softc *sc; 417 struct cf_setting set; 418 int first, i; 419 420 if (sets == NULL || count == NULL) 421 return (EINVAL); 422 if (*count < 2) { 423 *count = 2; 424 return (E2BIG); 425 } 426 sc = device_get_softc(dev); 427 428 /* 429 * Estimate frequencies for both levels, temporarily switching to 430 * the other one if we haven't calibrated it yet. 431 */ 432 for (i = 0; i < 2; i++) { 433 if (sc->sets[i].freq == CPUFREQ_VAL_UNKNOWN) { 434 first = (i == 0) ? 1 : 0; 435 smist_set(dev, &sc->sets[i]); 436 smist_get(dev, &set); 437 smist_set(dev, &sc->sets[first]); 438 } 439 } 440 441 bcopy(sc->sets, sets, sizeof(sc->sets)); 442 *count = 2; 443 444 return (0); 445 } 446 447 static int 448 smist_set(device_t dev, const struct cf_setting *set) 449 { 450 struct smist_softc *sc; 451 int rv, state, req_state, try; 452 453 /* Look up appropriate bit value based on frequency. */ 454 sc = device_get_softc(dev); 455 if (CPUFREQ_CMP(set->freq, sc->sets[0].freq)) 456 req_state = 0; 457 else if (CPUFREQ_CMP(set->freq, sc->sets[1].freq)) 458 req_state = 1; 459 else 460 return (EINVAL); 461 462 DPRINT(dev, "requested setting %d\n", req_state); 463 464 rv = getset_state(sc, &state, GET_STATE); 465 if (state == req_state) 466 return (0); 467 468 try = 3; 469 do { 470 rv = getset_state(sc, &req_state, SET_STATE); 471 472 /* Sleep for 200 microseconds. This value is just a guess. */ 473 if (rv) 474 DELAY(200); 475 } while (rv && --try); 476 DPRINT(dev, "set_state return %d, tried %d times\n", 477 rv, 4 - try); 478 479 return (rv); 480 } 481 482 static int 483 smist_get(device_t dev, struct cf_setting *set) 484 { 485 struct smist_softc *sc; 486 uint64_t rate; 487 int state; 488 int rv; 489 490 sc = device_get_softc(dev); 491 rv = getset_state(sc, &state, GET_STATE); 492 if (rv != 0) 493 return (rv); 494 495 /* If we haven't changed settings yet, estimate the current value. */ 496 if (sc->sets[state].freq == CPUFREQ_VAL_UNKNOWN) { 497 cpu_est_clockrate(0, &rate); 498 sc->sets[state].freq = rate / 1000000; 499 DPRINT(dev, "get calibrated new rate of %d\n", 500 sc->sets[state].freq); 501 } 502 *set = sc->sets[state]; 503 504 return (0); 505 } 506 507 static int 508 smist_type(device_t dev, int *type) 509 { 510 511 if (type == NULL) 512 return (EINVAL); 513 514 *type = CPUFREQ_TYPE_ABSOLUTE; 515 return (0); 516 }
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