1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 1996, by Peter Wemm and Steve Passe
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. The name of the developer may NOT be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: releng/12.0/sys/x86/include/apicreg.h 326263 2017-11-27 15:11:47Z pfg $
28 */
29
30 #ifndef _X86_APICREG_H_
31 #define _X86_APICREG_H_
32
33 /*
34 * Local && I/O APIC definitions.
35 */
36
37 /*
38 * Pentium P54C+ Built-in APIC
39 * (Advanced programmable Interrupt Controller)
40 *
41 * Base Address of Built-in APIC in memory location
42 * is 0xfee00000.
43 *
44 * Map of APIC Registers:
45 *
46 * Offset (hex) Description Read/Write state
47 * 000 Reserved
48 * 010 Reserved
49 * 020 ID Local APIC ID R/W
50 * 030 VER Local APIC Version R
51 * 040 Reserved
52 * 050 Reserved
53 * 060 Reserved
54 * 070 Reserved
55 * 080 Task Priority Register R/W
56 * 090 Arbitration Priority Register R
57 * 0A0 Processor Priority Register R
58 * 0B0 EOI Register W
59 * 0C0 RRR Remote read R
60 * 0D0 Logical Destination R/W
61 * 0E0 Destination Format Register 0..27 R; 28..31 R/W
62 * 0F0 SVR Spurious Interrupt Vector Reg. 0..3 R; 4..9 R/W
63 * 100 ISR 000-031 R
64 * 110 ISR 032-063 R
65 * 120 ISR 064-095 R
66 * 130 ISR 095-128 R
67 * 140 ISR 128-159 R
68 * 150 ISR 160-191 R
69 * 160 ISR 192-223 R
70 * 170 ISR 224-255 R
71 * 180 TMR 000-031 R
72 * 190 TMR 032-063 R
73 * 1A0 TMR 064-095 R
74 * 1B0 TMR 095-128 R
75 * 1C0 TMR 128-159 R
76 * 1D0 TMR 160-191 R
77 * 1E0 TMR 192-223 R
78 * 1F0 TMR 224-255 R
79 * 200 IRR 000-031 R
80 * 210 IRR 032-063 R
81 * 220 IRR 064-095 R
82 * 230 IRR 095-128 R
83 * 240 IRR 128-159 R
84 * 250 IRR 160-191 R
85 * 260 IRR 192-223 R
86 * 270 IRR 224-255 R
87 * 280 Error Status Register R
88 * 290 Reserved
89 * 2A0 Reserved
90 * 2B0 Reserved
91 * 2C0 Reserved
92 * 2D0 Reserved
93 * 2E0 Reserved
94 * 2F0 Local Vector Table (CMCI) R/W
95 * 300 ICR_LOW Interrupt Command Reg. (0-31) R/W
96 * 310 ICR_HI Interrupt Command Reg. (32-63) R/W
97 * 320 Local Vector Table (Timer) R/W
98 * 330 Local Vector Table (Thermal) R/W (PIV+)
99 * 340 Local Vector Table (Performance) R/W (P6+)
100 * 350 LVT1 Local Vector Table (LINT0) R/W
101 * 360 LVT2 Local Vector Table (LINT1) R/W
102 * 370 LVT3 Local Vector Table (ERROR) R/W
103 * 380 Initial Count Reg. for Timer R/W
104 * 390 Current Count of Timer R
105 * 3A0 Reserved
106 * 3B0 Reserved
107 * 3C0 Reserved
108 * 3D0 Reserved
109 * 3E0 Timer Divide Configuration Reg. R/W
110 * 3F0 Reserved
111 */
112
113
114 /******************************************************************************
115 * global defines, etc.
116 */
117
118
119 /******************************************************************************
120 * LOCAL APIC structure
121 */
122
123 #ifndef LOCORE
124 #include <sys/types.h>
125
126 #define PAD3 int : 32; int : 32; int : 32
127 #define PAD4 int : 32; int : 32; int : 32; int : 32
128
129 struct LAPIC {
130 /* reserved */ PAD4;
131 /* reserved */ PAD4;
132 u_int32_t id; PAD3;
133 u_int32_t version; PAD3;
134 /* reserved */ PAD4;
135 /* reserved */ PAD4;
136 /* reserved */ PAD4;
137 /* reserved */ PAD4;
138 u_int32_t tpr; PAD3;
139 u_int32_t apr; PAD3;
140 u_int32_t ppr; PAD3;
141 u_int32_t eoi; PAD3;
142 /* reserved */ PAD4;
143 u_int32_t ldr; PAD3;
144 u_int32_t dfr; PAD3;
145 u_int32_t svr; PAD3;
146 u_int32_t isr0; PAD3;
147 u_int32_t isr1; PAD3;
148 u_int32_t isr2; PAD3;
149 u_int32_t isr3; PAD3;
150 u_int32_t isr4; PAD3;
151 u_int32_t isr5; PAD3;
152 u_int32_t isr6; PAD3;
153 u_int32_t isr7; PAD3;
154 u_int32_t tmr0; PAD3;
155 u_int32_t tmr1; PAD3;
156 u_int32_t tmr2; PAD3;
157 u_int32_t tmr3; PAD3;
158 u_int32_t tmr4; PAD3;
159 u_int32_t tmr5; PAD3;
160 u_int32_t tmr6; PAD3;
161 u_int32_t tmr7; PAD3;
162 u_int32_t irr0; PAD3;
163 u_int32_t irr1; PAD3;
164 u_int32_t irr2; PAD3;
165 u_int32_t irr3; PAD3;
166 u_int32_t irr4; PAD3;
167 u_int32_t irr5; PAD3;
168 u_int32_t irr6; PAD3;
169 u_int32_t irr7; PAD3;
170 u_int32_t esr; PAD3;
171 /* reserved */ PAD4;
172 /* reserved */ PAD4;
173 /* reserved */ PAD4;
174 /* reserved */ PAD4;
175 /* reserved */ PAD4;
176 /* reserved */ PAD4;
177 u_int32_t lvt_cmci; PAD3;
178 u_int32_t icr_lo; PAD3;
179 u_int32_t icr_hi; PAD3;
180 u_int32_t lvt_timer; PAD3;
181 u_int32_t lvt_thermal; PAD3;
182 u_int32_t lvt_pcint; PAD3;
183 u_int32_t lvt_lint0; PAD3;
184 u_int32_t lvt_lint1; PAD3;
185 u_int32_t lvt_error; PAD3;
186 u_int32_t icr_timer; PAD3;
187 u_int32_t ccr_timer; PAD3;
188 /* reserved */ PAD4;
189 /* reserved */ PAD4;
190 /* reserved */ PAD4;
191 /* reserved */ PAD4;
192 u_int32_t dcr_timer; PAD3;
193 /* reserved */ PAD4;
194 };
195
196 typedef struct LAPIC lapic_t;
197
198 enum LAPIC_REGISTERS {
199 LAPIC_ID = 0x2,
200 LAPIC_VERSION = 0x3,
201 LAPIC_TPR = 0x8,
202 LAPIC_APR = 0x9,
203 LAPIC_PPR = 0xa,
204 LAPIC_EOI = 0xb,
205 LAPIC_LDR = 0xd,
206 LAPIC_DFR = 0xe, /* Not in x2APIC */
207 LAPIC_SVR = 0xf,
208 LAPIC_ISR0 = 0x10,
209 LAPIC_ISR1 = 0x11,
210 LAPIC_ISR2 = 0x12,
211 LAPIC_ISR3 = 0x13,
212 LAPIC_ISR4 = 0x14,
213 LAPIC_ISR5 = 0x15,
214 LAPIC_ISR6 = 0x16,
215 LAPIC_ISR7 = 0x17,
216 LAPIC_TMR0 = 0x18,
217 LAPIC_TMR1 = 0x19,
218 LAPIC_TMR2 = 0x1a,
219 LAPIC_TMR3 = 0x1b,
220 LAPIC_TMR4 = 0x1c,
221 LAPIC_TMR5 = 0x1d,
222 LAPIC_TMR6 = 0x1e,
223 LAPIC_TMR7 = 0x1f,
224 LAPIC_IRR0 = 0x20,
225 LAPIC_IRR1 = 0x21,
226 LAPIC_IRR2 = 0x22,
227 LAPIC_IRR3 = 0x23,
228 LAPIC_IRR4 = 0x24,
229 LAPIC_IRR5 = 0x25,
230 LAPIC_IRR6 = 0x26,
231 LAPIC_IRR7 = 0x27,
232 LAPIC_ESR = 0x28,
233 LAPIC_LVT_CMCI = 0x2f,
234 LAPIC_ICR_LO = 0x30,
235 LAPIC_ICR_HI = 0x31, /* Not in x2APIC */
236 LAPIC_LVT_TIMER = 0x32,
237 LAPIC_LVT_THERMAL = 0x33,
238 LAPIC_LVT_PCINT = 0x34,
239 LAPIC_LVT_LINT0 = 0x35,
240 LAPIC_LVT_LINT1 = 0x36,
241 LAPIC_LVT_ERROR = 0x37,
242 LAPIC_ICR_TIMER = 0x38,
243 LAPIC_CCR_TIMER = 0x39,
244 LAPIC_DCR_TIMER = 0x3e,
245 LAPIC_SELF_IPI = 0x3f, /* Only in x2APIC */
246 LAPIC_EXT_FEATURES = 0x40, /* AMD */
247 LAPIC_EXT_CTRL = 0x41, /* AMD */
248 LAPIC_EXT_SEOI = 0x42, /* AMD */
249 LAPIC_EXT_IER0 = 0x48, /* AMD */
250 LAPIC_EXT_IER1 = 0x49, /* AMD */
251 LAPIC_EXT_IER2 = 0x4a, /* AMD */
252 LAPIC_EXT_IER3 = 0x4b, /* AMD */
253 LAPIC_EXT_IER4 = 0x4c, /* AMD */
254 LAPIC_EXT_IER5 = 0x4d, /* AMD */
255 LAPIC_EXT_IER6 = 0x4e, /* AMD */
256 LAPIC_EXT_IER7 = 0x4f, /* AMD */
257 LAPIC_EXT_LVT0 = 0x50, /* AMD */
258 LAPIC_EXT_LVT1 = 0x51, /* AMD */
259 LAPIC_EXT_LVT2 = 0x52, /* AMD */
260 LAPIC_EXT_LVT3 = 0x53, /* AMD */
261 };
262
263 #define LAPIC_MEM_MUL 0x10
264
265 /*
266 * Although some registers are available on AMD processors only,
267 * it's not a big waste to reserve them on all platforms.
268 * However, we need to watch out for this space being assigned for
269 * non-APIC purposes in the future processor models.
270 */
271 #define LAPIC_MEM_REGION ((LAPIC_EXT_LVT3 + 1) * LAPIC_MEM_MUL)
272
273 /******************************************************************************
274 * I/O APIC structure
275 */
276
277 struct IOAPIC {
278 u_int32_t ioregsel; PAD3;
279 u_int32_t iowin; PAD3;
280 };
281
282 typedef struct IOAPIC ioapic_t;
283
284 #undef PAD4
285 #undef PAD3
286
287 #endif /* !LOCORE */
288
289
290 /******************************************************************************
291 * various code 'logical' values
292 */
293
294 /******************************************************************************
295 * LOCAL APIC defines
296 */
297
298 /* default physical locations of LOCAL (CPU) APICs */
299 #define DEFAULT_APIC_BASE 0xfee00000
300
301 /* constants relating to APIC ID registers */
302 #define APIC_ID_MASK 0xff000000
303 #define APIC_ID_SHIFT 24
304 #define APIC_ID_CLUSTER 0xf0
305 #define APIC_ID_CLUSTER_ID 0x0f
306 #define APIC_MAX_CLUSTER 0xe
307 #define APIC_MAX_INTRACLUSTER_ID 3
308 #define APIC_ID_CLUSTER_SHIFT 4
309
310 /* fields in VER */
311 #define APIC_VER_VERSION 0x000000ff
312 #define APIC_VER_MAXLVT 0x00ff0000
313 #define MAXLVTSHIFT 16
314 #define APIC_VER_EOI_SUPPRESSION 0x01000000
315 #define APIC_VER_AMD_EXT_SPACE 0x80000000
316
317 /* fields in LDR */
318 #define APIC_LDR_RESERVED 0x00ffffff
319
320 /* fields in DFR */
321 #define APIC_DFR_RESERVED 0x0fffffff
322 #define APIC_DFR_MODEL_MASK 0xf0000000
323 #define APIC_DFR_MODEL_FLAT 0xf0000000
324 #define APIC_DFR_MODEL_CLUSTER 0x00000000
325
326 /* fields in SVR */
327 #define APIC_SVR_VECTOR 0x000000ff
328 #define APIC_SVR_VEC_PROG 0x000000f0
329 #define APIC_SVR_VEC_FIX 0x0000000f
330 #define APIC_SVR_ENABLE 0x00000100
331 # define APIC_SVR_SWDIS 0x00000000
332 # define APIC_SVR_SWEN 0x00000100
333 #define APIC_SVR_FOCUS 0x00000200
334 # define APIC_SVR_FEN 0x00000000
335 # define APIC_SVR_FDIS 0x00000200
336 #define APIC_SVR_EOI_SUPPRESSION 0x00001000
337
338 /* fields in TPR */
339 #define APIC_TPR_PRIO 0x000000ff
340 # define APIC_TPR_INT 0x000000f0
341 # define APIC_TPR_SUB 0x0000000f
342
343 /* fields in ESR */
344 #define APIC_ESR_SEND_CS_ERROR 0x00000001
345 #define APIC_ESR_RECEIVE_CS_ERROR 0x00000002
346 #define APIC_ESR_SEND_ACCEPT 0x00000004
347 #define APIC_ESR_RECEIVE_ACCEPT 0x00000008
348 #define APIC_ESR_SEND_ILLEGAL_VECTOR 0x00000020
349 #define APIC_ESR_RECEIVE_ILLEGAL_VECTOR 0x00000040
350 #define APIC_ESR_ILLEGAL_REGISTER 0x00000080
351
352 /* fields in ICR_LOW */
353 #define APIC_VECTOR_MASK 0x000000ff
354
355 #define APIC_DELMODE_MASK 0x00000700
356 # define APIC_DELMODE_FIXED 0x00000000
357 # define APIC_DELMODE_LOWPRIO 0x00000100
358 # define APIC_DELMODE_SMI 0x00000200
359 # define APIC_DELMODE_RR 0x00000300
360 # define APIC_DELMODE_NMI 0x00000400
361 # define APIC_DELMODE_INIT 0x00000500
362 # define APIC_DELMODE_STARTUP 0x00000600
363 # define APIC_DELMODE_RESV 0x00000700
364
365 #define APIC_DESTMODE_MASK 0x00000800
366 # define APIC_DESTMODE_PHY 0x00000000
367 # define APIC_DESTMODE_LOG 0x00000800
368
369 #define APIC_DELSTAT_MASK 0x00001000
370 # define APIC_DELSTAT_IDLE 0x00000000
371 # define APIC_DELSTAT_PEND 0x00001000
372
373 #define APIC_RESV1_MASK 0x00002000
374
375 #define APIC_LEVEL_MASK 0x00004000
376 # define APIC_LEVEL_DEASSERT 0x00000000
377 # define APIC_LEVEL_ASSERT 0x00004000
378
379 #define APIC_TRIGMOD_MASK 0x00008000
380 # define APIC_TRIGMOD_EDGE 0x00000000
381 # define APIC_TRIGMOD_LEVEL 0x00008000
382
383 #define APIC_RRSTAT_MASK 0x00030000
384 # define APIC_RRSTAT_INVALID 0x00000000
385 # define APIC_RRSTAT_INPROG 0x00010000
386 # define APIC_RRSTAT_VALID 0x00020000
387 # define APIC_RRSTAT_RESV 0x00030000
388
389 #define APIC_DEST_MASK 0x000c0000
390 # define APIC_DEST_DESTFLD 0x00000000
391 # define APIC_DEST_SELF 0x00040000
392 # define APIC_DEST_ALLISELF 0x00080000
393 # define APIC_DEST_ALLESELF 0x000c0000
394
395 #define APIC_RESV2_MASK 0xfff00000
396
397 #define APIC_ICRLO_RESV_MASK (APIC_RESV1_MASK | APIC_RESV2_MASK)
398
399 /* fields in LVT1/2 */
400 #define APIC_LVT_VECTOR 0x000000ff
401 #define APIC_LVT_DM 0x00000700
402 # define APIC_LVT_DM_FIXED 0x00000000
403 # define APIC_LVT_DM_SMI 0x00000200
404 # define APIC_LVT_DM_NMI 0x00000400
405 # define APIC_LVT_DM_INIT 0x00000500
406 # define APIC_LVT_DM_EXTINT 0x00000700
407 #define APIC_LVT_DS 0x00001000
408 #define APIC_LVT_IIPP 0x00002000
409 #define APIC_LVT_IIPP_INTALO 0x00002000
410 #define APIC_LVT_IIPP_INTAHI 0x00000000
411 #define APIC_LVT_RIRR 0x00004000
412 #define APIC_LVT_TM 0x00008000
413 #define APIC_LVT_M 0x00010000
414
415
416 /* fields in LVT Timer */
417 #define APIC_LVTT_VECTOR 0x000000ff
418 #define APIC_LVTT_DS 0x00001000
419 #define APIC_LVTT_M 0x00010000
420 #define APIC_LVTT_TM 0x00060000
421 # define APIC_LVTT_TM_ONE_SHOT 0x00000000
422 # define APIC_LVTT_TM_PERIODIC 0x00020000
423 # define APIC_LVTT_TM_TSCDLT 0x00040000
424 # define APIC_LVTT_TM_RSRV 0x00060000
425
426 /* APIC timer current count */
427 #define APIC_TIMER_MAX_COUNT 0xffffffff
428
429 /* fields in TDCR */
430 #define APIC_TDCR_2 0x00
431 #define APIC_TDCR_4 0x01
432 #define APIC_TDCR_8 0x02
433 #define APIC_TDCR_16 0x03
434 #define APIC_TDCR_32 0x08
435 #define APIC_TDCR_64 0x09
436 #define APIC_TDCR_128 0x0a
437 #define APIC_TDCR_1 0x0b
438
439 /* Constants related to AMD Extended APIC Features Register */
440 #define APIC_EXTF_ELVT_MASK 0x00ff0000
441 #define APIC_EXTF_ELVT_SHIFT 16
442 #define APIC_EXTF_EXTID_CAP 0x00000004
443 #define APIC_EXTF_SEIO_CAP 0x00000002
444 #define APIC_EXTF_IER_CAP 0x00000001
445
446 /* LVT table indices */
447 #define APIC_LVT_LINT0 0
448 #define APIC_LVT_LINT1 1
449 #define APIC_LVT_TIMER 2
450 #define APIC_LVT_ERROR 3
451 #define APIC_LVT_PMC 4
452 #define APIC_LVT_THERMAL 5
453 #define APIC_LVT_CMCI 6
454 #define APIC_LVT_MAX APIC_LVT_CMCI
455
456 /* AMD extended LVT constants, seem to be assigned by fiat */
457 #define APIC_ELVT_IBS 0 /* Instruction based sampling */
458 #define APIC_ELVT_MCA 1 /* MCE thresholding */
459 #define APIC_ELVT_DEI 2 /* Deferred error interrupt */
460 #define APIC_ELVT_SBI 3 /* Sideband interface */
461 #define APIC_ELVT_MAX APIC_ELVT_SBI
462
463 /******************************************************************************
464 * I/O APIC defines
465 */
466
467 /* default physical locations of an IO APIC */
468 #define DEFAULT_IO_APIC_BASE 0xfec00000
469
470 /* window register offset */
471 #define IOAPIC_WINDOW 0x10
472 #define IOAPIC_EOIR 0x40
473
474 #define IOAPIC_WND_SIZE 0x50
475
476 /* indexes into IO APIC */
477 #define IOAPIC_ID 0x00
478 #define IOAPIC_VER 0x01
479 #define IOAPIC_ARB 0x02
480 #define IOAPIC_REDTBL 0x10
481 #define IOAPIC_REDTBL0 IOAPIC_REDTBL
482 #define IOAPIC_REDTBL1 (IOAPIC_REDTBL+0x02)
483 #define IOAPIC_REDTBL2 (IOAPIC_REDTBL+0x04)
484 #define IOAPIC_REDTBL3 (IOAPIC_REDTBL+0x06)
485 #define IOAPIC_REDTBL4 (IOAPIC_REDTBL+0x08)
486 #define IOAPIC_REDTBL5 (IOAPIC_REDTBL+0x0a)
487 #define IOAPIC_REDTBL6 (IOAPIC_REDTBL+0x0c)
488 #define IOAPIC_REDTBL7 (IOAPIC_REDTBL+0x0e)
489 #define IOAPIC_REDTBL8 (IOAPIC_REDTBL+0x10)
490 #define IOAPIC_REDTBL9 (IOAPIC_REDTBL+0x12)
491 #define IOAPIC_REDTBL10 (IOAPIC_REDTBL+0x14)
492 #define IOAPIC_REDTBL11 (IOAPIC_REDTBL+0x16)
493 #define IOAPIC_REDTBL12 (IOAPIC_REDTBL+0x18)
494 #define IOAPIC_REDTBL13 (IOAPIC_REDTBL+0x1a)
495 #define IOAPIC_REDTBL14 (IOAPIC_REDTBL+0x1c)
496 #define IOAPIC_REDTBL15 (IOAPIC_REDTBL+0x1e)
497 #define IOAPIC_REDTBL16 (IOAPIC_REDTBL+0x20)
498 #define IOAPIC_REDTBL17 (IOAPIC_REDTBL+0x22)
499 #define IOAPIC_REDTBL18 (IOAPIC_REDTBL+0x24)
500 #define IOAPIC_REDTBL19 (IOAPIC_REDTBL+0x26)
501 #define IOAPIC_REDTBL20 (IOAPIC_REDTBL+0x28)
502 #define IOAPIC_REDTBL21 (IOAPIC_REDTBL+0x2a)
503 #define IOAPIC_REDTBL22 (IOAPIC_REDTBL+0x2c)
504 #define IOAPIC_REDTBL23 (IOAPIC_REDTBL+0x2e)
505
506 /* fields in VER */
507 #define IOART_VER_VERSION 0x000000ff
508 #define IOART_VER_MAXREDIR 0x00ff0000
509 #define MAXREDIRSHIFT 16
510
511 /*
512 * fields in the IO APIC's redirection table entries
513 */
514 #define IOART_DEST APIC_ID_MASK /* broadcast addr: all APICs */
515
516 #define IOART_RESV 0x00fe0000 /* reserved */
517
518 #define IOART_INTMASK 0x00010000 /* R/W: INTerrupt mask */
519 # define IOART_INTMCLR 0x00000000 /* clear, allow INTs */
520 # define IOART_INTMSET 0x00010000 /* set, inhibit INTs */
521
522 #define IOART_TRGRMOD 0x00008000 /* R/W: trigger mode */
523 # define IOART_TRGREDG 0x00000000 /* edge */
524 # define IOART_TRGRLVL 0x00008000 /* level */
525
526 #define IOART_REM_IRR 0x00004000 /* RO: remote IRR */
527
528 #define IOART_INTPOL 0x00002000 /* R/W: INT input pin polarity */
529 # define IOART_INTAHI 0x00000000 /* active high */
530 # define IOART_INTALO 0x00002000 /* active low */
531
532 #define IOART_DELIVS 0x00001000 /* RO: delivery status */
533
534 #define IOART_DESTMOD 0x00000800 /* R/W: destination mode */
535 # define IOART_DESTPHY 0x00000000 /* physical */
536 # define IOART_DESTLOG 0x00000800 /* logical */
537
538 #define IOART_DELMOD 0x00000700 /* R/W: delivery mode */
539 # define IOART_DELFIXED 0x00000000 /* fixed */
540 # define IOART_DELLOPRI 0x00000100 /* lowest priority */
541 # define IOART_DELSMI 0x00000200 /* System Management INT */
542 # define IOART_DELRSV1 0x00000300 /* reserved */
543 # define IOART_DELNMI 0x00000400 /* NMI signal */
544 # define IOART_DELINIT 0x00000500 /* INIT signal */
545 # define IOART_DELRSV2 0x00000600 /* reserved */
546 # define IOART_DELEXINT 0x00000700 /* External INTerrupt */
547
548 #define IOART_INTVEC 0x000000ff /* R/W: INTerrupt vector field */
549
550 #endif /* _X86_APICREG_H_ */
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