1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD: releng/12.0/sys/x86/include/intr_machdep.h 338360 2018-08-28 21:09:19Z jhb $
29 */
30
31 #ifndef __X86_INTR_MACHDEP_H__
32 #define __X86_INTR_MACHDEP_H__
33
34 #ifdef _KERNEL
35
36 /*
37 * Values used in determining the allocation of IRQ values among
38 * different types of I/O interrupts. These values are used as
39 * indices into a interrupt source array to map I/O interrupts to a
40 * device interrupt source whether it be a pin on an interrupt
41 * controller or an MSI interrupt. The 16 ISA IRQs are assigned fixed
42 * IDT vectors, but all other device interrupts allocate IDT vectors
43 * on demand. Currently we have 191 IDT vectors available for device
44 * interrupts on each CPU. On many systems with I/O APICs, a lot of
45 * the IRQs are not used, so the total number of IRQ values reserved
46 * can exceed the number of available IDT slots.
47 *
48 * The first 16 IRQs (0 - 15) are reserved for ISA IRQs. Interrupt
49 * pins on I/O APICs for non-ISA interrupts use IRQ values starting at
50 * IRQ 17. This layout matches the GSI numbering used by ACPI so that
51 * IRQ values returned by ACPI methods such as _CRS can be used
52 * directly by the ACPI bus driver.
53 *
54 * MSI interrupts allocate a block of interrupts starting at either
55 * the end of the I/O APIC range or 256, whichever is higher. When
56 * running under the Xen Hypervisor, an additional range of IRQ values
57 * are available for binding to event channel events. We use 256 as
58 * the minimum IRQ value for MSI interrupts to attempt to leave 255
59 * unused since 255 is used in PCI to indicate an invalid INTx IRQ.
60 */
61 #define NUM_MSI_INTS 512
62 #define MINIMUM_MSI_INT 256
63
64 extern u_int first_msi_irq;
65 extern u_int num_io_irqs;
66
67 /*
68 * Default base address for MSI messages on x86 platforms.
69 */
70 #define MSI_INTEL_ADDR_BASE 0xfee00000
71
72 #ifndef LOCORE
73
74 typedef void inthand_t(void);
75
76 #define IDTVEC(name) __CONCAT(X,name)
77
78 struct intsrc;
79
80 /*
81 * Methods that a PIC provides to mask/unmask a given interrupt source,
82 * "turn on" the interrupt on the CPU side by setting up an IDT entry, and
83 * return the vector associated with this source.
84 */
85 struct pic {
86 void (*pic_register_sources)(struct pic *);
87 void (*pic_enable_source)(struct intsrc *);
88 void (*pic_disable_source)(struct intsrc *, int);
89 void (*pic_eoi_source)(struct intsrc *);
90 void (*pic_enable_intr)(struct intsrc *);
91 void (*pic_disable_intr)(struct intsrc *);
92 int (*pic_vector)(struct intsrc *);
93 int (*pic_source_pending)(struct intsrc *);
94 void (*pic_suspend)(struct pic *);
95 void (*pic_resume)(struct pic *, bool suspend_cancelled);
96 int (*pic_config_intr)(struct intsrc *, enum intr_trigger,
97 enum intr_polarity);
98 int (*pic_assign_cpu)(struct intsrc *, u_int apic_id);
99 void (*pic_reprogram_pin)(struct intsrc *);
100 TAILQ_ENTRY(pic) pics;
101 };
102
103 /* Flags for pic_disable_source() */
104 enum {
105 PIC_EOI,
106 PIC_NO_EOI,
107 };
108
109 /*
110 * An interrupt source. The upper-layer code uses the PIC methods to
111 * control a given source. The lower-layer PIC drivers can store additional
112 * private data in a given interrupt source such as an interrupt pin number
113 * or an I/O APIC pointer.
114 */
115 struct intsrc {
116 struct pic *is_pic;
117 struct intr_event *is_event;
118 u_long *is_count;
119 u_long *is_straycount;
120 u_int is_index;
121 u_int is_handlers;
122 u_int is_domain;
123 u_int is_cpu;
124 };
125
126 struct trapframe;
127
128 #ifdef SMP
129 extern cpuset_t intr_cpus;
130 #endif
131 extern struct mtx icu_lock;
132 extern int elcr_found;
133 #ifdef SMP
134 extern int msix_disable_migration;
135 #endif
136
137 #ifndef DEV_ATPIC
138 void atpic_reset(void);
139 #endif
140 /* XXX: The elcr_* prototypes probably belong somewhere else. */
141 int elcr_probe(void);
142 enum intr_trigger elcr_read_trigger(u_int irq);
143 void elcr_resume(void);
144 void elcr_write_trigger(u_int irq, enum intr_trigger trigger);
145 #ifdef SMP
146 void intr_add_cpu(u_int cpu);
147 #endif
148 int intr_add_handler(const char *name, int vector, driver_filter_t filter,
149 driver_intr_t handler, void *arg, enum intr_type flags, void **cookiep,
150 int domain);
151 #ifdef SMP
152 int intr_bind(u_int vector, u_char cpu);
153 #endif
154 int intr_config_intr(int vector, enum intr_trigger trig,
155 enum intr_polarity pol);
156 int intr_describe(u_int vector, void *ih, const char *descr);
157 void intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame);
158 u_int intr_next_cpu(int domain);
159 struct intsrc *intr_lookup_source(int vector);
160 int intr_register_pic(struct pic *pic);
161 int intr_register_source(struct intsrc *isrc);
162 int intr_remove_handler(void *cookie);
163 void intr_resume(bool suspend_cancelled);
164 void intr_suspend(void);
165 void intr_reprogram(void);
166 void intrcnt_add(const char *name, u_long **countp);
167 void nexus_add_irq(u_long irq);
168 int msi_alloc(device_t dev, int count, int maxcount, int *irqs);
169 void msi_init(void);
170 int msi_map(int irq, uint64_t *addr, uint32_t *data);
171 int msi_release(int *irqs, int count);
172 int msix_alloc(device_t dev, int *irq);
173 int msix_release(int irq);
174 #ifdef XENHVM
175 void xen_intr_alloc_irqs(void);
176 #endif
177
178 #endif /* !LOCORE */
179 #endif /* _KERNEL */
180 #endif /* !__X86_INTR_MACHDEP_H__ */
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