1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (c) 1991 The Regents of the University of California.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the University nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91
32 * $FreeBSD$
33 */
34
35 #ifndef _MACHINE_SPECIALREG_H_
36 #define _MACHINE_SPECIALREG_H_
37
38 /*
39 * Bits in 386 special registers:
40 */
41 #define CR0_PE 0x00000001 /* Protected mode Enable */
42 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */
43 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */
44 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
45 #define CR0_PG 0x80000000 /* PaGing enable */
46
47 /*
48 * Bits in 486 special registers:
49 */
50 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
51 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in
52 all modes) */
53 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
54 #define CR0_NW 0x20000000 /* Not Write-through */
55 #define CR0_CD 0x40000000 /* Cache Disable */
56
57 #define CR3_PCID_SAVE 0x8000000000000000
58 #define CR3_PCID_MASK 0xfff
59
60 /*
61 * Bits in PPro special registers
62 */
63 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */
64 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */
65 #define CR4_TSD 0x00000004 /* Time stamp disable */
66 #define CR4_DE 0x00000008 /* Debugging extensions */
67 #define CR4_PSE 0x00000010 /* Page size extensions */
68 #define CR4_PAE 0x00000020 /* Physical address extension */
69 #define CR4_MCE 0x00000040 /* Machine check enable */
70 #define CR4_PGE 0x00000080 /* Page global enable */
71 #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */
72 #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */
73 #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */
74 #define CR4_UMIP 0x00000800 /* User Mode Instruction Prevention */
75 #define CR4_LA57 0x00001000 /* Enable 5-level paging */
76 #define CR4_VMXE 0x00002000 /* enable VMX operation (Intel-specific) */
77 #define CR4_FSGSBASE 0x00010000 /* Enable FS/GS BASE accessing instructions */
78 #define CR4_PCIDE 0x00020000 /* Enable Context ID */
79 #define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */
80 #define CR4_SMEP 0x00100000 /* Supervisor-Mode Execution Prevention */
81 #define CR4_SMAP 0x00200000 /* Supervisor-Mode Access Prevention */
82 #define CR4_PKE 0x00400000 /* Protection Keys Enable */
83
84 /*
85 * Bits in AMD64 special registers. EFER is 64 bits wide.
86 */
87 #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */
88 #define EFER_LME 0x000000100 /* Long mode enable (R/W) */
89 #define EFER_LMA 0x000000400 /* Long mode active (R) */
90 #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */
91 #define EFER_SVM 0x000001000 /* SVM enable bit for AMD, reserved for Intel */
92 #define EFER_LMSLE 0x000002000 /* Long Mode Segment Limit Enable */
93 #define EFER_FFXSR 0x000004000 /* Fast FXSAVE/FSRSTOR */
94 #define EFER_TCE 0x000008000 /* Translation Cache Extension */
95 #define EFER_MCOMMIT 0x00020000 /* Enable MCOMMIT (AMD) */
96
97 /*
98 * Intel Extended Features registers
99 */
100 #define XCR0 0 /* XFEATURE_ENABLED_MASK register */
101
102 #define XFEATURE_ENABLED_X87 0x00000001
103 #define XFEATURE_ENABLED_SSE 0x00000002
104 #define XFEATURE_ENABLED_YMM_HI128 0x00000004
105 #define XFEATURE_ENABLED_AVX XFEATURE_ENABLED_YMM_HI128
106 #define XFEATURE_ENABLED_BNDREGS 0x00000008
107 #define XFEATURE_ENABLED_BNDCSR 0x00000010
108 #define XFEATURE_ENABLED_OPMASK 0x00000020
109 #define XFEATURE_ENABLED_ZMM_HI256 0x00000040
110 #define XFEATURE_ENABLED_HI16_ZMM 0x00000080
111 #define XFEATURE_ENABLED_PKRU 0x00000200
112 #define XFEATURE_ENABLED_TILECONFIG 0x00020000
113 #define XFEATURE_ENABLED_TILEDATA 0x00040000
114
115 #define XFEATURE_AVX \
116 (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE | XFEATURE_ENABLED_AVX)
117 #define XFEATURE_AVX512 \
118 (XFEATURE_ENABLED_OPMASK | XFEATURE_ENABLED_ZMM_HI256 | \
119 XFEATURE_ENABLED_HI16_ZMM)
120 #define XFEATURE_MPX \
121 (XFEATURE_ENABLED_BNDREGS | XFEATURE_ENABLED_BNDCSR)
122
123 /*
124 * CPUID instruction features register
125 */
126 #define CPUID_FPU 0x00000001
127 #define CPUID_VME 0x00000002
128 #define CPUID_DE 0x00000004
129 #define CPUID_PSE 0x00000008
130 #define CPUID_TSC 0x00000010
131 #define CPUID_MSR 0x00000020
132 #define CPUID_PAE 0x00000040
133 #define CPUID_MCE 0x00000080
134 #define CPUID_CX8 0x00000100
135 #define CPUID_APIC 0x00000200
136 #define CPUID_B10 0x00000400
137 #define CPUID_SEP 0x00000800
138 #define CPUID_MTRR 0x00001000
139 #define CPUID_PGE 0x00002000
140 #define CPUID_MCA 0x00004000
141 #define CPUID_CMOV 0x00008000
142 #define CPUID_PAT 0x00010000
143 #define CPUID_PSE36 0x00020000
144 #define CPUID_PSN 0x00040000
145 #define CPUID_CLFSH 0x00080000
146 #define CPUID_B20 0x00100000
147 #define CPUID_DS 0x00200000
148 #define CPUID_ACPI 0x00400000
149 #define CPUID_MMX 0x00800000
150 #define CPUID_FXSR 0x01000000
151 #define CPUID_SSE 0x02000000
152 #define CPUID_XMM 0x02000000
153 #define CPUID_SSE2 0x04000000
154 #define CPUID_SS 0x08000000
155 #define CPUID_HTT 0x10000000
156 #define CPUID_TM 0x20000000
157 #define CPUID_IA64 0x40000000
158 #define CPUID_PBE 0x80000000
159
160 #define CPUID2_SSE3 0x00000001
161 #define CPUID2_PCLMULQDQ 0x00000002
162 #define CPUID2_DTES64 0x00000004
163 #define CPUID2_MON 0x00000008
164 #define CPUID2_DS_CPL 0x00000010
165 #define CPUID2_VMX 0x00000020
166 #define CPUID2_SMX 0x00000040
167 #define CPUID2_EST 0x00000080
168 #define CPUID2_TM2 0x00000100
169 #define CPUID2_SSSE3 0x00000200
170 #define CPUID2_CNXTID 0x00000400
171 #define CPUID2_SDBG 0x00000800
172 #define CPUID2_FMA 0x00001000
173 #define CPUID2_CX16 0x00002000
174 #define CPUID2_XTPR 0x00004000
175 #define CPUID2_PDCM 0x00008000
176 #define CPUID2_PCID 0x00020000
177 #define CPUID2_DCA 0x00040000
178 #define CPUID2_SSE41 0x00080000
179 #define CPUID2_SSE42 0x00100000
180 #define CPUID2_X2APIC 0x00200000
181 #define CPUID2_MOVBE 0x00400000
182 #define CPUID2_POPCNT 0x00800000
183 #define CPUID2_TSCDLT 0x01000000
184 #define CPUID2_AESNI 0x02000000
185 #define CPUID2_XSAVE 0x04000000
186 #define CPUID2_OSXSAVE 0x08000000
187 #define CPUID2_AVX 0x10000000
188 #define CPUID2_F16C 0x20000000
189 #define CPUID2_RDRAND 0x40000000
190 #define CPUID2_HV 0x80000000
191
192 /* Intel Processor Trace CPUID. */
193
194 /* Leaf 0 ebx. */
195 #define CPUPT_CR3 (1 << 0) /* CR3 Filtering Support */
196 #define CPUPT_PSB (1 << 1) /* Configurable PSB and Cycle-Accurate Mode Supported */
197 #define CPUPT_IPF (1 << 2) /* IP Filtering and TraceStop supported */
198 #define CPUPT_MTC (1 << 3) /* MTC Supported */
199 #define CPUPT_PRW (1 << 4) /* PTWRITE Supported */
200 #define CPUPT_PWR (1 << 5) /* Power Event Trace Supported */
201
202 /* Leaf 0 ecx. */
203 #define CPUPT_TOPA (1 << 0) /* ToPA Output Supported */
204 #define CPUPT_TOPA_MULTI (1 << 1) /* ToPA Tables Allow Multiple Output Entries */
205 #define CPUPT_SINGLE (1 << 2) /* Single-Range Output Supported */
206 #define CPUPT_TT_OUT (1 << 3) /* Output to Trace Transport Subsystem Supported */
207 #define CPUPT_LINEAR_IP (1 << 31) /* IP Payloads are Linear IP, otherwise IP is effective */
208
209 /* Leaf 1 eax. */
210 #define CPUPT_NADDR_S 0 /* Number of Address Ranges */
211 #define CPUPT_NADDR_M (0x7 << CPUPT_NADDR_S)
212 #define CPUPT_MTC_BITMAP_S 16 /* Bitmap of supported MTC Period Encodings */
213 #define CPUPT_MTC_BITMAP_M (0xffff << CPUPT_MTC_BITMAP_S)
214
215 /* Leaf 1 ebx. */
216 #define CPUPT_CT_BITMAP_S 0 /* Bitmap of supported Cycle Threshold values */
217 #define CPUPT_CT_BITMAP_M (0xffff << CPUPT_CT_BITMAP_S)
218 #define CPUPT_PFE_BITMAP_S 16 /* Bitmap of supported Configurable PSB Frequency encoding */
219 #define CPUPT_PFE_BITMAP_M (0xffff << CPUPT_PFE_BITMAP_S)
220
221 /*
222 * Important bits in the AMD extended cpuid flags
223 */
224 #define AMDID_SYSCALL 0x00000800
225 #define AMDID_MP 0x00080000
226 #define AMDID_NX 0x00100000
227 #define AMDID_EXT_MMX 0x00400000
228 #define AMDID_FFXSR 0x02000000
229 #define AMDID_PAGE1GB 0x04000000
230 #define AMDID_RDTSCP 0x08000000
231 #define AMDID_LM 0x20000000
232 #define AMDID_EXT_3DNOW 0x40000000
233 #define AMDID_3DNOW 0x80000000
234
235 #define AMDID2_LAHF 0x00000001
236 #define AMDID2_CMP 0x00000002
237 #define AMDID2_SVM 0x00000004
238 #define AMDID2_EXT_APIC 0x00000008
239 #define AMDID2_CR8 0x00000010
240 #define AMDID2_ABM 0x00000020
241 #define AMDID2_SSE4A 0x00000040
242 #define AMDID2_MAS 0x00000080
243 #define AMDID2_PREFETCH 0x00000100
244 #define AMDID2_OSVW 0x00000200
245 #define AMDID2_IBS 0x00000400
246 #define AMDID2_XOP 0x00000800
247 #define AMDID2_SKINIT 0x00001000
248 #define AMDID2_WDT 0x00002000
249 #define AMDID2_LWP 0x00008000
250 #define AMDID2_FMA4 0x00010000
251 #define AMDID2_TCE 0x00020000
252 #define AMDID2_NODE_ID 0x00080000
253 #define AMDID2_TBM 0x00200000
254 #define AMDID2_TOPOLOGY 0x00400000
255 #define AMDID2_PCXC 0x00800000
256 #define AMDID2_PNXC 0x01000000
257 #define AMDID2_DBE 0x04000000
258 #define AMDID2_PTSC 0x08000000
259 #define AMDID2_PTSCEL2I 0x10000000
260 #define AMDID2_MWAITX 0x20000000
261
262 /*
263 * CPUID instruction 1 eax info
264 */
265 #define CPUID_STEPPING 0x0000000f
266 #define CPUID_MODEL 0x000000f0
267 #define CPUID_FAMILY 0x00000f00
268 #define CPUID_EXT_MODEL 0x000f0000
269 #define CPUID_EXT_FAMILY 0x0ff00000
270 #ifdef __i386__
271 #define CPUID_TO_MODEL(id) \
272 ((((id) & CPUID_MODEL) >> 4) | \
273 ((((id) & CPUID_FAMILY) >= 0x600) ? \
274 (((id) & CPUID_EXT_MODEL) >> 12) : 0))
275 #define CPUID_TO_FAMILY(id) \
276 ((((id) & CPUID_FAMILY) >> 8) + \
277 ((((id) & CPUID_FAMILY) == 0xf00) ? \
278 (((id) & CPUID_EXT_FAMILY) >> 20) : 0))
279 #else
280 #define CPUID_TO_MODEL(id) \
281 ((((id) & CPUID_MODEL) >> 4) | \
282 (((id) & CPUID_EXT_MODEL) >> 12))
283 #define CPUID_TO_FAMILY(id) \
284 ((((id) & CPUID_FAMILY) >> 8) + \
285 (((id) & CPUID_EXT_FAMILY) >> 20))
286 #endif
287 #define CPUID_TO_STEPPING(id) ((id) & CPUID_STEPPING)
288
289 /*
290 * CPUID instruction 1 ebx info
291 */
292 #define CPUID_BRAND_INDEX 0x000000ff
293 #define CPUID_CLFUSH_SIZE 0x0000ff00
294 #define CPUID_HTT_CORES 0x00ff0000
295 #define CPUID_LOCAL_APIC_ID 0xff000000
296
297 /*
298 * CPUID instruction 5 info
299 */
300 #define CPUID5_MON_MIN_SIZE 0x0000ffff /* eax */
301 #define CPUID5_MON_MAX_SIZE 0x0000ffff /* ebx */
302 #define CPUID5_MON_MWAIT_EXT 0x00000001 /* ecx */
303 #define CPUID5_MWAIT_INTRBREAK 0x00000002 /* ecx */
304
305 /*
306 * MWAIT cpu power states. Lower 4 bits are sub-states.
307 */
308 #define MWAIT_C0 0xf0
309 #define MWAIT_C1 0x00
310 #define MWAIT_C2 0x10
311 #define MWAIT_C3 0x20
312 #define MWAIT_C4 0x30
313
314 /*
315 * MWAIT extensions.
316 */
317 /* Interrupt breaks MWAIT even when masked. */
318 #define MWAIT_INTRBREAK 0x00000001
319
320 /*
321 * CPUID leaf 6: Thermal and Power management.
322 */
323 /* Eax. */
324 #define CPUTPM1_SENSOR 0x00000001
325 #define CPUTPM1_TURBO 0x00000002
326 #define CPUTPM1_ARAT 0x00000004
327 #define CPUTPM1_PLN 0x00000010
328 #define CPUTPM1_ECMD 0x00000020
329 #define CPUTPM1_PTM 0x00000040
330 #define CPUTPM1_HWP 0x00000080
331 #define CPUTPM1_HWP_NOTIFICATION 0x00000100
332 #define CPUTPM1_HWP_ACTIVITY_WINDOW 0x00000200
333 #define CPUTPM1_HWP_PERF_PREF 0x00000400
334 #define CPUTPM1_HWP_PKG 0x00000800
335 #define CPUTPM1_HDC 0x00002000
336 #define CPUTPM1_TURBO30 0x00004000
337 #define CPUTPM1_HWP_CAPABILITIES 0x00008000
338 #define CPUTPM1_HWP_PECI_OVR 0x00010000
339 #define CPUTPM1_HWP_FLEXIBLE 0x00020000
340 #define CPUTPM1_HWP_FAST_MSR 0x00040000
341 #define CPUTPM1_HWP_IGN_IDLE 0x00100000
342
343 /* Ebx. */
344 #define CPUTPM_B_NSENSINTTHRESH 0x0000000f
345
346 /* Ecx. */
347 #define CPUID_PERF_STAT 0x00000001
348 #define CPUID_PERF_BIAS 0x00000008
349
350 /*
351 * CPUID instruction 0xb ebx info.
352 */
353 #define CPUID_TYPE_INVAL 0
354 #define CPUID_TYPE_SMT 1
355 #define CPUID_TYPE_CORE 2
356
357 /*
358 * CPUID instruction 0xd Processor Extended State Enumeration Sub-leaf 1
359 */
360 #define CPUID_EXTSTATE_XSAVEOPT 0x00000001
361 #define CPUID_EXTSTATE_XSAVEC 0x00000002
362 #define CPUID_EXTSTATE_XINUSE 0x00000004
363 #define CPUID_EXTSTATE_XSAVES 0x00000008
364
365 /*
366 * AMD extended function 8000_0007h ebx info
367 */
368 #define AMDRAS_MCA_OF_RECOV 0x00000001
369 #define AMDRAS_SUCCOR 0x00000002
370 #define AMDRAS_HW_ASSERT 0x00000004
371 #define AMDRAS_SCALABLE_MCA 0x00000008
372 #define AMDRAS_PFEH_SUPPORT 0x00000010
373
374 /*
375 * AMD extended function 8000_0007h edx info
376 */
377 #define AMDPM_TS 0x00000001
378 #define AMDPM_FID 0x00000002
379 #define AMDPM_VID 0x00000004
380 #define AMDPM_TTP 0x00000008
381 #define AMDPM_TM 0x00000010
382 #define AMDPM_STC 0x00000020
383 #define AMDPM_100MHZ_STEPS 0x00000040
384 #define AMDPM_HW_PSTATE 0x00000080
385 #define AMDPM_TSC_INVARIANT 0x00000100
386 #define AMDPM_CPB 0x00000200
387
388 /*
389 * AMD extended function 8000_0008h ebx info (amd_extended_feature_extensions)
390 */
391 #define AMDFEID_CLZERO 0x00000001
392 #define AMDFEID_IRPERF 0x00000002
393 #define AMDFEID_XSAVEERPTR 0x00000004
394 #define AMDFEID_RDPRU 0x00000010
395 #define AMDFEID_MCOMMIT 0x00000100
396 #define AMDFEID_WBNOINVD 0x00000200
397 #define AMDFEID_IBPB 0x00001000
398 #define AMDFEID_IBRS 0x00004000
399 #define AMDFEID_STIBP 0x00008000
400 /* The below are only defined if the corresponding base feature above exists. */
401 #define AMDFEID_IBRS_ALWAYSON 0x00010000
402 #define AMDFEID_STIBP_ALWAYSON 0x00020000
403 #define AMDFEID_PREFER_IBRS 0x00040000
404 #define AMDFEID_PPIN 0x00800000
405 #define AMDFEID_SSBD 0x01000000
406 /* SSBD via MSRC001_011F instead of MSR 0x48: */
407 #define AMDFEID_VIRT_SSBD 0x02000000
408 #define AMDFEID_SSB_NO 0x04000000
409
410 /*
411 * AMD extended function 8000_0008h ecx info
412 */
413 #define AMDID_CMP_CORES 0x000000ff
414 #define AMDID_COREID_SIZE 0x0000f000
415 #define AMDID_COREID_SIZE_SHIFT 12
416
417 /*
418 * CPUID instruction 7 Structured Extended Features, leaf 0 ebx info
419 */
420 #define CPUID_STDEXT_FSGSBASE 0x00000001
421 #define CPUID_STDEXT_TSC_ADJUST 0x00000002
422 #define CPUID_STDEXT_SGX 0x00000004
423 #define CPUID_STDEXT_BMI1 0x00000008
424 #define CPUID_STDEXT_HLE 0x00000010
425 #define CPUID_STDEXT_AVX2 0x00000020
426 #define CPUID_STDEXT_FDP_EXC 0x00000040
427 #define CPUID_STDEXT_SMEP 0x00000080
428 #define CPUID_STDEXT_BMI2 0x00000100
429 #define CPUID_STDEXT_ERMS 0x00000200
430 #define CPUID_STDEXT_INVPCID 0x00000400
431 #define CPUID_STDEXT_RTM 0x00000800
432 #define CPUID_STDEXT_PQM 0x00001000
433 #define CPUID_STDEXT_NFPUSG 0x00002000
434 #define CPUID_STDEXT_MPX 0x00004000
435 #define CPUID_STDEXT_PQE 0x00008000
436 #define CPUID_STDEXT_AVX512F 0x00010000
437 #define CPUID_STDEXT_AVX512DQ 0x00020000
438 #define CPUID_STDEXT_RDSEED 0x00040000
439 #define CPUID_STDEXT_ADX 0x00080000
440 #define CPUID_STDEXT_SMAP 0x00100000
441 #define CPUID_STDEXT_AVX512IFMA 0x00200000
442 /* Formerly PCOMMIT */
443 #define CPUID_STDEXT_CLFLUSHOPT 0x00800000
444 #define CPUID_STDEXT_CLWB 0x01000000
445 #define CPUID_STDEXT_PROCTRACE 0x02000000
446 #define CPUID_STDEXT_AVX512PF 0x04000000
447 #define CPUID_STDEXT_AVX512ER 0x08000000
448 #define CPUID_STDEXT_AVX512CD 0x10000000
449 #define CPUID_STDEXT_SHA 0x20000000
450 #define CPUID_STDEXT_AVX512BW 0x40000000
451 #define CPUID_STDEXT_AVX512VL 0x80000000
452
453 /*
454 * CPUID instruction 7 Structured Extended Features, leaf 0 ecx info
455 */
456 #define CPUID_STDEXT2_PREFETCHWT1 0x00000001
457 #define CPUID_STDEXT2_AVX512VBMI 0x00000002
458 #define CPUID_STDEXT2_UMIP 0x00000004
459 #define CPUID_STDEXT2_PKU 0x00000008
460 #define CPUID_STDEXT2_OSPKE 0x00000010
461 #define CPUID_STDEXT2_WAITPKG 0x00000020
462 #define CPUID_STDEXT2_AVX512VBMI2 0x00000040
463 #define CPUID_STDEXT2_GFNI 0x00000100
464 #define CPUID_STDEXT2_VAES 0x00000200
465 #define CPUID_STDEXT2_VPCLMULQDQ 0x00000400
466 #define CPUID_STDEXT2_AVX512VNNI 0x00000800
467 #define CPUID_STDEXT2_AVX512BITALG 0x00001000
468 #define CPUID_STDEXT2_TME 0x00002000
469 #define CPUID_STDEXT2_AVX512VPOPCNTDQ 0x00004000
470 #define CPUID_STDEXT2_LA57 0x00010000
471 #define CPUID_STDEXT2_RDPID 0x00400000
472 #define CPUID_STDEXT2_CLDEMOTE 0x02000000
473 #define CPUID_STDEXT2_MOVDIRI 0x08000000
474 #define CPUID_STDEXT2_MOVDIR64B 0x10000000
475 #define CPUID_STDEXT2_ENQCMD 0x20000000
476 #define CPUID_STDEXT2_SGXLC 0x40000000
477
478 /*
479 * CPUID instruction 7 Structured Extended Features, leaf 0 edx info
480 */
481 #define CPUID_STDEXT3_AVX5124VNNIW 0x00000004
482 #define CPUID_STDEXT3_AVX5124FMAPS 0x00000008
483 #define CPUID_STDEXT3_FSRM 0x00000010
484 #define CPUID_STDEXT3_AVX512VP2INTERSECT 0x00000100
485 #define CPUID_STDEXT3_MCUOPT 0x00000200
486 #define CPUID_STDEXT3_MD_CLEAR 0x00000400
487 #define CPUID_STDEXT3_TSXFA 0x00002000
488 #define CPUID_STDEXT3_PCONFIG 0x00040000
489 #define CPUID_STDEXT3_IBPB 0x04000000
490 #define CPUID_STDEXT3_STIBP 0x08000000
491 #define CPUID_STDEXT3_L1D_FLUSH 0x10000000
492 #define CPUID_STDEXT3_ARCH_CAP 0x20000000
493 #define CPUID_STDEXT3_CORE_CAP 0x40000000
494 #define CPUID_STDEXT3_SSBD 0x80000000
495
496 /* CPUID_HYBRID_ID leaf 0x1a */
497 #define CPUID_HYBRID_CORE_MASK 0xff000000
498 #define CPUID_HYBRID_SMALL_CORE 0x20000000
499 #define CPUID_HYBRID_LARGE_CORE 0x40000000
500
501 /* MSR IA32_ARCH_CAP(ABILITIES) bits */
502 #define IA32_ARCH_CAP_RDCL_NO 0x00000001
503 #define IA32_ARCH_CAP_IBRS_ALL 0x00000002
504 #define IA32_ARCH_CAP_RSBA 0x00000004
505 #define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x00000008
506 #define IA32_ARCH_CAP_SSB_NO 0x00000010
507 #define IA32_ARCH_CAP_MDS_NO 0x00000020
508 #define IA32_ARCH_CAP_IF_PSCHANGE_MC_NO 0x00000040
509 #define IA32_ARCH_CAP_TSX_CTRL 0x00000080
510 #define IA32_ARCH_CAP_TAA_NO 0x00000100
511
512 /* MSR IA32_TSX_CTRL bits */
513 #define IA32_TSX_CTRL_RTM_DISABLE 0x00000001
514 #define IA32_TSX_CTRL_TSX_CPUID_CLEAR 0x00000002
515
516 /*
517 * CPUID manufacturers identifiers
518 */
519 #define AMD_VENDOR_ID "AuthenticAMD"
520 #define CENTAUR_VENDOR_ID "CentaurHauls"
521 #define CYRIX_VENDOR_ID "CyrixInstead"
522 #define INTEL_VENDOR_ID "GenuineIntel"
523 #define NEXGEN_VENDOR_ID "NexGenDriven"
524 #define NSC_VENDOR_ID "Geode by NSC"
525 #define RISE_VENDOR_ID "RiseRiseRise"
526 #define SIS_VENDOR_ID "SiS SiS SiS "
527 #define TRANSMETA_VENDOR_ID "GenuineTMx86"
528 #define UMC_VENDOR_ID "UMC UMC UMC "
529 #define HYGON_VENDOR_ID "HygonGenuine"
530
531 /*
532 * Model-specific registers for the i386 family
533 */
534 #define MSR_P5_MC_ADDR 0x000
535 #define MSR_P5_MC_TYPE 0x001
536 #define MSR_TSC 0x010
537 #define MSR_P5_CESR 0x011
538 #define MSR_P5_CTR0 0x012
539 #define MSR_P5_CTR1 0x013
540 #define MSR_IA32_PLATFORM_ID 0x017
541 #define MSR_APICBASE 0x01b
542 #define MSR_EBL_CR_POWERON 0x02a
543 #define MSR_TEST_CTL 0x033
544 #define MSR_IA32_FEATURE_CONTROL 0x03a
545 #define MSR_IA32_SPEC_CTRL 0x048
546 #define MSR_IA32_PRED_CMD 0x049
547 #define MSR_BIOS_UPDT_TRIG 0x079
548 #define MSR_BBL_CR_D0 0x088
549 #define MSR_BBL_CR_D1 0x089
550 #define MSR_BBL_CR_D2 0x08a
551 #define MSR_BIOS_SIGN 0x08b
552 #define MSR_PERFCTR0 0x0c1
553 #define MSR_PERFCTR1 0x0c2
554 #define MSR_PLATFORM_INFO 0x0ce
555 #define MSR_MPERF 0x0e7
556 #define MSR_APERF 0x0e8
557 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */
558 #define MSR_MTRRcap 0x0fe
559 #define MSR_IA32_ARCH_CAP 0x10a
560 #define MSR_IA32_FLUSH_CMD 0x10b
561 #define MSR_TSX_FORCE_ABORT 0x10f
562 #define MSR_BBL_CR_ADDR 0x116
563 #define MSR_BBL_CR_DECC 0x118
564 #define MSR_BBL_CR_CTL 0x119
565 #define MSR_BBL_CR_TRIG 0x11a
566 #define MSR_BBL_CR_BUSY 0x11b
567 #define MSR_BBL_CR_CTL3 0x11e
568 #define MSR_IA32_TSX_CTRL 0x122
569 #define MSR_IA32_MCU_OPT_CTRL 0x123
570 #define MSR_MISC_FEATURE_ENABLES 0x140
571 #define MSR_SYSENTER_CS_MSR 0x174
572 #define MSR_SYSENTER_ESP_MSR 0x175
573 #define MSR_SYSENTER_EIP_MSR 0x176
574 #define MSR_MCG_CAP 0x179
575 #define MSR_MCG_STATUS 0x17a
576 #define MSR_MCG_CTL 0x17b
577 #define MSR_EVNTSEL0 0x186
578 #define MSR_EVNTSEL1 0x187
579 #define MSR_THERM_CONTROL 0x19a
580 #define MSR_THERM_INTERRUPT 0x19b
581 #define MSR_THERM_STATUS 0x19c
582 #define MSR_IA32_MISC_ENABLE 0x1a0
583 #define MSR_IA32_TEMPERATURE_TARGET 0x1a2
584 #define MSR_TURBO_RATIO_LIMIT 0x1ad
585 #define MSR_TURBO_RATIO_LIMIT1 0x1ae
586 #define MSR_IA32_ENERGY_PERF_BIAS 0x1b0
587 #define MSR_DEBUGCTLMSR 0x1d9
588 #define MSR_LASTBRANCHFROMIP 0x1db
589 #define MSR_LASTBRANCHTOIP 0x1dc
590 #define MSR_LASTINTFROMIP 0x1dd
591 #define MSR_LASTINTTOIP 0x1de
592 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0
593 #define MSR_MTRRVarBase 0x200
594 #define MSR_MTRR64kBase 0x250
595 #define MSR_MTRR16kBase 0x258
596 #define MSR_MTRR4kBase 0x268
597 #define MSR_PAT 0x277
598 #define MSR_MC0_CTL2 0x280
599 #define MSR_MTRRdefType 0x2ff
600 #define MSR_MC0_CTL 0x400
601 #define MSR_MC0_STATUS 0x401
602 #define MSR_MC0_ADDR 0x402
603 #define MSR_MC0_MISC 0x403
604 #define MSR_MC1_CTL 0x404
605 #define MSR_MC1_STATUS 0x405
606 #define MSR_MC1_ADDR 0x406
607 #define MSR_MC1_MISC 0x407
608 #define MSR_MC2_CTL 0x408
609 #define MSR_MC2_STATUS 0x409
610 #define MSR_MC2_ADDR 0x40a
611 #define MSR_MC2_MISC 0x40b
612 #define MSR_MC3_CTL 0x40c
613 #define MSR_MC3_STATUS 0x40d
614 #define MSR_MC3_ADDR 0x40e
615 #define MSR_MC3_MISC 0x40f
616 #define MSR_MC4_CTL 0x410
617 #define MSR_MC4_STATUS 0x411
618 #define MSR_MC4_ADDR 0x412
619 #define MSR_MC4_MISC 0x413
620 #define MSR_MCG_EXT_CTL 0x4d0
621 #define MSR_RAPL_POWER_UNIT 0x606
622 #define MSR_PKG_ENERGY_STATUS 0x611
623 #define MSR_DRAM_ENERGY_STATUS 0x619
624 #define MSR_PP0_ENERGY_STATUS 0x639
625 #define MSR_PP1_ENERGY_STATUS 0x641
626 #define MSR_PPERF 0x64e
627 #define MSR_TSC_DEADLINE 0x6e0 /* Writes are not serializing */
628 #define MSR_IA32_PM_ENABLE 0x770
629 #define MSR_IA32_HWP_CAPABILITIES 0x771
630 #define MSR_IA32_HWP_REQUEST_PKG 0x772
631 #define MSR_IA32_HWP_INTERRUPT 0x773
632 #define MSR_IA32_HWP_REQUEST 0x774
633 #define MSR_IA32_HWP_STATUS 0x777
634
635 /*
636 * VMX MSRs
637 */
638 #define MSR_VMX_BASIC 0x480
639 #define MSR_VMX_PINBASED_CTLS 0x481
640 #define MSR_VMX_PROCBASED_CTLS 0x482
641 #define MSR_VMX_EXIT_CTLS 0x483
642 #define MSR_VMX_ENTRY_CTLS 0x484
643 #define MSR_VMX_CR0_FIXED0 0x486
644 #define MSR_VMX_CR0_FIXED1 0x487
645 #define MSR_VMX_CR4_FIXED0 0x488
646 #define MSR_VMX_CR4_FIXED1 0x489
647 #define MSR_VMX_PROCBASED_CTLS2 0x48b
648 #define MSR_VMX_EPT_VPID_CAP 0x48c
649 #define MSR_VMX_TRUE_PINBASED_CTLS 0x48d
650 #define MSR_VMX_TRUE_PROCBASED_CTLS 0x48e
651 #define MSR_VMX_TRUE_EXIT_CTLS 0x48f
652 #define MSR_VMX_TRUE_ENTRY_CTLS 0x490
653
654 /*
655 * X2APIC MSRs.
656 * Writes are not serializing.
657 */
658 #define MSR_APIC_000 0x800
659 #define MSR_APIC_ID 0x802
660 #define MSR_APIC_VERSION 0x803
661 #define MSR_APIC_TPR 0x808
662 #define MSR_APIC_EOI 0x80b
663 #define MSR_APIC_LDR 0x80d
664 #define MSR_APIC_SVR 0x80f
665 #define MSR_APIC_ISR0 0x810
666 #define MSR_APIC_ISR1 0x811
667 #define MSR_APIC_ISR2 0x812
668 #define MSR_APIC_ISR3 0x813
669 #define MSR_APIC_ISR4 0x814
670 #define MSR_APIC_ISR5 0x815
671 #define MSR_APIC_ISR6 0x816
672 #define MSR_APIC_ISR7 0x817
673 #define MSR_APIC_TMR0 0x818
674 #define MSR_APIC_IRR0 0x820
675 #define MSR_APIC_ESR 0x828
676 #define MSR_APIC_LVT_CMCI 0x82F
677 #define MSR_APIC_ICR 0x830
678 #define MSR_APIC_LVT_TIMER 0x832
679 #define MSR_APIC_LVT_THERMAL 0x833
680 #define MSR_APIC_LVT_PCINT 0x834
681 #define MSR_APIC_LVT_LINT0 0x835
682 #define MSR_APIC_LVT_LINT1 0x836
683 #define MSR_APIC_LVT_ERROR 0x837
684 #define MSR_APIC_ICR_TIMER 0x838
685 #define MSR_APIC_CCR_TIMER 0x839
686 #define MSR_APIC_DCR_TIMER 0x83e
687 #define MSR_APIC_SELF_IPI 0x83f
688
689 #define MSR_IA32_XSS 0xda0
690
691 /*
692 * Intel Processor Trace (PT) MSRs.
693 */
694 #define MSR_IA32_RTIT_OUTPUT_BASE 0x560 /* Trace Output Base Register (R/W) */
695 #define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x561 /* Trace Output Mask Pointers Register (R/W) */
696 #define MSR_IA32_RTIT_CTL 0x570 /* Trace Control Register (R/W) */
697 #define RTIT_CTL_TRACEEN (1 << 0)
698 #define RTIT_CTL_CYCEN (1 << 1)
699 #define RTIT_CTL_OS (1 << 2)
700 #define RTIT_CTL_USER (1 << 3)
701 #define RTIT_CTL_PWREVTEN (1 << 4)
702 #define RTIT_CTL_FUPONPTW (1 << 5)
703 #define RTIT_CTL_FABRICEN (1 << 6)
704 #define RTIT_CTL_CR3FILTER (1 << 7)
705 #define RTIT_CTL_TOPA (1 << 8)
706 #define RTIT_CTL_MTCEN (1 << 9)
707 #define RTIT_CTL_TSCEN (1 << 10)
708 #define RTIT_CTL_DISRETC (1 << 11)
709 #define RTIT_CTL_PTWEN (1 << 12)
710 #define RTIT_CTL_BRANCHEN (1 << 13)
711 #define RTIT_CTL_MTC_FREQ_S 14
712 #define RTIT_CTL_MTC_FREQ(n) ((n) << RTIT_CTL_MTC_FREQ_S)
713 #define RTIT_CTL_MTC_FREQ_M (0xf << RTIT_CTL_MTC_FREQ_S)
714 #define RTIT_CTL_CYC_THRESH_S 19
715 #define RTIT_CTL_CYC_THRESH_M (0xf << RTIT_CTL_CYC_THRESH_S)
716 #define RTIT_CTL_PSB_FREQ_S 24
717 #define RTIT_CTL_PSB_FREQ_M (0xf << RTIT_CTL_PSB_FREQ_S)
718 #define RTIT_CTL_ADDR_CFG_S(n) (32 + (n) * 4)
719 #define RTIT_CTL_ADDR0_CFG_S 32
720 #define RTIT_CTL_ADDR0_CFG_M (0xfULL << RTIT_CTL_ADDR0_CFG_S)
721 #define RTIT_CTL_ADDR1_CFG_S 36
722 #define RTIT_CTL_ADDR1_CFG_M (0xfULL << RTIT_CTL_ADDR1_CFG_S)
723 #define RTIT_CTL_ADDR2_CFG_S 40
724 #define RTIT_CTL_ADDR2_CFG_M (0xfULL << RTIT_CTL_ADDR2_CFG_S)
725 #define RTIT_CTL_ADDR3_CFG_S 44
726 #define RTIT_CTL_ADDR3_CFG_M (0xfULL << RTIT_CTL_ADDR3_CFG_S)
727 #define MSR_IA32_RTIT_STATUS 0x571 /* Tracing Status Register (R/W) */
728 #define RTIT_STATUS_FILTEREN (1 << 0)
729 #define RTIT_STATUS_CONTEXTEN (1 << 1)
730 #define RTIT_STATUS_TRIGGEREN (1 << 2)
731 #define RTIT_STATUS_ERROR (1 << 4)
732 #define RTIT_STATUS_STOPPED (1 << 5)
733 #define RTIT_STATUS_PACKETBYTECNT_S 32
734 #define RTIT_STATUS_PACKETBYTECNT_M (0x1ffffULL << RTIT_STATUS_PACKETBYTECNT_S)
735 #define MSR_IA32_RTIT_CR3_MATCH 0x572 /* Trace Filter CR3 Match Register (R/W) */
736 #define MSR_IA32_RTIT_ADDR_A(n) (0x580 + (n) * 2)
737 #define MSR_IA32_RTIT_ADDR_B(n) (0x581 + (n) * 2)
738 #define MSR_IA32_RTIT_ADDR0_A 0x580 /* Region 0 Start Address (R/W) */
739 #define MSR_IA32_RTIT_ADDR0_B 0x581 /* Region 0 End Address (R/W) */
740 #define MSR_IA32_RTIT_ADDR1_A 0x582 /* Region 1 Start Address (R/W) */
741 #define MSR_IA32_RTIT_ADDR1_B 0x583 /* Region 1 End Address (R/W) */
742 #define MSR_IA32_RTIT_ADDR2_A 0x584 /* Region 2 Start Address (R/W) */
743 #define MSR_IA32_RTIT_ADDR2_B 0x585 /* Region 2 End Address (R/W) */
744 #define MSR_IA32_RTIT_ADDR3_A 0x586 /* Region 3 Start Address (R/W) */
745 #define MSR_IA32_RTIT_ADDR3_B 0x587 /* Region 3 End Address (R/W) */
746
747 /* Intel Processor Trace Table of Physical Addresses (ToPA). */
748 #define TOPA_SIZE_S 6
749 #define TOPA_SIZE_M (0xf << TOPA_SIZE_S)
750 #define TOPA_SIZE_4K (0 << TOPA_SIZE_S)
751 #define TOPA_SIZE_8K (1 << TOPA_SIZE_S)
752 #define TOPA_SIZE_16K (2 << TOPA_SIZE_S)
753 #define TOPA_SIZE_32K (3 << TOPA_SIZE_S)
754 #define TOPA_SIZE_64K (4 << TOPA_SIZE_S)
755 #define TOPA_SIZE_128K (5 << TOPA_SIZE_S)
756 #define TOPA_SIZE_256K (6 << TOPA_SIZE_S)
757 #define TOPA_SIZE_512K (7 << TOPA_SIZE_S)
758 #define TOPA_SIZE_1M (8 << TOPA_SIZE_S)
759 #define TOPA_SIZE_2M (9 << TOPA_SIZE_S)
760 #define TOPA_SIZE_4M (10 << TOPA_SIZE_S)
761 #define TOPA_SIZE_8M (11 << TOPA_SIZE_S)
762 #define TOPA_SIZE_16M (12 << TOPA_SIZE_S)
763 #define TOPA_SIZE_32M (13 << TOPA_SIZE_S)
764 #define TOPA_SIZE_64M (14 << TOPA_SIZE_S)
765 #define TOPA_SIZE_128M (15 << TOPA_SIZE_S)
766 #define TOPA_STOP (1 << 4)
767 #define TOPA_INT (1 << 2)
768 #define TOPA_END (1 << 0)
769
770 /*
771 * Constants related to MSR's.
772 */
773 #define APICBASE_RESERVED 0x000002ff
774 #define APICBASE_BSP 0x00000100
775 #define APICBASE_X2APIC 0x00000400
776 #define APICBASE_ENABLED 0x00000800
777 #define APICBASE_ADDRESS 0xfffff000
778
779 /* MSR_IA32_FEATURE_CONTROL related */
780 #define IA32_FEATURE_CONTROL_LOCK 0x01 /* lock bit */
781 #define IA32_FEATURE_CONTROL_SMX_EN 0x02 /* enable VMX inside SMX */
782 #define IA32_FEATURE_CONTROL_VMX_EN 0x04 /* enable VMX outside SMX */
783 #define IA32_FEATURE_CONTROL_LMCE_EN 0x100000 /* enable local MCE */
784
785 /* MSR IA32_MISC_ENABLE */
786 #define IA32_MISC_EN_FASTSTR 0x0000000000000001ULL
787 #define IA32_MISC_EN_ATCCE 0x0000000000000008ULL
788 #define IA32_MISC_EN_PERFMON 0x0000000000000080ULL
789 #define IA32_MISC_EN_PEBSU 0x0000000000001000ULL
790 #define IA32_MISC_EN_ESSTE 0x0000000000010000ULL
791 #define IA32_MISC_EN_MONE 0x0000000000040000ULL
792 #define IA32_MISC_EN_LIMCPUID 0x0000000000400000ULL
793 #define IA32_MISC_EN_xTPRD 0x0000000000800000ULL
794 #define IA32_MISC_EN_XDD 0x0000000400000000ULL
795
796 /*
797 * IA32_SPEC_CTRL and IA32_PRED_CMD MSRs are described in the Intel'
798 * document 336996-001 Speculative Execution Side Channel Mitigations.
799 *
800 * AMD uses the same MSRs and bit definitions, as described in 111006-B
801 * "Indirect Branch Control Extension" and 124441 "Speculative Store Bypass
802 * Disable."
803 */
804 /* MSR IA32_SPEC_CTRL */
805 #define IA32_SPEC_CTRL_IBRS 0x00000001
806 #define IA32_SPEC_CTRL_STIBP 0x00000002
807 #define IA32_SPEC_CTRL_SSBD 0x00000004
808
809 /* MSR IA32_PRED_CMD */
810 #define IA32_PRED_CMD_IBPB_BARRIER 0x0000000000000001ULL
811
812 /* MSR IA32_FLUSH_CMD */
813 #define IA32_FLUSH_CMD_L1D 0x00000001
814
815 /* MSR IA32_MCU_OPT_CTRL */
816 #define IA32_RNGDS_MITG_DIS 0x00000001
817
818 /* MSR IA32_HWP_CAPABILITIES */
819 #define IA32_HWP_CAPABILITIES_HIGHEST_PERFORMANCE(x) (((x) >> 0) & 0xff)
820 #define IA32_HWP_CAPABILITIES_GUARANTEED_PERFORMANCE(x) (((x) >> 8) & 0xff)
821 #define IA32_HWP_CAPABILITIES_EFFICIENT_PERFORMANCE(x) (((x) >> 16) & 0xff)
822 #define IA32_HWP_CAPABILITIES_LOWEST_PERFORMANCE(x) (((x) >> 24) & 0xff)
823
824 /* MSR IA32_HWP_REQUEST */
825 #define IA32_HWP_REQUEST_MINIMUM_VALID (1ULL << 63)
826 #define IA32_HWP_REQUEST_MAXIMUM_VALID (1ULL << 62)
827 #define IA32_HWP_REQUEST_DESIRED_VALID (1ULL << 61)
828 #define IA32_HWP_REQUEST_EPP_VALID (1ULL << 60)
829 #define IA32_HWP_REQUEST_ACTIVITY_WINDOW_VALID (1ULL << 59)
830 #define IA32_HWP_REQUEST_PACKAGE_CONTROL (1ULL << 42)
831 #define IA32_HWP_ACTIVITY_WINDOW (0x3ffULL << 32)
832 #define IA32_HWP_REQUEST_ENERGY_PERFORMANCE_PREFERENCE (0xffULL << 24)
833 #define IA32_HWP_DESIRED_PERFORMANCE (0xffULL << 16)
834 #define IA32_HWP_REQUEST_MAXIMUM_PERFORMANCE (0xffULL << 8)
835 #define IA32_HWP_MINIMUM_PERFORMANCE (0xffULL << 0)
836
837 /* MSR IA32_ENERGY_PERF_BIAS */
838 #define IA32_ENERGY_PERF_BIAS_POLICY_HINT_MASK (0xfULL << 0)
839
840 /*
841 * PAT modes.
842 */
843 #define PAT_UNCACHEABLE 0x00
844 #define PAT_WRITE_COMBINING 0x01
845 #define PAT_WRITE_THROUGH 0x04
846 #define PAT_WRITE_PROTECTED 0x05
847 #define PAT_WRITE_BACK 0x06
848 #define PAT_UNCACHED 0x07
849 #define PAT_VALUE(i, m) ((long long)(m) << (8 * (i)))
850 #define PAT_MASK(i) PAT_VALUE(i, 0xff)
851
852 /*
853 * Constants related to MTRRs
854 */
855 #define MTRR_UNCACHEABLE 0x00
856 #define MTRR_WRITE_COMBINING 0x01
857 #define MTRR_WRITE_THROUGH 0x04
858 #define MTRR_WRITE_PROTECTED 0x05
859 #define MTRR_WRITE_BACK 0x06
860 #define MTRR_N64K 8 /* numbers of fixed-size entries */
861 #define MTRR_N16K 16
862 #define MTRR_N4K 64
863 #define MTRR_CAP_WC 0x0000000000000400
864 #define MTRR_CAP_FIXED 0x0000000000000100
865 #define MTRR_CAP_VCNT 0x00000000000000ff
866 #define MTRR_DEF_ENABLE 0x0000000000000800
867 #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400
868 #define MTRR_DEF_TYPE 0x00000000000000ff
869 #define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000
870 #define MTRR_PHYSBASE_TYPE 0x00000000000000ff
871 #define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000
872 #define MTRR_PHYSMASK_VALID 0x0000000000000800
873
874 /*
875 * Cyrix configuration registers, accessible as IO ports.
876 */
877 #define CCR0 0xc0 /* Configuration control register 0 */
878 #define CCR0_NC0 0x01 /* First 64K of each 1M memory region is
879 non-cacheable */
880 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */
881 #define CCR0_A20M 0x04 /* Enables A20M# input pin */
882 #define CCR0_KEN 0x08 /* Enables KEN# input pin */
883 #define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */
884 #define CCR0_BARB 0x20 /* Flushes internal cache when entering hold
885 state */
886 #define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set
887 assoc */
888 #define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */
889
890 #define CCR1 0xc1 /* Configuration control register 1 */
891 #define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */
892 #define CCR1_SMI 0x02 /* Enables SMM pins */
893 #define CCR1_SMAC 0x04 /* System management memory access */
894 #define CCR1_MMAC 0x08 /* Main memory access */
895 #define CCR1_NO_LOCK 0x10 /* Negate LOCK# */
896 #define CCR1_SM3 0x80 /* SMM address space address region 3 */
897
898 #define CCR2 0xc2
899 #define CCR2_WB 0x02 /* Enables WB cache interface pins */
900 #define CCR2_SADS 0x02 /* Slow ADS */
901 #define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */
902 #define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */
903 #define CCR2_WT1 0x10 /* WT region 1 */
904 #define CCR2_WPR1 0x10 /* Write-protect region 1 */
905 #define CCR2_BARB 0x20 /* Flushes write-back cache when entering
906 hold state. */
907 #define CCR2_BWRT 0x40 /* Enables burst write cycles */
908 #define CCR2_USE_SUSP 0x80 /* Enables suspend pins */
909
910 #define CCR3 0xc3
911 #define CCR3_SMILOCK 0x01 /* SMM register lock */
912 #define CCR3_NMI 0x02 /* Enables NMI during SMM */
913 #define CCR3_LINBRST 0x04 /* Linear address burst cycles */
914 #define CCR3_SMMMODE 0x08 /* SMM Mode */
915 #define CCR3_MAPEN0 0x10 /* Enables Map0 */
916 #define CCR3_MAPEN1 0x20 /* Enables Map1 */
917 #define CCR3_MAPEN2 0x40 /* Enables Map2 */
918 #define CCR3_MAPEN3 0x80 /* Enables Map3 */
919
920 #define CCR4 0xe8
921 #define CCR4_IOMASK 0x07
922 #define CCR4_MEM 0x08 /* Enables momory bypassing */
923 #define CCR4_DTE 0x10 /* Enables directory table entry cache */
924 #define CCR4_FASTFPE 0x20 /* Fast FPU exception */
925 #define CCR4_CPUID 0x80 /* Enables CPUID instruction */
926
927 #define CCR5 0xe9
928 #define CCR5_WT_ALLOC 0x01 /* Write-through allocate */
929 #define CCR5_SLOP 0x02 /* LOOP instruction slowed down */
930 #define CCR5_LBR1 0x10 /* Local bus region 1 */
931 #define CCR5_ARREN 0x20 /* Enables ARR region */
932
933 #define CCR6 0xea
934
935 #define CCR7 0xeb
936
937 /* Performance Control Register (5x86 only). */
938 #define PCR0 0x20
939 #define PCR0_RSTK 0x01 /* Enables return stack */
940 #define PCR0_BTB 0x02 /* Enables branch target buffer */
941 #define PCR0_LOOP 0x04 /* Enables loop */
942 #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to
943 serialize pipe. */
944 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */
945 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */
946 #define PCR0_LSSER 0x80 /* Disable reorder */
947
948 /* Device Identification Registers */
949 #define DIR0 0xfe
950 #define DIR1 0xff
951
952 /*
953 * Machine Check register constants.
954 */
955 #define MCG_CAP_COUNT 0x000000ff
956 #define MCG_CAP_CTL_P 0x00000100
957 #define MCG_CAP_EXT_P 0x00000200
958 #define MCG_CAP_CMCI_P 0x00000400
959 #define MCG_CAP_TES_P 0x00000800
960 #define MCG_CAP_EXT_CNT 0x00ff0000
961 #define MCG_CAP_SER_P 0x01000000
962 #define MCG_CAP_EMC_P 0x02000000
963 #define MCG_CAP_ELOG_P 0x04000000
964 #define MCG_CAP_LMCE_P 0x08000000
965 #define MCG_STATUS_RIPV 0x00000001
966 #define MCG_STATUS_EIPV 0x00000002
967 #define MCG_STATUS_MCIP 0x00000004
968 #define MCG_STATUS_LMCS 0x00000008 /* if MCG_CAP_LMCE_P */
969 #define MCG_CTL_ENABLE 0xffffffffffffffff
970 #define MCG_CTL_DISABLE 0x0000000000000000
971 #define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4)
972 #define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4)
973 #define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4)
974 #define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4)
975 #define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */
976 #define MC_STATUS_MCA_ERROR 0x000000000000ffff
977 #define MC_STATUS_MODEL_ERROR 0x00000000ffff0000
978 #define MC_STATUS_OTHER_INFO 0x01ffffff00000000
979 #define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_CMCI_P */
980 #define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */
981 #define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_TES_P */
982 #define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_TES_P */
983 #define MC_STATUS_PCC 0x0200000000000000
984 #define MC_STATUS_ADDRV 0x0400000000000000
985 #define MC_STATUS_MISCV 0x0800000000000000
986 #define MC_STATUS_EN 0x1000000000000000
987 #define MC_STATUS_UC 0x2000000000000000
988 #define MC_STATUS_OVER 0x4000000000000000
989 #define MC_STATUS_VAL 0x8000000000000000
990 #define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */
991 #define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */
992 #define MC_MISC_PCIE_RID 0x00000000ffff0000
993 #define MC_MISC_PCIE_FUNC 0x0000000000070000
994 #define MC_MISC_PCIE_SLOT 0x0000000000f80000
995 #define MC_MISC_PCIE_BUS 0x00000000ff000000
996 #define MC_MISC_PCIE_SEG 0x000000ff00000000
997 #define MC_CTL2_THRESHOLD 0x0000000000007fff
998 #define MC_CTL2_CMCI_EN 0x0000000040000000
999 #define MC_AMDNB_BANK 4
1000 #define MC_MISC_AMD_VAL 0x8000000000000000 /* Counter presence valid */
1001 #define MC_MISC_AMD_CNTP 0x4000000000000000 /* Counter present */
1002 #define MC_MISC_AMD_LOCK 0x2000000000000000 /* Register locked */
1003 #define MC_MISC_AMD_INTP 0x1000000000000000 /* Int. type can generate interrupts */
1004 #define MC_MISC_AMD_LVT_MASK 0x00f0000000000000 /* Extended LVT offset */
1005 #define MC_MISC_AMD_LVT_SHIFT 52
1006 #define MC_MISC_AMD_CNTEN 0x0008000000000000 /* Counter enabled */
1007 #define MC_MISC_AMD_INT_MASK 0x0006000000000000 /* Interrupt type */
1008 #define MC_MISC_AMD_INT_LVT 0x0002000000000000 /* Interrupt via Extended LVT */
1009 #define MC_MISC_AMD_INT_SMI 0x0004000000000000 /* SMI */
1010 #define MC_MISC_AMD_OVERFLOW 0x0001000000000000 /* Counter overflow */
1011 #define MC_MISC_AMD_CNT_MASK 0x00000fff00000000 /* Counter value */
1012 #define MC_MISC_AMD_CNT_SHIFT 32
1013 #define MC_MISC_AMD_CNT_MAX 0xfff
1014 #define MC_MISC_AMD_PTR_MASK 0x00000000ff000000 /* Pointer to additional registers */
1015 #define MC_MISC_AMD_PTR_SHIFT 24
1016
1017 /* AMD Scalable MCA */
1018 #define MSR_SMCA_MC0_CTL 0xc0002000
1019 #define MSR_SMCA_MC0_STATUS 0xc0002001
1020 #define MSR_SMCA_MC0_ADDR 0xc0002002
1021 #define MSR_SMCA_MC0_MISC0 0xc0002003
1022 #define MSR_SMCA_MC_CTL(x) (MSR_SMCA_MC0_CTL + 0x10 * (x))
1023 #define MSR_SMCA_MC_STATUS(x) (MSR_SMCA_MC0_STATUS + 0x10 * (x))
1024 #define MSR_SMCA_MC_ADDR(x) (MSR_SMCA_MC0_ADDR + 0x10 * (x))
1025 #define MSR_SMCA_MC_MISC(x) (MSR_SMCA_MC0_MISC0 + 0x10 * (x))
1026
1027 /*
1028 * The following four 3-byte registers control the non-cacheable regions.
1029 * These registers must be written as three separate bytes.
1030 *
1031 * NCRx+0: A31-A24 of starting address
1032 * NCRx+1: A23-A16 of starting address
1033 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
1034 *
1035 * The non-cacheable region's starting address must be aligned to the
1036 * size indicated by the NCR_SIZE_xx field.
1037 */
1038 #define NCR1 0xc4
1039 #define NCR2 0xc7
1040 #define NCR3 0xca
1041 #define NCR4 0xcd
1042
1043 #define NCR_SIZE_0K 0
1044 #define NCR_SIZE_4K 1
1045 #define NCR_SIZE_8K 2
1046 #define NCR_SIZE_16K 3
1047 #define NCR_SIZE_32K 4
1048 #define NCR_SIZE_64K 5
1049 #define NCR_SIZE_128K 6
1050 #define NCR_SIZE_256K 7
1051 #define NCR_SIZE_512K 8
1052 #define NCR_SIZE_1M 9
1053 #define NCR_SIZE_2M 10
1054 #define NCR_SIZE_4M 11
1055 #define NCR_SIZE_8M 12
1056 #define NCR_SIZE_16M 13
1057 #define NCR_SIZE_32M 14
1058 #define NCR_SIZE_4G 15
1059
1060 /*
1061 * The address region registers are used to specify the location and
1062 * size for the eight address regions.
1063 *
1064 * ARRx + 0: A31-A24 of start address
1065 * ARRx + 1: A23-A16 of start address
1066 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
1067 */
1068 #define ARR0 0xc4
1069 #define ARR1 0xc7
1070 #define ARR2 0xca
1071 #define ARR3 0xcd
1072 #define ARR4 0xd0
1073 #define ARR5 0xd3
1074 #define ARR6 0xd6
1075 #define ARR7 0xd9
1076
1077 #define ARR_SIZE_0K 0
1078 #define ARR_SIZE_4K 1
1079 #define ARR_SIZE_8K 2
1080 #define ARR_SIZE_16K 3
1081 #define ARR_SIZE_32K 4
1082 #define ARR_SIZE_64K 5
1083 #define ARR_SIZE_128K 6
1084 #define ARR_SIZE_256K 7
1085 #define ARR_SIZE_512K 8
1086 #define ARR_SIZE_1M 9
1087 #define ARR_SIZE_2M 10
1088 #define ARR_SIZE_4M 11
1089 #define ARR_SIZE_8M 12
1090 #define ARR_SIZE_16M 13
1091 #define ARR_SIZE_32M 14
1092 #define ARR_SIZE_4G 15
1093
1094 /*
1095 * The region control registers specify the attributes associated with
1096 * the ARRx addres regions.
1097 */
1098 #define RCR0 0xdc
1099 #define RCR1 0xdd
1100 #define RCR2 0xde
1101 #define RCR3 0xdf
1102 #define RCR4 0xe0
1103 #define RCR5 0xe1
1104 #define RCR6 0xe2
1105 #define RCR7 0xe3
1106
1107 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */
1108 #define RCR_RCE 0x01 /* Enables caching for ARR7. */
1109 #define RCR_WWO 0x02 /* Weak write ordering. */
1110 #define RCR_WL 0x04 /* Weak locking. */
1111 #define RCR_WG 0x08 /* Write gathering. */
1112 #define RCR_WT 0x10 /* Write-through. */
1113 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */
1114
1115 /* AMD Write Allocate Top-Of-Memory and Control Register */
1116 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */
1117 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */
1118 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */
1119
1120 /* AMD64 MSR's */
1121 #define MSR_EFER 0xc0000080 /* extended features */
1122 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */
1123 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */
1124 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */
1125 #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */
1126 #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */
1127 #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */
1128 #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */
1129 #define MSR_TSC_AUX 0xc0000103
1130 #define MSR_PERFEVSEL0 0xc0010000
1131 #define MSR_PERFEVSEL1 0xc0010001
1132 #define MSR_PERFEVSEL2 0xc0010002
1133 #define MSR_PERFEVSEL3 0xc0010003
1134 #define MSR_K7_PERFCTR0 0xc0010004
1135 #define MSR_K7_PERFCTR1 0xc0010005
1136 #define MSR_K7_PERFCTR2 0xc0010006
1137 #define MSR_K7_PERFCTR3 0xc0010007
1138 #define MSR_SYSCFG 0xc0010010
1139 #define MSR_HWCR 0xc0010015
1140 #define MSR_IORRBASE0 0xc0010016
1141 #define MSR_IORRMASK0 0xc0010017
1142 #define MSR_IORRBASE1 0xc0010018
1143 #define MSR_IORRMASK1 0xc0010019
1144 #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */
1145 #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */
1146 #define MSR_NB_CFG1 0xc001001f /* NB configuration 1 */
1147 #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */
1148 #define MSR_MC0_CTL_MASK 0xc0010044
1149 #define MSR_AMDK8_IPM 0xc0010055
1150 #define MSR_P_STATE_LIMIT 0xc0010061 /* P-state Current Limit Register */
1151 #define MSR_P_STATE_CONTROL 0xc0010062 /* P-state Control Register */
1152 #define MSR_P_STATE_STATUS 0xc0010063 /* P-state Status Register */
1153 #define MSR_P_STATE_CONFIG(n) (0xc0010064 + (n)) /* P-state Config */
1154 #define MSR_SMM_ADDR 0xc0010112 /* SMM TSEG base address */
1155 #define MSR_SMM_MASK 0xc0010113 /* SMM TSEG address mask */
1156 #define MSR_VM_CR 0xc0010114 /* SVM: feature control */
1157 #define MSR_VM_HSAVE_PA 0xc0010117 /* SVM: host save area address */
1158 #define MSR_AMD_CPUID07 0xc0011002 /* CPUID 07 %ebx override */
1159 #define MSR_EXTFEATURES 0xc0011005 /* Extended CPUID Features override */
1160 #define MSR_LS_CFG 0xc0011020
1161 #define MSR_IC_CFG 0xc0011021 /* Instruction Cache Configuration */
1162 #define MSR_DE_CFG 0xc0011029 /* Decode Configuration */
1163
1164 /* MSR_VM_CR related */
1165 #define VM_CR_SVMDIS 0x10 /* SVM: disabled by BIOS */
1166
1167 #define AMDK8_SMIONCMPHALT (1ULL << 27)
1168 #define AMDK8_C1EONCMPHALT (1ULL << 28)
1169
1170 /* VIA ACE crypto featureset: for via_feature_rng */
1171 #define VIA_HAS_RNG 1 /* cpu has RNG */
1172
1173 /* VIA ACE crypto featureset: for via_feature_xcrypt */
1174 #define VIA_HAS_AES 1 /* cpu has AES */
1175 #define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */
1176 #define VIA_HAS_MM 4 /* cpu has RSA instructions */
1177 #define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */
1178
1179 /* Centaur Extended Feature flags */
1180 #define VIA_CPUID_HAS_RNG 0x000004
1181 #define VIA_CPUID_DO_RNG 0x000008
1182 #define VIA_CPUID_HAS_ACE 0x000040
1183 #define VIA_CPUID_DO_ACE 0x000080
1184 #define VIA_CPUID_HAS_ACE2 0x000100
1185 #define VIA_CPUID_DO_ACE2 0x000200
1186 #define VIA_CPUID_HAS_PHE 0x000400
1187 #define VIA_CPUID_DO_PHE 0x000800
1188 #define VIA_CPUID_HAS_PMM 0x001000
1189 #define VIA_CPUID_DO_PMM 0x002000
1190
1191 /* VIA ACE xcrypt-* instruction context control options */
1192 #define VIA_CRYPT_CWLO_ROUND_M 0x0000000f
1193 #define VIA_CRYPT_CWLO_ALG_M 0x00000070
1194 #define VIA_CRYPT_CWLO_ALG_AES 0x00000000
1195 #define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080
1196 #define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000
1197 #define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080
1198 #define VIA_CRYPT_CWLO_NORMAL 0x00000000
1199 #define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100
1200 #define VIA_CRYPT_CWLO_ENCRYPT 0x00000000
1201 #define VIA_CRYPT_CWLO_DECRYPT 0x00000200
1202 #define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */
1203 #define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */
1204 #define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */
1205
1206 #endif /* !_MACHINE_SPECIALREG_H_ */
Cache object: 687afd50c85464115febc36102d81ba8
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