The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/x86/include/specialreg.h

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    1 /*-
    2  * Copyright (c) 1991 The Regents of the University of California.
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 4. Neither the name of the University nor the names of its contributors
   14  *    may be used to endorse or promote products derived from this software
   15  *    without specific prior written permission.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  *
   29  *      from: @(#)specialreg.h  7.1 (Berkeley) 5/9/91
   30  * $FreeBSD: head/sys/x86/include/specialreg.h 298101 2016-04-16 06:07:13Z kib $
   31  */
   32 
   33 #ifndef _MACHINE_SPECIALREG_H_
   34 #define _MACHINE_SPECIALREG_H_
   35 
   36 /*
   37  * Bits in 386 special registers:
   38  */
   39 #define CR0_PE  0x00000001      /* Protected mode Enable */
   40 #define CR0_MP  0x00000002      /* "Math" (fpu) Present */
   41 #define CR0_EM  0x00000004      /* EMulate FPU instructions. (trap ESC only) */
   42 #define CR0_TS  0x00000008      /* Task Switched (if MP, trap ESC and WAIT) */
   43 #define CR0_PG  0x80000000      /* PaGing enable */
   44 
   45 /*
   46  * Bits in 486 special registers:
   47  */
   48 #define CR0_NE  0x00000020      /* Numeric Error enable (EX16 vs IRQ13) */
   49 #define CR0_WP  0x00010000      /* Write Protect (honor page protect in
   50                                                            all modes) */
   51 #define CR0_AM  0x00040000      /* Alignment Mask (set to enable AC flag) */
   52 #define CR0_NW  0x20000000      /* Not Write-through */
   53 #define CR0_CD  0x40000000      /* Cache Disable */
   54 
   55 #define CR3_PCID_SAVE 0x8000000000000000
   56 #define CR3_PCID_MASK 0xfff
   57 
   58 /*
   59  * Bits in PPro special registers
   60  */
   61 #define CR4_VME 0x00000001      /* Virtual 8086 mode extensions */
   62 #define CR4_PVI 0x00000002      /* Protected-mode virtual interrupts */
   63 #define CR4_TSD 0x00000004      /* Time stamp disable */
   64 #define CR4_DE  0x00000008      /* Debugging extensions */
   65 #define CR4_PSE 0x00000010      /* Page size extensions */
   66 #define CR4_PAE 0x00000020      /* Physical address extension */
   67 #define CR4_MCE 0x00000040      /* Machine check enable */
   68 #define CR4_PGE 0x00000080      /* Page global enable */
   69 #define CR4_PCE 0x00000100      /* Performance monitoring counter enable */
   70 #define CR4_FXSR 0x00000200     /* Fast FPU save/restore used by OS */
   71 #define CR4_XMM 0x00000400      /* enable SIMD/MMX2 to use except 16 */
   72 #define CR4_VMXE 0x00002000     /* enable VMX operation (Intel-specific) */
   73 #define CR4_FSGSBASE 0x00010000 /* Enable FS/GS BASE accessing instructions */
   74 #define CR4_PCIDE 0x00020000    /* Enable Context ID */
   75 #define CR4_XSAVE 0x00040000    /* XSETBV/XGETBV */
   76 #define CR4_SMEP 0x00100000     /* Supervisor-Mode Execution Prevention */
   77 
   78 /*
   79  * Bits in AMD64 special registers.  EFER is 64 bits wide.
   80  */
   81 #define EFER_SCE 0x000000001    /* System Call Extensions (R/W) */
   82 #define EFER_LME 0x000000100    /* Long mode enable (R/W) */
   83 #define EFER_LMA 0x000000400    /* Long mode active (R) */
   84 #define EFER_NXE 0x000000800    /* PTE No-Execute bit enable (R/W) */
   85 #define EFER_SVM 0x000001000    /* SVM enable bit for AMD, reserved for Intel */
   86 #define EFER_LMSLE 0x000002000  /* Long Mode Segment Limit Enable */
   87 #define EFER_FFXSR 0x000004000  /* Fast FXSAVE/FSRSTOR */
   88 #define EFER_TCE   0x000008000  /* Translation Cache Extension */
   89 
   90 /*
   91  * Intel Extended Features registers
   92  */
   93 #define XCR0    0               /* XFEATURE_ENABLED_MASK register */
   94 
   95 #define XFEATURE_ENABLED_X87            0x00000001
   96 #define XFEATURE_ENABLED_SSE            0x00000002
   97 #define XFEATURE_ENABLED_YMM_HI128      0x00000004
   98 #define XFEATURE_ENABLED_AVX            XFEATURE_ENABLED_YMM_HI128
   99 #define XFEATURE_ENABLED_BNDREGS        0x00000008
  100 #define XFEATURE_ENABLED_BNDCSR         0x00000010
  101 #define XFEATURE_ENABLED_OPMASK         0x00000020
  102 #define XFEATURE_ENABLED_ZMM_HI256      0x00000040
  103 #define XFEATURE_ENABLED_HI16_ZMM       0x00000080
  104 
  105 #define XFEATURE_AVX                                    \
  106     (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE | XFEATURE_ENABLED_AVX)
  107 #define XFEATURE_AVX512                                         \
  108     (XFEATURE_ENABLED_OPMASK | XFEATURE_ENABLED_ZMM_HI256 |     \
  109     XFEATURE_ENABLED_HI16_ZMM)
  110 #define XFEATURE_MPX                                    \
  111     (XFEATURE_ENABLED_BNDREGS | XFEATURE_ENABLED_BNDCSR)
  112 
  113 /*
  114  * CPUID instruction features register
  115  */
  116 #define CPUID_FPU       0x00000001
  117 #define CPUID_VME       0x00000002
  118 #define CPUID_DE        0x00000004
  119 #define CPUID_PSE       0x00000008
  120 #define CPUID_TSC       0x00000010
  121 #define CPUID_MSR       0x00000020
  122 #define CPUID_PAE       0x00000040
  123 #define CPUID_MCE       0x00000080
  124 #define CPUID_CX8       0x00000100
  125 #define CPUID_APIC      0x00000200
  126 #define CPUID_B10       0x00000400
  127 #define CPUID_SEP       0x00000800
  128 #define CPUID_MTRR      0x00001000
  129 #define CPUID_PGE       0x00002000
  130 #define CPUID_MCA       0x00004000
  131 #define CPUID_CMOV      0x00008000
  132 #define CPUID_PAT       0x00010000
  133 #define CPUID_PSE36     0x00020000
  134 #define CPUID_PSN       0x00040000
  135 #define CPUID_CLFSH     0x00080000
  136 #define CPUID_B20       0x00100000
  137 #define CPUID_DS        0x00200000
  138 #define CPUID_ACPI      0x00400000
  139 #define CPUID_MMX       0x00800000
  140 #define CPUID_FXSR      0x01000000
  141 #define CPUID_SSE       0x02000000
  142 #define CPUID_XMM       0x02000000
  143 #define CPUID_SSE2      0x04000000
  144 #define CPUID_SS        0x08000000
  145 #define CPUID_HTT       0x10000000
  146 #define CPUID_TM        0x20000000
  147 #define CPUID_IA64      0x40000000
  148 #define CPUID_PBE       0x80000000
  149 
  150 #define CPUID2_SSE3     0x00000001
  151 #define CPUID2_PCLMULQDQ 0x00000002
  152 #define CPUID2_DTES64   0x00000004
  153 #define CPUID2_MON      0x00000008
  154 #define CPUID2_DS_CPL   0x00000010
  155 #define CPUID2_VMX      0x00000020
  156 #define CPUID2_SMX      0x00000040
  157 #define CPUID2_EST      0x00000080
  158 #define CPUID2_TM2      0x00000100
  159 #define CPUID2_SSSE3    0x00000200
  160 #define CPUID2_CNXTID   0x00000400
  161 #define CPUID2_SDBG     0x00000800
  162 #define CPUID2_FMA      0x00001000
  163 #define CPUID2_CX16     0x00002000
  164 #define CPUID2_XTPR     0x00004000
  165 #define CPUID2_PDCM     0x00008000
  166 #define CPUID2_PCID     0x00020000
  167 #define CPUID2_DCA      0x00040000
  168 #define CPUID2_SSE41    0x00080000
  169 #define CPUID2_SSE42    0x00100000
  170 #define CPUID2_X2APIC   0x00200000
  171 #define CPUID2_MOVBE    0x00400000
  172 #define CPUID2_POPCNT   0x00800000
  173 #define CPUID2_TSCDLT   0x01000000
  174 #define CPUID2_AESNI    0x02000000
  175 #define CPUID2_XSAVE    0x04000000
  176 #define CPUID2_OSXSAVE  0x08000000
  177 #define CPUID2_AVX      0x10000000
  178 #define CPUID2_F16C     0x20000000
  179 #define CPUID2_RDRAND   0x40000000
  180 #define CPUID2_HV       0x80000000
  181 
  182 /*
  183  * Important bits in the Thermal and Power Management flags
  184  * CPUID.6 EAX and ECX.
  185  */
  186 #define CPUTPM1_SENSOR  0x00000001
  187 #define CPUTPM1_TURBO   0x00000002
  188 #define CPUTPM1_ARAT    0x00000004
  189 #define CPUTPM2_EFFREQ  0x00000001
  190 
  191 /*
  192  * Important bits in the AMD extended cpuid flags
  193  */
  194 #define AMDID_SYSCALL   0x00000800
  195 #define AMDID_MP        0x00080000
  196 #define AMDID_NX        0x00100000
  197 #define AMDID_EXT_MMX   0x00400000
  198 #define AMDID_FFXSR     0x02000000
  199 #define AMDID_PAGE1GB   0x04000000
  200 #define AMDID_RDTSCP    0x08000000
  201 #define AMDID_LM        0x20000000
  202 #define AMDID_EXT_3DNOW 0x40000000
  203 #define AMDID_3DNOW     0x80000000
  204 
  205 #define AMDID2_LAHF     0x00000001
  206 #define AMDID2_CMP      0x00000002
  207 #define AMDID2_SVM      0x00000004
  208 #define AMDID2_EXT_APIC 0x00000008
  209 #define AMDID2_CR8      0x00000010
  210 #define AMDID2_ABM      0x00000020
  211 #define AMDID2_SSE4A    0x00000040
  212 #define AMDID2_MAS      0x00000080
  213 #define AMDID2_PREFETCH 0x00000100
  214 #define AMDID2_OSVW     0x00000200
  215 #define AMDID2_IBS      0x00000400
  216 #define AMDID2_XOP      0x00000800
  217 #define AMDID2_SKINIT   0x00001000
  218 #define AMDID2_WDT      0x00002000
  219 #define AMDID2_LWP      0x00008000
  220 #define AMDID2_FMA4     0x00010000
  221 #define AMDID2_TCE      0x00020000
  222 #define AMDID2_NODE_ID  0x00080000
  223 #define AMDID2_TBM      0x00200000
  224 #define AMDID2_TOPOLOGY 0x00400000
  225 #define AMDID2_PCXC     0x00800000
  226 #define AMDID2_PNXC     0x01000000
  227 #define AMDID2_DBE      0x04000000
  228 #define AMDID2_PTSC     0x08000000
  229 #define AMDID2_PTSCEL2I 0x10000000
  230 
  231 /*
  232  * CPUID instruction 1 eax info
  233  */
  234 #define CPUID_STEPPING          0x0000000f
  235 #define CPUID_MODEL             0x000000f0
  236 #define CPUID_FAMILY            0x00000f00
  237 #define CPUID_EXT_MODEL         0x000f0000
  238 #define CPUID_EXT_FAMILY        0x0ff00000
  239 #ifdef __i386__
  240 #define CPUID_TO_MODEL(id) \
  241     ((((id) & CPUID_MODEL) >> 4) | \
  242     ((((id) & CPUID_FAMILY) >= 0x600) ? \
  243     (((id) & CPUID_EXT_MODEL) >> 12) : 0))
  244 #define CPUID_TO_FAMILY(id) \
  245     ((((id) & CPUID_FAMILY) >> 8) + \
  246     ((((id) & CPUID_FAMILY) == 0xf00) ? \
  247     (((id) & CPUID_EXT_FAMILY) >> 20) : 0))
  248 #else
  249 #define CPUID_TO_MODEL(id) \
  250     ((((id) & CPUID_MODEL) >> 4) | \
  251     (((id) & CPUID_EXT_MODEL) >> 12))
  252 #define CPUID_TO_FAMILY(id) \
  253     ((((id) & CPUID_FAMILY) >> 8) + \
  254     (((id) & CPUID_EXT_FAMILY) >> 20))
  255 #endif
  256 
  257 /*
  258  * CPUID instruction 1 ebx info
  259  */
  260 #define CPUID_BRAND_INDEX       0x000000ff
  261 #define CPUID_CLFUSH_SIZE       0x0000ff00
  262 #define CPUID_HTT_CORES         0x00ff0000
  263 #define CPUID_LOCAL_APIC_ID     0xff000000
  264 
  265 /*
  266  * CPUID instruction 5 info
  267  */
  268 #define CPUID5_MON_MIN_SIZE     0x0000ffff      /* eax */
  269 #define CPUID5_MON_MAX_SIZE     0x0000ffff      /* ebx */
  270 #define CPUID5_MON_MWAIT_EXT    0x00000001      /* ecx */
  271 #define CPUID5_MWAIT_INTRBREAK  0x00000002      /* ecx */
  272 
  273 /*
  274  * MWAIT cpu power states.  Lower 4 bits are sub-states.
  275  */
  276 #define MWAIT_C0        0xf0
  277 #define MWAIT_C1        0x00
  278 #define MWAIT_C2        0x10
  279 #define MWAIT_C3        0x20
  280 #define MWAIT_C4        0x30
  281 
  282 /*
  283  * MWAIT extensions.
  284  */
  285 /* Interrupt breaks MWAIT even when masked. */
  286 #define MWAIT_INTRBREAK         0x00000001
  287 
  288 /*
  289  * CPUID instruction 6 ecx info
  290  */
  291 #define CPUID_PERF_STAT         0x00000001
  292 #define CPUID_PERF_BIAS         0x00000008
  293 
  294 /* 
  295  * CPUID instruction 0xb ebx info.
  296  */
  297 #define CPUID_TYPE_INVAL        0
  298 #define CPUID_TYPE_SMT          1
  299 #define CPUID_TYPE_CORE         2
  300 
  301 /*
  302  * CPUID instruction 0xd Processor Extended State Enumeration Sub-leaf 1
  303  */
  304 #define CPUID_EXTSTATE_XSAVEOPT 0x00000001
  305 #define CPUID_EXTSTATE_XSAVEC   0x00000002
  306 #define CPUID_EXTSTATE_XINUSE   0x00000004
  307 #define CPUID_EXTSTATE_XSAVES   0x00000008
  308 
  309 /*
  310  * AMD extended function 8000_0007h edx info
  311  */
  312 #define AMDPM_TS                0x00000001
  313 #define AMDPM_FID               0x00000002
  314 #define AMDPM_VID               0x00000004
  315 #define AMDPM_TTP               0x00000008
  316 #define AMDPM_TM                0x00000010
  317 #define AMDPM_STC               0x00000020
  318 #define AMDPM_100MHZ_STEPS      0x00000040
  319 #define AMDPM_HW_PSTATE         0x00000080
  320 #define AMDPM_TSC_INVARIANT     0x00000100
  321 #define AMDPM_CPB               0x00000200
  322 
  323 /*
  324  * AMD extended function 8000_0008h ecx info
  325  */
  326 #define AMDID_CMP_CORES         0x000000ff
  327 #define AMDID_COREID_SIZE       0x0000f000
  328 #define AMDID_COREID_SIZE_SHIFT 12
  329 
  330 /*
  331  * CPUID instruction 7 Structured Extended Features, leaf 0 ebx info
  332  */
  333 #define CPUID_STDEXT_FSGSBASE   0x00000001
  334 #define CPUID_STDEXT_TSC_ADJUST 0x00000002
  335 #define CPUID_STDEXT_SGX        0x00000004
  336 #define CPUID_STDEXT_BMI1       0x00000008
  337 #define CPUID_STDEXT_HLE        0x00000010
  338 #define CPUID_STDEXT_AVX2       0x00000020
  339 #define CPUID_STDEXT_FDP_EXC    0x00000040
  340 #define CPUID_STDEXT_SMEP       0x00000080
  341 #define CPUID_STDEXT_BMI2       0x00000100
  342 #define CPUID_STDEXT_ERMS       0x00000200
  343 #define CPUID_STDEXT_INVPCID    0x00000400
  344 #define CPUID_STDEXT_RTM        0x00000800
  345 #define CPUID_STDEXT_PQM        0x00001000
  346 #define CPUID_STDEXT_NFPUSG     0x00002000
  347 #define CPUID_STDEXT_MPX        0x00004000
  348 #define CPUID_STDEXT_PQE        0x00008000
  349 #define CPUID_STDEXT_AVX512F    0x00010000
  350 #define CPUID_STDEXT_AVX512DQ   0x00020000
  351 #define CPUID_STDEXT_RDSEED     0x00040000
  352 #define CPUID_STDEXT_ADX        0x00080000
  353 #define CPUID_STDEXT_SMAP       0x00100000
  354 #define CPUID_STDEXT_AVX512IFMA 0x00200000
  355 #define CPUID_STDEXT_PCOMMIT    0x00400000
  356 #define CPUID_STDEXT_CLFLUSHOPT 0x00800000
  357 #define CPUID_STDEXT_CLWB       0x01000000
  358 #define CPUID_STDEXT_PROCTRACE  0x02000000
  359 #define CPUID_STDEXT_AVX512PF   0x04000000
  360 #define CPUID_STDEXT_AVX512ER   0x08000000
  361 #define CPUID_STDEXT_AVX512CD   0x10000000
  362 #define CPUID_STDEXT_SHA        0x20000000
  363 #define CPUID_STDEXT_AVX512BW   0x40000000
  364 
  365 /*
  366  * CPUID instruction 7 Structured Extended Features, leaf 0 ecx info
  367  */
  368 #define CPUID_STDEXT2_PREFETCHWT1 0x00000001
  369 #define CPUID_STDEXT2_UMIP      0x00000004
  370 #define CPUID_STDEXT2_PKU       0x00000008
  371 #define CPUID_STDEXT2_OSPKE     0x00000010
  372 #define CPUID_STDEXT2_RDPID     0x00400000
  373 #define CPUID_STDEXT2_SGXLC     0x40000000
  374 
  375 /*
  376  * CPUID manufacturers identifiers
  377  */
  378 #define AMD_VENDOR_ID           "AuthenticAMD"
  379 #define CENTAUR_VENDOR_ID       "CentaurHauls"
  380 #define CYRIX_VENDOR_ID         "CyrixInstead"
  381 #define INTEL_VENDOR_ID         "GenuineIntel"
  382 #define NEXGEN_VENDOR_ID        "NexGenDriven"
  383 #define NSC_VENDOR_ID           "Geode by NSC"
  384 #define RISE_VENDOR_ID          "RiseRiseRise"
  385 #define SIS_VENDOR_ID           "SiS SiS SiS "
  386 #define TRANSMETA_VENDOR_ID     "GenuineTMx86"
  387 #define UMC_VENDOR_ID           "UMC UMC UMC "
  388 
  389 /*
  390  * Model-specific registers for the i386 family
  391  */
  392 #define MSR_P5_MC_ADDR          0x000
  393 #define MSR_P5_MC_TYPE          0x001
  394 #define MSR_TSC                 0x010
  395 #define MSR_P5_CESR             0x011
  396 #define MSR_P5_CTR0             0x012
  397 #define MSR_P5_CTR1             0x013
  398 #define MSR_IA32_PLATFORM_ID    0x017
  399 #define MSR_APICBASE            0x01b
  400 #define MSR_EBL_CR_POWERON      0x02a
  401 #define MSR_TEST_CTL            0x033
  402 #define MSR_IA32_FEATURE_CONTROL 0x03a
  403 #define MSR_BIOS_UPDT_TRIG      0x079
  404 #define MSR_BBL_CR_D0           0x088
  405 #define MSR_BBL_CR_D1           0x089
  406 #define MSR_BBL_CR_D2           0x08a
  407 #define MSR_BIOS_SIGN           0x08b
  408 #define MSR_PERFCTR0            0x0c1
  409 #define MSR_PERFCTR1            0x0c2
  410 #define MSR_PLATFORM_INFO       0x0ce
  411 #define MSR_MPERF               0x0e7
  412 #define MSR_APERF               0x0e8
  413 #define MSR_IA32_EXT_CONFIG     0x0ee   /* Undocumented. Core Solo/Duo only */
  414 #define MSR_MTRRcap             0x0fe
  415 #define MSR_BBL_CR_ADDR         0x116
  416 #define MSR_BBL_CR_DECC         0x118
  417 #define MSR_BBL_CR_CTL          0x119
  418 #define MSR_BBL_CR_TRIG         0x11a
  419 #define MSR_BBL_CR_BUSY         0x11b
  420 #define MSR_BBL_CR_CTL3         0x11e
  421 #define MSR_SYSENTER_CS_MSR     0x174
  422 #define MSR_SYSENTER_ESP_MSR    0x175
  423 #define MSR_SYSENTER_EIP_MSR    0x176
  424 #define MSR_MCG_CAP             0x179
  425 #define MSR_MCG_STATUS          0x17a
  426 #define MSR_MCG_CTL             0x17b
  427 #define MSR_EVNTSEL0            0x186
  428 #define MSR_EVNTSEL1            0x187
  429 #define MSR_THERM_CONTROL       0x19a
  430 #define MSR_THERM_INTERRUPT     0x19b
  431 #define MSR_THERM_STATUS        0x19c
  432 #define MSR_IA32_MISC_ENABLE    0x1a0
  433 #define MSR_IA32_TEMPERATURE_TARGET     0x1a2
  434 #define MSR_TURBO_RATIO_LIMIT   0x1ad
  435 #define MSR_TURBO_RATIO_LIMIT1  0x1ae
  436 #define MSR_DEBUGCTLMSR         0x1d9
  437 #define MSR_LASTBRANCHFROMIP    0x1db
  438 #define MSR_LASTBRANCHTOIP      0x1dc
  439 #define MSR_LASTINTFROMIP       0x1dd
  440 #define MSR_LASTINTTOIP         0x1de
  441 #define MSR_ROB_CR_BKUPTMPDR6   0x1e0
  442 #define MSR_MTRRVarBase         0x200
  443 #define MSR_MTRR64kBase         0x250
  444 #define MSR_MTRR16kBase         0x258
  445 #define MSR_MTRR4kBase          0x268
  446 #define MSR_PAT                 0x277
  447 #define MSR_MC0_CTL2            0x280
  448 #define MSR_MTRRdefType         0x2ff
  449 #define MSR_MC0_CTL             0x400
  450 #define MSR_MC0_STATUS          0x401
  451 #define MSR_MC0_ADDR            0x402
  452 #define MSR_MC0_MISC            0x403
  453 #define MSR_MC1_CTL             0x404
  454 #define MSR_MC1_STATUS          0x405
  455 #define MSR_MC1_ADDR            0x406
  456 #define MSR_MC1_MISC            0x407
  457 #define MSR_MC2_CTL             0x408
  458 #define MSR_MC2_STATUS          0x409
  459 #define MSR_MC2_ADDR            0x40a
  460 #define MSR_MC2_MISC            0x40b
  461 #define MSR_MC3_CTL             0x40c
  462 #define MSR_MC3_STATUS          0x40d
  463 #define MSR_MC3_ADDR            0x40e
  464 #define MSR_MC3_MISC            0x40f
  465 #define MSR_MC4_CTL             0x410
  466 #define MSR_MC4_STATUS          0x411
  467 #define MSR_MC4_ADDR            0x412
  468 #define MSR_MC4_MISC            0x413
  469 #define MSR_RAPL_POWER_UNIT     0x606
  470 #define MSR_PKG_ENERGY_STATUS   0x611
  471 #define MSR_DRAM_ENERGY_STATUS  0x619
  472 #define MSR_PP0_ENERGY_STATUS   0x639
  473 #define MSR_PP1_ENERGY_STATUS   0x641
  474 #define MSR_TSC_DEADLINE        0x6e0   /* Writes are not serializing */
  475 
  476 /*
  477  * VMX MSRs
  478  */
  479 #define MSR_VMX_BASIC           0x480
  480 #define MSR_VMX_PINBASED_CTLS   0x481
  481 #define MSR_VMX_PROCBASED_CTLS  0x482
  482 #define MSR_VMX_EXIT_CTLS       0x483
  483 #define MSR_VMX_ENTRY_CTLS      0x484
  484 #define MSR_VMX_CR0_FIXED0      0x486
  485 #define MSR_VMX_CR0_FIXED1      0x487
  486 #define MSR_VMX_CR4_FIXED0      0x488
  487 #define MSR_VMX_CR4_FIXED1      0x489
  488 #define MSR_VMX_PROCBASED_CTLS2 0x48b
  489 #define MSR_VMX_EPT_VPID_CAP    0x48c
  490 #define MSR_VMX_TRUE_PINBASED_CTLS      0x48d
  491 #define MSR_VMX_TRUE_PROCBASED_CTLS     0x48e
  492 #define MSR_VMX_TRUE_EXIT_CTLS  0x48f
  493 #define MSR_VMX_TRUE_ENTRY_CTLS 0x490
  494 
  495 /*
  496  * X2APIC MSRs.
  497  * Writes are not serializing.
  498  */
  499 #define MSR_APIC_000            0x800
  500 #define MSR_APIC_ID             0x802
  501 #define MSR_APIC_VERSION        0x803
  502 #define MSR_APIC_TPR            0x808
  503 #define MSR_APIC_EOI            0x80b
  504 #define MSR_APIC_LDR            0x80d
  505 #define MSR_APIC_SVR            0x80f
  506 #define MSR_APIC_ISR0           0x810
  507 #define MSR_APIC_ISR1           0x811
  508 #define MSR_APIC_ISR2           0x812
  509 #define MSR_APIC_ISR3           0x813
  510 #define MSR_APIC_ISR4           0x814
  511 #define MSR_APIC_ISR5           0x815
  512 #define MSR_APIC_ISR6           0x816
  513 #define MSR_APIC_ISR7           0x817
  514 #define MSR_APIC_TMR0           0x818
  515 #define MSR_APIC_IRR0           0x820
  516 #define MSR_APIC_ESR            0x828
  517 #define MSR_APIC_LVT_CMCI       0x82F
  518 #define MSR_APIC_ICR            0x830
  519 #define MSR_APIC_LVT_TIMER      0x832
  520 #define MSR_APIC_LVT_THERMAL    0x833
  521 #define MSR_APIC_LVT_PCINT      0x834
  522 #define MSR_APIC_LVT_LINT0      0x835
  523 #define MSR_APIC_LVT_LINT1      0x836
  524 #define MSR_APIC_LVT_ERROR      0x837
  525 #define MSR_APIC_ICR_TIMER      0x838
  526 #define MSR_APIC_CCR_TIMER      0x839
  527 #define MSR_APIC_DCR_TIMER      0x83e
  528 #define MSR_APIC_SELF_IPI       0x83f
  529 
  530 #define MSR_IA32_XSS            0xda0
  531 
  532 /*
  533  * Constants related to MSR's.
  534  */
  535 #define APICBASE_RESERVED       0x000002ff
  536 #define APICBASE_BSP            0x00000100
  537 #define APICBASE_X2APIC         0x00000400
  538 #define APICBASE_ENABLED        0x00000800
  539 #define APICBASE_ADDRESS        0xfffff000
  540 
  541 /* MSR_IA32_FEATURE_CONTROL related */
  542 #define IA32_FEATURE_CONTROL_LOCK       0x01    /* lock bit */
  543 #define IA32_FEATURE_CONTROL_SMX_EN     0x02    /* enable VMX inside SMX */
  544 #define IA32_FEATURE_CONTROL_VMX_EN     0x04    /* enable VMX outside SMX */
  545 
  546 /* MSR IA32_MISC_ENABLE */
  547 #define IA32_MISC_EN_FASTSTR    0x0000000000000001ULL
  548 #define IA32_MISC_EN_ATCCE      0x0000000000000008ULL
  549 #define IA32_MISC_EN_PERFMON    0x0000000000000080ULL
  550 #define IA32_MISC_EN_PEBSU      0x0000000000001000ULL
  551 #define IA32_MISC_EN_ESSTE      0x0000000000010000ULL
  552 #define IA32_MISC_EN_MONE       0x0000000000040000ULL
  553 #define IA32_MISC_EN_LIMCPUID   0x0000000000400000ULL
  554 #define IA32_MISC_EN_xTPRD      0x0000000000800000ULL
  555 #define IA32_MISC_EN_XDD        0x0000000400000000ULL
  556 
  557 /*
  558  * PAT modes.
  559  */
  560 #define PAT_UNCACHEABLE         0x00
  561 #define PAT_WRITE_COMBINING     0x01
  562 #define PAT_WRITE_THROUGH       0x04
  563 #define PAT_WRITE_PROTECTED     0x05
  564 #define PAT_WRITE_BACK          0x06
  565 #define PAT_UNCACHED            0x07
  566 #define PAT_VALUE(i, m)         ((long long)(m) << (8 * (i)))
  567 #define PAT_MASK(i)             PAT_VALUE(i, 0xff)
  568 
  569 /*
  570  * Constants related to MTRRs
  571  */
  572 #define MTRR_UNCACHEABLE        0x00
  573 #define MTRR_WRITE_COMBINING    0x01
  574 #define MTRR_WRITE_THROUGH      0x04
  575 #define MTRR_WRITE_PROTECTED    0x05
  576 #define MTRR_WRITE_BACK         0x06
  577 #define MTRR_N64K               8       /* numbers of fixed-size entries */
  578 #define MTRR_N16K               16
  579 #define MTRR_N4K                64
  580 #define MTRR_CAP_WC             0x0000000000000400
  581 #define MTRR_CAP_FIXED          0x0000000000000100
  582 #define MTRR_CAP_VCNT           0x00000000000000ff
  583 #define MTRR_DEF_ENABLE         0x0000000000000800
  584 #define MTRR_DEF_FIXED_ENABLE   0x0000000000000400
  585 #define MTRR_DEF_TYPE           0x00000000000000ff
  586 #define MTRR_PHYSBASE_PHYSBASE  0x000ffffffffff000
  587 #define MTRR_PHYSBASE_TYPE      0x00000000000000ff
  588 #define MTRR_PHYSMASK_PHYSMASK  0x000ffffffffff000
  589 #define MTRR_PHYSMASK_VALID     0x0000000000000800
  590 
  591 /*
  592  * Cyrix configuration registers, accessible as IO ports.
  593  */
  594 #define CCR0                    0xc0    /* Configuration control register 0 */
  595 #define CCR0_NC0                0x01    /* First 64K of each 1M memory region is
  596                                                                    non-cacheable */
  597 #define CCR0_NC1                0x02    /* 640K-1M region is non-cacheable */
  598 #define CCR0_A20M               0x04    /* Enables A20M# input pin */
  599 #define CCR0_KEN                0x08    /* Enables KEN# input pin */
  600 #define CCR0_FLUSH              0x10    /* Enables FLUSH# input pin */
  601 #define CCR0_BARB               0x20    /* Flushes internal cache when entering hold
  602                                                                    state */
  603 #define CCR0_CO                 0x40    /* Cache org: 1=direct mapped, 0=2x set
  604                                                                    assoc */
  605 #define CCR0_SUSPEND    0x80    /* Enables SUSP# and SUSPA# pins */
  606 
  607 #define CCR1                    0xc1    /* Configuration control register 1 */
  608 #define CCR1_RPL                0x01    /* Enables RPLSET and RPLVAL# pins */
  609 #define CCR1_SMI                0x02    /* Enables SMM pins */
  610 #define CCR1_SMAC               0x04    /* System management memory access */
  611 #define CCR1_MMAC               0x08    /* Main memory access */
  612 #define CCR1_NO_LOCK    0x10    /* Negate LOCK# */
  613 #define CCR1_SM3                0x80    /* SMM address space address region 3 */
  614 
  615 #define CCR2                    0xc2
  616 #define CCR2_WB                 0x02    /* Enables WB cache interface pins */
  617 #define CCR2_SADS               0x02    /* Slow ADS */
  618 #define CCR2_LOCK_NW    0x04    /* LOCK NW Bit */
  619 #define CCR2_SUSP_HLT   0x08    /* Suspend on HALT */
  620 #define CCR2_WT1                0x10    /* WT region 1 */
  621 #define CCR2_WPR1               0x10    /* Write-protect region 1 */
  622 #define CCR2_BARB               0x20    /* Flushes write-back cache when entering
  623                                                                    hold state. */
  624 #define CCR2_BWRT               0x40    /* Enables burst write cycles */
  625 #define CCR2_USE_SUSP   0x80    /* Enables suspend pins */
  626 
  627 #define CCR3                    0xc3
  628 #define CCR3_SMILOCK    0x01    /* SMM register lock */
  629 #define CCR3_NMI                0x02    /* Enables NMI during SMM */
  630 #define CCR3_LINBRST    0x04    /* Linear address burst cycles */
  631 #define CCR3_SMMMODE    0x08    /* SMM Mode */
  632 #define CCR3_MAPEN0             0x10    /* Enables Map0 */
  633 #define CCR3_MAPEN1             0x20    /* Enables Map1 */
  634 #define CCR3_MAPEN2             0x40    /* Enables Map2 */
  635 #define CCR3_MAPEN3             0x80    /* Enables Map3 */
  636 
  637 #define CCR4                    0xe8
  638 #define CCR4_IOMASK             0x07
  639 #define CCR4_MEM                0x08    /* Enables momory bypassing */
  640 #define CCR4_DTE                0x10    /* Enables directory table entry cache */
  641 #define CCR4_FASTFPE    0x20    /* Fast FPU exception */
  642 #define CCR4_CPUID              0x80    /* Enables CPUID instruction */
  643 
  644 #define CCR5                    0xe9
  645 #define CCR5_WT_ALLOC   0x01    /* Write-through allocate */
  646 #define CCR5_SLOP               0x02    /* LOOP instruction slowed down */
  647 #define CCR5_LBR1               0x10    /* Local bus region 1 */
  648 #define CCR5_ARREN              0x20    /* Enables ARR region */
  649 
  650 #define CCR6                    0xea
  651 
  652 #define CCR7                    0xeb
  653 
  654 /* Performance Control Register (5x86 only). */
  655 #define PCR0                    0x20
  656 #define PCR0_RSTK               0x01    /* Enables return stack */
  657 #define PCR0_BTB                0x02    /* Enables branch target buffer */
  658 #define PCR0_LOOP               0x04    /* Enables loop */
  659 #define PCR0_AIS                0x08    /* Enables all instrcutions stalled to
  660                                                                    serialize pipe. */
  661 #define PCR0_MLR                0x10    /* Enables reordering of misaligned loads */
  662 #define PCR0_BTBRT              0x40    /* Enables BTB test register. */
  663 #define PCR0_LSSER              0x80    /* Disable reorder */
  664 
  665 /* Device Identification Registers */
  666 #define DIR0                    0xfe
  667 #define DIR1                    0xff
  668 
  669 /*
  670  * Machine Check register constants.
  671  */
  672 #define MCG_CAP_COUNT           0x000000ff
  673 #define MCG_CAP_CTL_P           0x00000100
  674 #define MCG_CAP_EXT_P           0x00000200
  675 #define MCG_CAP_CMCI_P          0x00000400
  676 #define MCG_CAP_TES_P           0x00000800
  677 #define MCG_CAP_EXT_CNT         0x00ff0000
  678 #define MCG_CAP_SER_P           0x01000000
  679 #define MCG_STATUS_RIPV         0x00000001
  680 #define MCG_STATUS_EIPV         0x00000002
  681 #define MCG_STATUS_MCIP         0x00000004
  682 #define MCG_CTL_ENABLE          0xffffffffffffffff
  683 #define MCG_CTL_DISABLE         0x0000000000000000
  684 #define MSR_MC_CTL(x)           (MSR_MC0_CTL + (x) * 4)
  685 #define MSR_MC_STATUS(x)        (MSR_MC0_STATUS + (x) * 4)
  686 #define MSR_MC_ADDR(x)          (MSR_MC0_ADDR + (x) * 4)
  687 #define MSR_MC_MISC(x)          (MSR_MC0_MISC + (x) * 4)
  688 #define MSR_MC_CTL2(x)          (MSR_MC0_CTL2 + (x))    /* If MCG_CAP_CMCI_P */
  689 #define MC_STATUS_MCA_ERROR     0x000000000000ffff
  690 #define MC_STATUS_MODEL_ERROR   0x00000000ffff0000
  691 #define MC_STATUS_OTHER_INFO    0x01ffffff00000000
  692 #define MC_STATUS_COR_COUNT     0x001fffc000000000      /* If MCG_CAP_CMCI_P */
  693 #define MC_STATUS_TES_STATUS    0x0060000000000000      /* If MCG_CAP_TES_P */
  694 #define MC_STATUS_AR            0x0080000000000000      /* If MCG_CAP_TES_P */
  695 #define MC_STATUS_S             0x0100000000000000      /* If MCG_CAP_TES_P */
  696 #define MC_STATUS_PCC           0x0200000000000000
  697 #define MC_STATUS_ADDRV         0x0400000000000000
  698 #define MC_STATUS_MISCV         0x0800000000000000
  699 #define MC_STATUS_EN            0x1000000000000000
  700 #define MC_STATUS_UC            0x2000000000000000
  701 #define MC_STATUS_OVER          0x4000000000000000
  702 #define MC_STATUS_VAL           0x8000000000000000
  703 #define MC_MISC_RA_LSB          0x000000000000003f      /* If MCG_CAP_SER_P */
  704 #define MC_MISC_ADDRESS_MODE    0x00000000000001c0      /* If MCG_CAP_SER_P */
  705 #define MC_CTL2_THRESHOLD       0x0000000000007fff
  706 #define MC_CTL2_CMCI_EN         0x0000000040000000
  707 
  708 /*
  709  * The following four 3-byte registers control the non-cacheable regions.
  710  * These registers must be written as three separate bytes.
  711  *
  712  * NCRx+0: A31-A24 of starting address
  713  * NCRx+1: A23-A16 of starting address
  714  * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
  715  *
  716  * The non-cacheable region's starting address must be aligned to the
  717  * size indicated by the NCR_SIZE_xx field.
  718  */
  719 #define NCR1    0xc4
  720 #define NCR2    0xc7
  721 #define NCR3    0xca
  722 #define NCR4    0xcd
  723 
  724 #define NCR_SIZE_0K     0
  725 #define NCR_SIZE_4K     1
  726 #define NCR_SIZE_8K     2
  727 #define NCR_SIZE_16K    3
  728 #define NCR_SIZE_32K    4
  729 #define NCR_SIZE_64K    5
  730 #define NCR_SIZE_128K   6
  731 #define NCR_SIZE_256K   7
  732 #define NCR_SIZE_512K   8
  733 #define NCR_SIZE_1M     9
  734 #define NCR_SIZE_2M     10
  735 #define NCR_SIZE_4M     11
  736 #define NCR_SIZE_8M     12
  737 #define NCR_SIZE_16M    13
  738 #define NCR_SIZE_32M    14
  739 #define NCR_SIZE_4G     15
  740 
  741 /*
  742  * The address region registers are used to specify the location and
  743  * size for the eight address regions.
  744  *
  745  * ARRx + 0: A31-A24 of start address
  746  * ARRx + 1: A23-A16 of start address
  747  * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
  748  */
  749 #define ARR0    0xc4
  750 #define ARR1    0xc7
  751 #define ARR2    0xca
  752 #define ARR3    0xcd
  753 #define ARR4    0xd0
  754 #define ARR5    0xd3
  755 #define ARR6    0xd6
  756 #define ARR7    0xd9
  757 
  758 #define ARR_SIZE_0K             0
  759 #define ARR_SIZE_4K             1
  760 #define ARR_SIZE_8K             2
  761 #define ARR_SIZE_16K    3
  762 #define ARR_SIZE_32K    4
  763 #define ARR_SIZE_64K    5
  764 #define ARR_SIZE_128K   6
  765 #define ARR_SIZE_256K   7
  766 #define ARR_SIZE_512K   8
  767 #define ARR_SIZE_1M             9
  768 #define ARR_SIZE_2M             10
  769 #define ARR_SIZE_4M             11
  770 #define ARR_SIZE_8M             12
  771 #define ARR_SIZE_16M    13
  772 #define ARR_SIZE_32M    14
  773 #define ARR_SIZE_4G             15
  774 
  775 /*
  776  * The region control registers specify the attributes associated with
  777  * the ARRx addres regions.
  778  */
  779 #define RCR0    0xdc
  780 #define RCR1    0xdd
  781 #define RCR2    0xde
  782 #define RCR3    0xdf
  783 #define RCR4    0xe0
  784 #define RCR5    0xe1
  785 #define RCR6    0xe2
  786 #define RCR7    0xe3
  787 
  788 #define RCR_RCD 0x01    /* Disables caching for ARRx (x = 0-6). */
  789 #define RCR_RCE 0x01    /* Enables caching for ARR7. */
  790 #define RCR_WWO 0x02    /* Weak write ordering. */
  791 #define RCR_WL  0x04    /* Weak locking. */
  792 #define RCR_WG  0x08    /* Write gathering. */
  793 #define RCR_WT  0x10    /* Write-through. */
  794 #define RCR_NLB 0x20    /* LBA# pin is not asserted. */
  795 
  796 /* AMD Write Allocate Top-Of-Memory and Control Register */
  797 #define AMD_WT_ALLOC_TME        0x40000 /* top-of-memory enable */
  798 #define AMD_WT_ALLOC_PRE        0x20000 /* programmable range enable */
  799 #define AMD_WT_ALLOC_FRE        0x10000 /* fixed (A0000-FFFFF) range enable */
  800 
  801 /* AMD64 MSR's */
  802 #define MSR_EFER        0xc0000080      /* extended features */
  803 #define MSR_STAR        0xc0000081      /* legacy mode SYSCALL target/cs/ss */
  804 #define MSR_LSTAR       0xc0000082      /* long mode SYSCALL target rip */
  805 #define MSR_CSTAR       0xc0000083      /* compat mode SYSCALL target rip */
  806 #define MSR_SF_MASK     0xc0000084      /* syscall flags mask */
  807 #define MSR_FSBASE      0xc0000100      /* base address of the %fs "segment" */
  808 #define MSR_GSBASE      0xc0000101      /* base address of the %gs "segment" */
  809 #define MSR_KGSBASE     0xc0000102      /* base address of the kernel %gs */
  810 #define MSR_PERFEVSEL0  0xc0010000
  811 #define MSR_PERFEVSEL1  0xc0010001
  812 #define MSR_PERFEVSEL2  0xc0010002
  813 #define MSR_PERFEVSEL3  0xc0010003
  814 #define MSR_K7_PERFCTR0 0xc0010004
  815 #define MSR_K7_PERFCTR1 0xc0010005
  816 #define MSR_K7_PERFCTR2 0xc0010006
  817 #define MSR_K7_PERFCTR3 0xc0010007
  818 #define MSR_SYSCFG      0xc0010010
  819 #define MSR_HWCR        0xc0010015
  820 #define MSR_IORRBASE0   0xc0010016
  821 #define MSR_IORRMASK0   0xc0010017
  822 #define MSR_IORRBASE1   0xc0010018
  823 #define MSR_IORRMASK1   0xc0010019
  824 #define MSR_TOP_MEM     0xc001001a      /* boundary for ram below 4G */
  825 #define MSR_TOP_MEM2    0xc001001d      /* boundary for ram above 4G */
  826 #define MSR_NB_CFG1     0xc001001f      /* NB configuration 1 */
  827 #define MSR_P_STATE_LIMIT 0xc0010061    /* P-state Current Limit Register */
  828 #define MSR_P_STATE_CONTROL 0xc0010062  /* P-state Control Register */
  829 #define MSR_P_STATE_STATUS 0xc0010063   /* P-state Status Register */
  830 #define MSR_P_STATE_CONFIG(n) (0xc0010064 + (n)) /* P-state Config */
  831 #define MSR_SMM_ADDR    0xc0010112      /* SMM TSEG base address */
  832 #define MSR_SMM_MASK    0xc0010113      /* SMM TSEG address mask */
  833 #define MSR_EXTFEATURES 0xc0011005      /* Extended CPUID Features override */
  834 #define MSR_IC_CFG      0xc0011021      /* Instruction Cache Configuration */
  835 #define MSR_K8_UCODE_UPDATE     0xc0010020      /* update microcode */
  836 #define MSR_MC0_CTL_MASK        0xc0010044
  837 #define MSR_VM_CR               0xc0010114 /* SVM: feature control */
  838 #define MSR_VM_HSAVE_PA         0xc0010117 /* SVM: host save area address */
  839 
  840 /* MSR_VM_CR related */
  841 #define VM_CR_SVMDIS            0x10    /* SVM: disabled by BIOS */
  842 
  843 /* VIA ACE crypto featureset: for via_feature_rng */
  844 #define VIA_HAS_RNG             1       /* cpu has RNG */
  845 
  846 /* VIA ACE crypto featureset: for via_feature_xcrypt */
  847 #define VIA_HAS_AES             1       /* cpu has AES */
  848 #define VIA_HAS_SHA             2       /* cpu has SHA1 & SHA256 */
  849 #define VIA_HAS_MM              4       /* cpu has RSA instructions */
  850 #define VIA_HAS_AESCTR          8       /* cpu has AES-CTR instructions */
  851 
  852 /* Centaur Extended Feature flags */
  853 #define VIA_CPUID_HAS_RNG       0x000004
  854 #define VIA_CPUID_DO_RNG        0x000008
  855 #define VIA_CPUID_HAS_ACE       0x000040
  856 #define VIA_CPUID_DO_ACE        0x000080
  857 #define VIA_CPUID_HAS_ACE2      0x000100
  858 #define VIA_CPUID_DO_ACE2       0x000200
  859 #define VIA_CPUID_HAS_PHE       0x000400
  860 #define VIA_CPUID_DO_PHE        0x000800
  861 #define VIA_CPUID_HAS_PMM       0x001000
  862 #define VIA_CPUID_DO_PMM        0x002000
  863 
  864 /* VIA ACE xcrypt-* instruction context control options */
  865 #define VIA_CRYPT_CWLO_ROUND_M          0x0000000f
  866 #define VIA_CRYPT_CWLO_ALG_M            0x00000070
  867 #define VIA_CRYPT_CWLO_ALG_AES          0x00000000
  868 #define VIA_CRYPT_CWLO_KEYGEN_M         0x00000080
  869 #define VIA_CRYPT_CWLO_KEYGEN_HW        0x00000000
  870 #define VIA_CRYPT_CWLO_KEYGEN_SW        0x00000080
  871 #define VIA_CRYPT_CWLO_NORMAL           0x00000000
  872 #define VIA_CRYPT_CWLO_INTERMEDIATE     0x00000100
  873 #define VIA_CRYPT_CWLO_ENCRYPT          0x00000000
  874 #define VIA_CRYPT_CWLO_DECRYPT          0x00000200
  875 #define VIA_CRYPT_CWLO_KEY128           0x0000000a      /* 128bit, 10 rds */
  876 #define VIA_CRYPT_CWLO_KEY192           0x0000040c      /* 192bit, 12 rds */
  877 #define VIA_CRYPT_CWLO_KEY256           0x0000080e      /* 256bit, 15 rds */
  878 
  879 #endif /* !_MACHINE_SPECIALREG_H_ */

Cache object: 687afd50c85464115febc36102d81ba8


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