1 /*-
2 * Copyright (c) 1995 Bruce D. Evans.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * $FreeBSD$
30 */
31
32 #ifndef _X86_X86_VAR_H_
33 #define _X86_X86_VAR_H_
34
35 /*
36 * Miscellaneous machine-dependent declarations.
37 */
38
39 extern long Maxmem;
40 extern u_int basemem;
41 extern int busdma_swi_pending;
42 extern u_int cpu_exthigh;
43 extern u_int cpu_feature;
44 extern u_int cpu_feature2;
45 extern u_int amd_feature;
46 extern u_int amd_feature2;
47 extern u_int amd_rascap;
48 extern u_int amd_pminfo;
49 extern u_int amd_extended_feature_extensions;
50 extern u_int via_feature_rng;
51 extern u_int via_feature_xcrypt;
52 extern u_int cpu_clflush_line_size;
53 extern u_int cpu_stdext_feature;
54 extern u_int cpu_stdext_feature2;
55 extern u_int cpu_stdext_feature3;
56 extern uint64_t cpu_ia32_arch_caps;
57 extern u_int cpu_fxsr;
58 extern u_int cpu_high;
59 extern u_int cpu_id;
60 extern u_int cpu_max_ext_state_size;
61 extern u_int cpu_mxcsr_mask;
62 extern u_int cpu_procinfo;
63 extern u_int cpu_procinfo2;
64 extern char cpu_vendor[];
65 extern u_int cpu_vendor_id;
66 extern u_int cpu_mon_mwait_flags;
67 extern u_int cpu_mon_min_size;
68 extern u_int cpu_mon_max_size;
69 extern u_int cpu_maxphyaddr;
70 extern u_int hv_high;
71 extern char hv_vendor[];
72 extern char kstack[];
73 extern char sigcode[];
74 extern int szsigcode;
75 extern int vm_page_dump_size;
76 extern int workaround_erratum383;
77 extern int _udatasel;
78 extern int _ucodesel;
79 extern int _ucode32sel;
80 extern int _ufssel;
81 extern int _ugssel;
82 extern int use_xsave;
83 extern uint64_t xsave_mask;
84 extern u_int max_apic_id;
85 extern int pti;
86 extern int hw_ibrs_ibpb_active;
87 extern int hw_mds_disable;
88 extern int hw_ssb_active;
89 extern int x86_taa_enable;
90 extern int cpu_flush_rsb_ctxsw;
91 extern int x86_rngds_mitg_enable;
92 extern int cpu_amdc1e_bug;
93
94 struct pcb;
95 struct thread;
96 struct reg;
97 struct fpreg;
98 struct dbreg;
99 struct dumperinfo;
100 struct trapframe;
101
102 /*
103 * The interface type of the interrupt handler entry point cannot be
104 * expressed in C. Use simplest non-variadic function type as an
105 * approximation.
106 */
107 typedef void alias_for_inthand_t(void);
108
109 /*
110 * Returns the maximum physical address that can be used with the
111 * current system.
112 */
113 static __inline vm_paddr_t
114 cpu_getmaxphyaddr(void)
115 {
116 #if defined(__i386__) && !defined(PAE)
117 return (0xffffffff);
118 #else
119 return ((1ULL << cpu_maxphyaddr) - 1);
120 #endif
121 }
122
123 bool acpi_get_fadt_bootflags(uint16_t *flagsp);
124 void *alloc_fpusave(int flags);
125 void busdma_swi(void);
126 u_int cpu_auxmsr(void);
127 bool cpu_mwait_usable(void);
128 void cpu_probe_amdc1e(void);
129 void cpu_setregs(void);
130 void x86_clear_dbregs(struct pcb *pcb);
131 bool disable_wp(void);
132 void restore_wp(bool old_wp);
133 void dump_add_page(vm_paddr_t);
134 void dump_drop_page(vm_paddr_t);
135 void finishidentcpu(void);
136 void identify_cpu1(void);
137 void identify_cpu2(void);
138 void identify_cpu_fixup_bsp(void);
139 void identify_hypervisor(void);
140 void initializecpu(void);
141 void initializecpucache(void);
142 bool fix_cpuid(void);
143 void fillw(int /*u_short*/ pat, void *base, size_t cnt);
144 int is_physical_memory(vm_paddr_t addr);
145 int isa_nmi(int cd);
146 void handle_ibrs_entry(void);
147 void handle_ibrs_exit(void);
148 void hw_ibrs_recalculate(bool all_cpus);
149 void hw_mds_recalculate(void);
150 void hw_ssb_recalculate(bool all_cpus);
151 void x86_taa_recalculate(void);
152 void x86_rngds_mitg_recalculate(bool all_cpus);
153 void nmi_call_kdb(u_int cpu, u_int type, struct trapframe *frame);
154 void nmi_call_kdb_smp(u_int type, struct trapframe *frame);
155 void nmi_handle_intr(u_int type, struct trapframe *frame);
156 void pagecopy(void *from, void *to);
157 void printcpuinfo(void);
158 int pti_get_default(void);
159 int user_dbreg_trap(register_t dr6);
160 int minidumpsys(struct dumperinfo *);
161 struct pcb *get_pcb_td(struct thread *td);
162 uint64_t rdtsc_ordered(void);
163
164 #define MSR_OP_ANDNOT 0x00000001
165 #define MSR_OP_OR 0x00000002
166 #define MSR_OP_WRITE 0x00000003
167 #define MSR_OP_LOCAL 0x10000000
168 #define MSR_OP_SCHED 0x20000000
169 #define MSR_OP_RENDEZVOUS 0x30000000
170 void x86_msr_op(u_int msr, u_int op, uint64_t arg1);
171
172 #endif
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