The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/x86/iommu/intel_dmar.h

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    1 /*-
    2  * Copyright (c) 2013 The FreeBSD Foundation
    3  * All rights reserved.
    4  *
    5  * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
    6  * under sponsorship from the FreeBSD Foundation.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  *
   29  * $FreeBSD: releng/10.2/sys/x86/iommu/intel_dmar.h 281545 2015-04-15 06:56:51Z kib $
   30  */
   31 
   32 #ifndef __X86_IOMMU_INTEL_DMAR_H
   33 #define __X86_IOMMU_INTEL_DMAR_H
   34 
   35 /* Host or physical memory address, after translation. */
   36 typedef uint64_t dmar_haddr_t;
   37 /* Guest or bus address, before translation. */
   38 typedef uint64_t dmar_gaddr_t;
   39 
   40 struct dmar_qi_genseq {
   41         u_int gen;
   42         uint32_t seq;
   43 };
   44 
   45 struct dmar_map_entry {
   46         dmar_gaddr_t start;
   47         dmar_gaddr_t end;
   48         dmar_gaddr_t free_after;        /* Free space after the entry */
   49         dmar_gaddr_t free_down;         /* Max free space below the
   50                                            current R/B tree node */
   51         u_int flags;
   52         TAILQ_ENTRY(dmar_map_entry) dmamap_link; /* Link for dmamap entries */
   53         RB_ENTRY(dmar_map_entry) rb_entry;       /* Links for ctx entries */
   54         TAILQ_ENTRY(dmar_map_entry) unroll_link; /* Link for unroll after
   55                                                     dmamap_load failure */
   56         struct dmar_ctx *ctx;
   57         struct dmar_qi_genseq gseq;
   58 };
   59 
   60 RB_HEAD(dmar_gas_entries_tree, dmar_map_entry);
   61 RB_PROTOTYPE(dmar_gas_entries_tree, dmar_map_entry, rb_entry,
   62     dmar_gas_cmp_entries);
   63 
   64 #define DMAR_MAP_ENTRY_PLACE    0x0001  /* Fake entry */
   65 #define DMAR_MAP_ENTRY_RMRR     0x0002  /* Permanent, not linked by
   66                                            dmamap_link */
   67 #define DMAR_MAP_ENTRY_MAP      0x0004  /* Busdma created, linked by
   68                                            dmamap_link */
   69 #define DMAR_MAP_ENTRY_UNMAPPED 0x0010  /* No backing pages */
   70 #define DMAR_MAP_ENTRY_QI_NF    0x0020  /* qi task, do not free entry */
   71 #define DMAR_MAP_ENTRY_READ     0x1000  /* Read permitted */
   72 #define DMAR_MAP_ENTRY_WRITE    0x2000  /* Write permitted */
   73 #define DMAR_MAP_ENTRY_SNOOP    0x4000  /* Snoop */
   74 #define DMAR_MAP_ENTRY_TM       0x8000  /* Transient */
   75 
   76 struct dmar_ctx {
   77         uint16_t rid;   /* pci RID */
   78         int domain;     /* DID */
   79         int mgaw;       /* Real max address width */
   80         int agaw;       /* Adjusted guest address width */
   81         int pglvl;      /* The pagelevel */
   82         int awlvl;      /* The pagelevel as the bitmask, to set in
   83                            context entry */
   84         dmar_gaddr_t end;/* Highest address + 1 in the guest AS */
   85         u_int refs;     /* References to the context, from tags */
   86         struct dmar_unit *dmar;
   87         struct bus_dma_tag_dmar ctx_tag; /* Root tag */
   88         struct mtx lock;
   89         LIST_ENTRY(dmar_ctx) link;      /* Member in the dmar list */
   90         vm_object_t pgtbl_obj;          /* Page table pages */
   91         u_int flags;                    /* Protected by dmar lock */
   92         uint64_t last_fault_rec[2];     /* Last fault reported */
   93         u_int entries_cnt;
   94         u_long loads;
   95         u_long unloads;
   96         struct dmar_gas_entries_tree rb_root;
   97         struct dmar_map_entries_tailq unload_entries; /* Entries to unload */
   98         struct dmar_map_entry *first_place, *last_place;
   99         struct task unload_task;
  100 };
  101 
  102 /* struct dmar_ctx flags */
  103 #define DMAR_CTX_FAULTED        0x0001  /* Fault was reported,
  104                                            last_fault_rec is valid */
  105 #define DMAR_CTX_IDMAP          0x0002  /* Context uses identity page table */
  106 #define DMAR_CTX_RMRR           0x0004  /* Context contains RMRR entry,
  107                                            cannot be turned off */
  108 #define DMAR_CTX_DISABLED       0x0008  /* Device is disabled, the
  109                                            ephemeral reference is kept
  110                                            to prevent context destruction */
  111 
  112 #define DMAR_CTX_PGLOCK(ctx)    VM_OBJECT_WLOCK((ctx)->pgtbl_obj)
  113 #define DMAR_CTX_PGTRYLOCK(ctx) VM_OBJECT_TRYWLOCK((ctx)->pgtbl_obj)
  114 #define DMAR_CTX_PGUNLOCK(ctx)  VM_OBJECT_WUNLOCK((ctx)->pgtbl_obj)
  115 #define DMAR_CTX_ASSERT_PGLOCKED(ctx) \
  116         VM_OBJECT_ASSERT_WLOCKED((ctx)->pgtbl_obj)
  117 
  118 #define DMAR_CTX_LOCK(ctx)      mtx_lock(&(ctx)->lock)
  119 #define DMAR_CTX_UNLOCK(ctx)    mtx_unlock(&(ctx)->lock)
  120 #define DMAR_CTX_ASSERT_LOCKED(ctx) mtx_assert(&(ctx)->lock, MA_OWNED)
  121 
  122 struct dmar_msi_data {
  123         int irq;
  124         int irq_rid;
  125         struct resource *irq_res;
  126         void *intr_handle;
  127         int (*handler)(void *);
  128         int msi_data_reg;
  129         int msi_addr_reg;
  130         int msi_uaddr_reg;
  131         void (*enable_intr)(struct dmar_unit *);
  132         void (*disable_intr)(struct dmar_unit *);
  133         const char *name;
  134 };
  135 
  136 #define DMAR_INTR_FAULT         0
  137 #define DMAR_INTR_QI            1
  138 #define DMAR_INTR_TOTAL         2
  139 
  140 struct dmar_unit {
  141         device_t dev;
  142         int unit;
  143         uint16_t segment;
  144         uint64_t base;
  145 
  146         /* Resources */
  147         int reg_rid;
  148         struct resource *regs;
  149 
  150         struct dmar_msi_data intrs[DMAR_INTR_TOTAL];
  151 
  152         /* Hardware registers cache */
  153         uint32_t hw_ver;
  154         uint64_t hw_cap;
  155         uint64_t hw_ecap;
  156         uint32_t hw_gcmd;
  157 
  158         /* Data for being a dmar */
  159         struct mtx lock;
  160         LIST_HEAD(, dmar_ctx) contexts;
  161         struct unrhdr *domids;
  162         vm_object_t ctx_obj;
  163         u_int barrier_flags;
  164 
  165         /* Fault handler data */
  166         struct mtx fault_lock;
  167         uint64_t *fault_log;
  168         int fault_log_head;
  169         int fault_log_tail;
  170         int fault_log_size;
  171         struct task fault_task;
  172         struct taskqueue *fault_taskqueue;
  173 
  174         /* QI */
  175         int qi_enabled;
  176         vm_offset_t inv_queue;
  177         vm_size_t inv_queue_size;
  178         uint32_t inv_queue_avail;
  179         uint32_t inv_queue_tail;
  180         volatile uint32_t inv_waitd_seq_hw; /* hw writes there on wait
  181                                                descr completion */
  182         uint64_t inv_waitd_seq_hw_phys;
  183         uint32_t inv_waitd_seq; /* next sequence number to use for wait descr */
  184         u_int inv_waitd_gen;    /* seq number generation AKA seq overflows */
  185         u_int inv_seq_waiters;  /* count of waiters for seq */
  186         u_int inv_queue_full;   /* informational counter */
  187 
  188         /* Delayed freeing of map entries queue processing */
  189         struct dmar_map_entries_tailq tlb_flush_entries;
  190         struct task qi_task;
  191         struct taskqueue *qi_taskqueue;
  192 
  193         /* Busdma delayed map load */
  194         struct task dmamap_load_task;
  195         TAILQ_HEAD(, bus_dmamap_dmar) delayed_maps;
  196         struct taskqueue *delayed_taskqueue;
  197 };
  198 
  199 #define DMAR_LOCK(dmar)         mtx_lock(&(dmar)->lock)
  200 #define DMAR_UNLOCK(dmar)       mtx_unlock(&(dmar)->lock)
  201 #define DMAR_ASSERT_LOCKED(dmar) mtx_assert(&(dmar)->lock, MA_OWNED)
  202 
  203 #define DMAR_FAULT_LOCK(dmar)   mtx_lock_spin(&(dmar)->fault_lock)
  204 #define DMAR_FAULT_UNLOCK(dmar) mtx_unlock_spin(&(dmar)->fault_lock)
  205 #define DMAR_FAULT_ASSERT_LOCKED(dmar) mtx_assert(&(dmar)->fault_lock, MA_OWNED)
  206 
  207 #define DMAR_IS_COHERENT(dmar)  (((dmar)->hw_ecap & DMAR_ECAP_C) != 0)
  208 #define DMAR_HAS_QI(dmar)       (((dmar)->hw_ecap & DMAR_ECAP_QI) != 0)
  209 
  210 /* Barrier ids */
  211 #define DMAR_BARRIER_RMRR       0
  212 #define DMAR_BARRIER_USEQ       1
  213 
  214 struct dmar_unit *dmar_find(device_t dev);
  215 
  216 u_int dmar_nd2mask(u_int nd);
  217 bool dmar_pglvl_supported(struct dmar_unit *unit, int pglvl);
  218 int ctx_set_agaw(struct dmar_ctx *ctx, int mgaw);
  219 int dmar_maxaddr2mgaw(struct dmar_unit* unit, dmar_gaddr_t maxaddr,
  220     bool allow_less);
  221 vm_pindex_t pglvl_max_pages(int pglvl);
  222 int ctx_is_sp_lvl(struct dmar_ctx *ctx, int lvl);
  223 dmar_gaddr_t pglvl_page_size(int total_pglvl, int lvl);
  224 dmar_gaddr_t ctx_page_size(struct dmar_ctx *ctx, int lvl);
  225 int calc_am(struct dmar_unit *unit, dmar_gaddr_t base, dmar_gaddr_t size,
  226     dmar_gaddr_t *isizep);
  227 struct vm_page *dmar_pgalloc(vm_object_t obj, vm_pindex_t idx, int flags);
  228 void dmar_pgfree(vm_object_t obj, vm_pindex_t idx, int flags);
  229 void *dmar_map_pgtbl(vm_object_t obj, vm_pindex_t idx, int flags,
  230     struct sf_buf **sf);
  231 void dmar_unmap_pgtbl(struct sf_buf *sf);
  232 int dmar_load_root_entry_ptr(struct dmar_unit *unit);
  233 int dmar_inv_ctx_glob(struct dmar_unit *unit);
  234 int dmar_inv_iotlb_glob(struct dmar_unit *unit);
  235 int dmar_flush_write_bufs(struct dmar_unit *unit);
  236 void dmar_flush_pte_to_ram(struct dmar_unit *unit, dmar_pte_t *dst);
  237 void dmar_flush_ctx_to_ram(struct dmar_unit *unit, dmar_ctx_entry_t *dst);
  238 void dmar_flush_root_to_ram(struct dmar_unit *unit, dmar_root_entry_t *dst);
  239 int dmar_enable_translation(struct dmar_unit *unit);
  240 int dmar_disable_translation(struct dmar_unit *unit);
  241 bool dmar_barrier_enter(struct dmar_unit *dmar, u_int barrier_id);
  242 void dmar_barrier_exit(struct dmar_unit *dmar, u_int barrier_id);
  243 
  244 int dmar_fault_intr(void *arg);
  245 void dmar_enable_fault_intr(struct dmar_unit *unit);
  246 void dmar_disable_fault_intr(struct dmar_unit *unit);
  247 int dmar_init_fault_log(struct dmar_unit *unit);
  248 void dmar_fini_fault_log(struct dmar_unit *unit);
  249 
  250 int dmar_qi_intr(void *arg);
  251 void dmar_enable_qi_intr(struct dmar_unit *unit);
  252 void dmar_disable_qi_intr(struct dmar_unit *unit);
  253 int dmar_init_qi(struct dmar_unit *unit);
  254 void dmar_fini_qi(struct dmar_unit *unit);
  255 void dmar_qi_invalidate_locked(struct dmar_ctx *ctx, dmar_gaddr_t start,
  256     dmar_gaddr_t size, struct dmar_qi_genseq *pseq);
  257 void dmar_qi_invalidate_ctx_glob_locked(struct dmar_unit *unit);
  258 void dmar_qi_invalidate_iotlb_glob_locked(struct dmar_unit *unit);
  259 
  260 vm_object_t ctx_get_idmap_pgtbl(struct dmar_ctx *ctx, dmar_gaddr_t maxaddr);
  261 void put_idmap_pgtbl(vm_object_t obj);
  262 int ctx_map_buf(struct dmar_ctx *ctx, dmar_gaddr_t base, dmar_gaddr_t size,
  263     vm_page_t *ma, uint64_t pflags, int flags);
  264 int ctx_unmap_buf(struct dmar_ctx *ctx, dmar_gaddr_t base, dmar_gaddr_t size,
  265     int flags);
  266 void ctx_flush_iotlb_sync(struct dmar_ctx *ctx, dmar_gaddr_t base,
  267     dmar_gaddr_t size);
  268 int ctx_alloc_pgtbl(struct dmar_ctx *ctx);
  269 void ctx_free_pgtbl(struct dmar_ctx *ctx);
  270 
  271 struct dmar_ctx *dmar_instantiate_ctx(struct dmar_unit *dmar, device_t dev,
  272     bool rmrr);
  273 struct dmar_ctx *dmar_get_ctx(struct dmar_unit *dmar, device_t dev, 
  274     uint16_t rid, bool id_mapped, bool rmrr_init);
  275 void dmar_free_ctx_locked(struct dmar_unit *dmar, struct dmar_ctx *ctx);
  276 void dmar_free_ctx(struct dmar_ctx *ctx);
  277 struct dmar_ctx *dmar_find_ctx_locked(struct dmar_unit *dmar, uint16_t rid);
  278 void dmar_ctx_unload_entry(struct dmar_map_entry *entry, bool free);
  279 void dmar_ctx_unload(struct dmar_ctx *ctx,
  280     struct dmar_map_entries_tailq *entries, bool cansleep);
  281 void dmar_ctx_free_entry(struct dmar_map_entry *entry, bool free);
  282 
  283 int dmar_init_busdma(struct dmar_unit *unit);
  284 void dmar_fini_busdma(struct dmar_unit *unit);
  285 
  286 void dmar_gas_init_ctx(struct dmar_ctx *ctx);
  287 void dmar_gas_fini_ctx(struct dmar_ctx *ctx);
  288 struct dmar_map_entry *dmar_gas_alloc_entry(struct dmar_ctx *ctx, u_int flags);
  289 void dmar_gas_free_entry(struct dmar_ctx *ctx, struct dmar_map_entry *entry);
  290 void dmar_gas_free_space(struct dmar_ctx *ctx, struct dmar_map_entry *entry);
  291 int dmar_gas_map(struct dmar_ctx *ctx, const struct bus_dma_tag_common *common,
  292     dmar_gaddr_t size, int offset, u_int eflags, u_int flags, vm_page_t *ma,
  293     struct dmar_map_entry **res);
  294 void dmar_gas_free_region(struct dmar_ctx *ctx, struct dmar_map_entry *entry);
  295 int dmar_gas_map_region(struct dmar_ctx *ctx, struct dmar_map_entry *entry,
  296     u_int eflags, u_int flags, vm_page_t *ma);
  297 int dmar_gas_reserve_region(struct dmar_ctx *ctx, dmar_gaddr_t start,
  298     dmar_gaddr_t end);
  299 
  300 void dmar_ctx_parse_rmrr(struct dmar_ctx *ctx, device_t dev,
  301     struct dmar_map_entries_tailq *rmrr_entries);
  302 int dmar_instantiate_rmrr_ctxs(struct dmar_unit *dmar);
  303 
  304 void dmar_quirks_post_ident(struct dmar_unit *dmar);
  305 void dmar_quirks_pre_use(struct dmar_unit *dmar);
  306 
  307 #define DMAR_GM_CANWAIT 0x0001
  308 #define DMAR_GM_CANSPLIT 0x0002
  309 
  310 #define DMAR_PGF_WAITOK 0x0001
  311 #define DMAR_PGF_ZERO   0x0002
  312 #define DMAR_PGF_ALLOC  0x0004
  313 #define DMAR_PGF_NOALLOC 0x0008
  314 #define DMAR_PGF_OBJL   0x0010
  315 
  316 extern dmar_haddr_t dmar_high;
  317 extern int haw;
  318 extern int dmar_tbl_pagecnt;
  319 extern int dmar_match_verbose;
  320 extern int dmar_check_free;
  321 
  322 static inline uint32_t
  323 dmar_read4(const struct dmar_unit *unit, int reg)
  324 {
  325 
  326         return (bus_read_4(unit->regs, reg));
  327 }
  328 
  329 static inline uint64_t
  330 dmar_read8(const struct dmar_unit *unit, int reg)
  331 {
  332 #ifdef __i386__
  333         uint32_t high, low;
  334 
  335         low = bus_read_4(unit->regs, reg);
  336         high = bus_read_4(unit->regs, reg + 4);
  337         return (low | ((uint64_t)high << 32));
  338 #else
  339         return (bus_read_8(unit->regs, reg));
  340 #endif
  341 }
  342 
  343 static inline void
  344 dmar_write4(const struct dmar_unit *unit, int reg, uint32_t val)
  345 {
  346 
  347         KASSERT(reg != DMAR_GCMD_REG || (val & DMAR_GCMD_TE) ==
  348             (unit->hw_gcmd & DMAR_GCMD_TE),
  349             ("dmar%d clearing TE 0x%08x 0x%08x", unit->unit,
  350             unit->hw_gcmd, val));
  351         bus_write_4(unit->regs, reg, val);
  352 }
  353 
  354 static inline void
  355 dmar_write8(const struct dmar_unit *unit, int reg, uint64_t val)
  356 {
  357 
  358         KASSERT(reg != DMAR_GCMD_REG, ("8byte GCMD write"));
  359 #ifdef __i386__
  360         uint32_t high, low;
  361 
  362         low = val;
  363         high = val >> 32;
  364         bus_write_4(unit->regs, reg, low);
  365         bus_write_4(unit->regs, reg + 4, high);
  366 #else
  367         bus_write_8(unit->regs, reg, val);
  368 #endif
  369 }
  370 
  371 /*
  372  * dmar_pte_store and dmar_pte_clear ensure that on i386, 32bit writes
  373  * are issued in the correct order.  For store, the lower word,
  374  * containing the P or R and W bits, is set only after the high word
  375  * is written.  For clear, the P bit is cleared first, then the high
  376  * word is cleared.
  377  */
  378 static inline void
  379 dmar_pte_store(volatile uint64_t *dst, uint64_t val)
  380 {
  381 
  382         KASSERT(*dst == 0, ("used pte %p oldval %jx newval %jx",
  383             dst, (uintmax_t)*dst, (uintmax_t)val));
  384 #ifdef __i386__
  385         volatile uint32_t *p;
  386         uint32_t hi, lo;
  387 
  388         hi = val >> 32;
  389         lo = val;
  390         p = (volatile uint32_t *)dst;
  391         *(p + 1) = hi;
  392         *p = lo;
  393 #else
  394         *dst = val;
  395 #endif
  396 }
  397 
  398 static inline void
  399 dmar_pte_clear(volatile uint64_t *dst)
  400 {
  401 #ifdef __i386__
  402         volatile uint32_t *p;
  403 
  404         p = (volatile uint32_t *)dst;
  405         *p = 0;
  406         *(p + 1) = 0;
  407 #else
  408         *dst = 0;
  409 #endif
  410 }
  411 
  412 static inline bool
  413 dmar_test_boundary(dmar_gaddr_t start, dmar_gaddr_t size,
  414     dmar_gaddr_t boundary)
  415 {
  416 
  417         if (boundary == 0)
  418                 return (true);
  419         return (start + size <= ((start + boundary) & ~(boundary - 1)));
  420 }
  421 
  422 #ifdef INVARIANTS
  423 #define TD_PREP_PINNED_ASSERT                                           \
  424         int old_td_pinned;                                              \
  425         old_td_pinned = curthread->td_pinned
  426 #define TD_PINNED_ASSERT                                                \
  427         KASSERT(curthread->td_pinned == old_td_pinned,                  \
  428             ("pin count leak: %d %d %s:%d", curthread->td_pinned,       \
  429             old_td_pinned, __FILE__, __LINE__))
  430 #else
  431 #define TD_PREP_PINNED_ASSERT
  432 #define TD_PINNED_ASSERT
  433 #endif
  434 
  435 #endif

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