The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/x86/iommu/intel_dmar.h

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2013-2015 The FreeBSD Foundation
    5  * All rights reserved.
    6  *
    7  * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
    8  * under sponsorship from the FreeBSD Foundation.
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  *
   19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   22  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   29  * SUCH DAMAGE.
   30  *
   31  * $FreeBSD: stable/12/sys/x86/iommu/intel_dmar.h 355384 2019-12-04 09:18:32Z kib $
   32  */
   33 
   34 #ifndef __X86_IOMMU_INTEL_DMAR_H
   35 #define __X86_IOMMU_INTEL_DMAR_H
   36 
   37 /* Host or physical memory address, after translation. */
   38 typedef uint64_t dmar_haddr_t;
   39 /* Guest or bus address, before translation. */
   40 typedef uint64_t dmar_gaddr_t;
   41 
   42 struct dmar_qi_genseq {
   43         u_int gen;
   44         uint32_t seq;
   45 };
   46 
   47 struct dmar_map_entry {
   48         dmar_gaddr_t start;
   49         dmar_gaddr_t end;
   50         dmar_gaddr_t free_after;        /* Free space after the entry */
   51         dmar_gaddr_t free_down;         /* Max free space below the
   52                                            current R/B tree node */
   53         u_int flags;
   54         TAILQ_ENTRY(dmar_map_entry) dmamap_link; /* Link for dmamap entries */
   55         RB_ENTRY(dmar_map_entry) rb_entry;       /* Links for domain entries */
   56         TAILQ_ENTRY(dmar_map_entry) unroll_link; /* Link for unroll after
   57                                                     dmamap_load failure */
   58         struct dmar_domain *domain;
   59         struct dmar_qi_genseq gseq;
   60 };
   61 
   62 RB_HEAD(dmar_gas_entries_tree, dmar_map_entry);
   63 RB_PROTOTYPE(dmar_gas_entries_tree, dmar_map_entry, rb_entry,
   64     dmar_gas_cmp_entries);
   65 
   66 #define DMAR_MAP_ENTRY_PLACE    0x0001  /* Fake entry */
   67 #define DMAR_MAP_ENTRY_RMRR     0x0002  /* Permanent, not linked by
   68                                            dmamap_link */
   69 #define DMAR_MAP_ENTRY_MAP      0x0004  /* Busdma created, linked by
   70                                            dmamap_link */
   71 #define DMAR_MAP_ENTRY_UNMAPPED 0x0010  /* No backing pages */
   72 #define DMAR_MAP_ENTRY_QI_NF    0x0020  /* qi task, do not free entry */
   73 #define DMAR_MAP_ENTRY_READ     0x1000  /* Read permitted */
   74 #define DMAR_MAP_ENTRY_WRITE    0x2000  /* Write permitted */
   75 #define DMAR_MAP_ENTRY_SNOOP    0x4000  /* Snoop */
   76 #define DMAR_MAP_ENTRY_TM       0x8000  /* Transient */
   77 
   78 /*
   79  * Locking annotations:
   80  * (u) - Protected by dmar unit lock
   81  * (d) - Protected by domain lock
   82  * (c) - Immutable after initialization
   83  */
   84 
   85 /*
   86  * The domain abstraction.  Most non-constant members of the domain
   87  * are protected by owning dmar unit lock, not by the domain lock.
   88  * Most important, the dmar lock protects the contexts list.
   89  *
   90  * The domain lock protects the address map for the domain, and list
   91  * of unload entries delayed.
   92  *
   93  * Page tables pages and pages content is protected by the vm object
   94  * lock pgtbl_obj, which contains the page tables pages.
   95  */
   96 struct dmar_domain {
   97         int domain;                     /* (c) DID, written in context entry */
   98         int mgaw;                       /* (c) Real max address width */
   99         int agaw;                       /* (c) Adjusted guest address width */
  100         int pglvl;                      /* (c) The pagelevel */
  101         int awlvl;                      /* (c) The pagelevel as the bitmask,
  102                                            to set in context entry */
  103         dmar_gaddr_t end;               /* (c) Highest address + 1 in
  104                                            the guest AS */
  105         u_int ctx_cnt;                  /* (u) Number of contexts owned */
  106         u_int refs;                     /* (u) Refs, including ctx */
  107         struct dmar_unit *dmar;         /* (c) */
  108         struct mtx lock;                /* (c) */
  109         LIST_ENTRY(dmar_domain) link;   /* (u) Member in the dmar list */
  110         LIST_HEAD(, dmar_ctx) contexts; /* (u) */
  111         vm_object_t pgtbl_obj;          /* (c) Page table pages */
  112         u_int flags;                    /* (u) */
  113         u_int entries_cnt;              /* (d) */
  114         struct dmar_gas_entries_tree rb_root; /* (d) */
  115         struct dmar_map_entries_tailq unload_entries; /* (d) Entries to
  116                                                          unload */
  117         struct dmar_map_entry *first_place, *last_place; /* (d) */
  118         struct task unload_task;        /* (c) */
  119         u_int batch_no;
  120 };
  121 
  122 struct dmar_ctx {
  123         struct bus_dma_tag_dmar ctx_tag; /* (c) Root tag */
  124         uint16_t rid;                   /* (c) pci RID */
  125         uint64_t last_fault_rec[2];     /* Last fault reported */
  126         struct dmar_domain *domain;     /* (c) */
  127         LIST_ENTRY(dmar_ctx) link;      /* (u) Member in the domain list */
  128         u_int refs;                     /* (u) References from tags */
  129         u_int flags;                    /* (u) */
  130         u_long loads;                   /* atomic updates, for stat only */
  131         u_long unloads;                 /* same */
  132 };
  133 
  134 #define DMAR_DOMAIN_GAS_INITED          0x0001
  135 #define DMAR_DOMAIN_PGTBL_INITED        0x0002
  136 #define DMAR_DOMAIN_IDMAP               0x0010  /* Domain uses identity
  137                                                    page table */
  138 #define DMAR_DOMAIN_RMRR                0x0020  /* Domain contains RMRR entry,
  139                                                    cannot be turned off */
  140 
  141 /* struct dmar_ctx flags */
  142 #define DMAR_CTX_FAULTED        0x0001  /* Fault was reported,
  143                                            last_fault_rec is valid */
  144 #define DMAR_CTX_DISABLED       0x0002  /* Device is disabled, the
  145                                            ephemeral reference is kept
  146                                            to prevent context destruction */
  147 
  148 #define DMAR_DOMAIN_PGLOCK(dom)         VM_OBJECT_WLOCK((dom)->pgtbl_obj)
  149 #define DMAR_DOMAIN_PGTRYLOCK(dom)      VM_OBJECT_TRYWLOCK((dom)->pgtbl_obj)
  150 #define DMAR_DOMAIN_PGUNLOCK(dom)       VM_OBJECT_WUNLOCK((dom)->pgtbl_obj)
  151 #define DMAR_DOMAIN_ASSERT_PGLOCKED(dom) \
  152         VM_OBJECT_ASSERT_WLOCKED((dom)->pgtbl_obj)
  153 
  154 #define DMAR_DOMAIN_LOCK(dom)   mtx_lock(&(dom)->lock)
  155 #define DMAR_DOMAIN_UNLOCK(dom) mtx_unlock(&(dom)->lock)
  156 #define DMAR_DOMAIN_ASSERT_LOCKED(dom) mtx_assert(&(dom)->lock, MA_OWNED)
  157 
  158 struct dmar_msi_data {
  159         int irq;
  160         int irq_rid;
  161         struct resource *irq_res;
  162         void *intr_handle;
  163         int (*handler)(void *);
  164         int msi_data_reg;
  165         int msi_addr_reg;
  166         int msi_uaddr_reg;
  167         void (*enable_intr)(struct dmar_unit *);
  168         void (*disable_intr)(struct dmar_unit *);
  169         const char *name;
  170 };
  171 
  172 #define DMAR_INTR_FAULT         0
  173 #define DMAR_INTR_QI            1
  174 #define DMAR_INTR_TOTAL         2
  175 
  176 struct dmar_unit {
  177         device_t dev;
  178         int unit;
  179         uint16_t segment;
  180         uint64_t base;
  181 
  182         /* Resources */
  183         int reg_rid;
  184         struct resource *regs;
  185 
  186         struct dmar_msi_data intrs[DMAR_INTR_TOTAL];
  187 
  188         /* Hardware registers cache */
  189         uint32_t hw_ver;
  190         uint64_t hw_cap;
  191         uint64_t hw_ecap;
  192         uint32_t hw_gcmd;
  193 
  194         /* Data for being a dmar */
  195         struct mtx lock;
  196         LIST_HEAD(, dmar_domain) domains;
  197         struct unrhdr *domids;
  198         vm_object_t ctx_obj;
  199         u_int barrier_flags;
  200 
  201         /* Fault handler data */
  202         struct mtx fault_lock;
  203         uint64_t *fault_log;
  204         int fault_log_head;
  205         int fault_log_tail;
  206         int fault_log_size;
  207         struct task fault_task;
  208         struct taskqueue *fault_taskqueue;
  209 
  210         /* QI */
  211         int qi_enabled;
  212         vm_offset_t inv_queue;
  213         vm_size_t inv_queue_size;
  214         uint32_t inv_queue_avail;
  215         uint32_t inv_queue_tail;
  216         volatile uint32_t inv_waitd_seq_hw; /* hw writes there on wait
  217                                                descr completion */
  218         uint64_t inv_waitd_seq_hw_phys;
  219         uint32_t inv_waitd_seq; /* next sequence number to use for wait descr */
  220         u_int inv_waitd_gen;    /* seq number generation AKA seq overflows */
  221         u_int inv_seq_waiters;  /* count of waiters for seq */
  222         u_int inv_queue_full;   /* informational counter */
  223 
  224         /* IR */
  225         int ir_enabled;
  226         vm_paddr_t irt_phys;
  227         dmar_irte_t *irt;
  228         u_int irte_cnt;
  229         vmem_t *irtids;
  230 
  231         /* Delayed freeing of map entries queue processing */
  232         struct dmar_map_entries_tailq tlb_flush_entries;
  233         struct task qi_task;
  234         struct taskqueue *qi_taskqueue;
  235 
  236         /* Busdma delayed map load */
  237         struct task dmamap_load_task;
  238         TAILQ_HEAD(, bus_dmamap_dmar) delayed_maps;
  239         struct taskqueue *delayed_taskqueue;
  240 
  241         int dma_enabled;
  242 
  243         /*
  244          * Bitmap of buses for which context must ignore slot:func,
  245          * duplicating the page table pointer into all context table
  246          * entries.  This is a client-controlled quirk to support some
  247          * NTBs.
  248          */
  249         uint32_t buswide_ctxs[(PCI_BUSMAX + 1) / NBBY / sizeof(uint32_t)];
  250 
  251 };
  252 
  253 #define DMAR_LOCK(dmar)         mtx_lock(&(dmar)->lock)
  254 #define DMAR_UNLOCK(dmar)       mtx_unlock(&(dmar)->lock)
  255 #define DMAR_ASSERT_LOCKED(dmar) mtx_assert(&(dmar)->lock, MA_OWNED)
  256 
  257 #define DMAR_FAULT_LOCK(dmar)   mtx_lock_spin(&(dmar)->fault_lock)
  258 #define DMAR_FAULT_UNLOCK(dmar) mtx_unlock_spin(&(dmar)->fault_lock)
  259 #define DMAR_FAULT_ASSERT_LOCKED(dmar) mtx_assert(&(dmar)->fault_lock, MA_OWNED)
  260 
  261 #define DMAR_IS_COHERENT(dmar)  (((dmar)->hw_ecap & DMAR_ECAP_C) != 0)
  262 #define DMAR_HAS_QI(dmar)       (((dmar)->hw_ecap & DMAR_ECAP_QI) != 0)
  263 #define DMAR_X2APIC(dmar) \
  264         (x2apic_mode && ((dmar)->hw_ecap & DMAR_ECAP_EIM) != 0)
  265 
  266 /* Barrier ids */
  267 #define DMAR_BARRIER_RMRR       0
  268 #define DMAR_BARRIER_USEQ       1
  269 
  270 struct dmar_unit *dmar_find(device_t dev, bool verbose);
  271 struct dmar_unit *dmar_find_hpet(device_t dev, uint16_t *rid);
  272 struct dmar_unit *dmar_find_ioapic(u_int apic_id, uint16_t *rid);
  273 
  274 u_int dmar_nd2mask(u_int nd);
  275 bool dmar_pglvl_supported(struct dmar_unit *unit, int pglvl);
  276 int domain_set_agaw(struct dmar_domain *domain, int mgaw);
  277 int dmar_maxaddr2mgaw(struct dmar_unit *unit, dmar_gaddr_t maxaddr,
  278     bool allow_less);
  279 vm_pindex_t pglvl_max_pages(int pglvl);
  280 int domain_is_sp_lvl(struct dmar_domain *domain, int lvl);
  281 dmar_gaddr_t pglvl_page_size(int total_pglvl, int lvl);
  282 dmar_gaddr_t domain_page_size(struct dmar_domain *domain, int lvl);
  283 int calc_am(struct dmar_unit *unit, dmar_gaddr_t base, dmar_gaddr_t size,
  284     dmar_gaddr_t *isizep);
  285 struct vm_page *dmar_pgalloc(vm_object_t obj, vm_pindex_t idx, int flags);
  286 void dmar_pgfree(vm_object_t obj, vm_pindex_t idx, int flags);
  287 void *dmar_map_pgtbl(vm_object_t obj, vm_pindex_t idx, int flags,
  288     struct sf_buf **sf);
  289 void dmar_unmap_pgtbl(struct sf_buf *sf);
  290 int dmar_load_root_entry_ptr(struct dmar_unit *unit);
  291 int dmar_inv_ctx_glob(struct dmar_unit *unit);
  292 int dmar_inv_iotlb_glob(struct dmar_unit *unit);
  293 int dmar_flush_write_bufs(struct dmar_unit *unit);
  294 void dmar_flush_pte_to_ram(struct dmar_unit *unit, dmar_pte_t *dst);
  295 void dmar_flush_ctx_to_ram(struct dmar_unit *unit, dmar_ctx_entry_t *dst);
  296 void dmar_flush_root_to_ram(struct dmar_unit *unit, dmar_root_entry_t *dst);
  297 int dmar_enable_translation(struct dmar_unit *unit);
  298 int dmar_disable_translation(struct dmar_unit *unit);
  299 int dmar_load_irt_ptr(struct dmar_unit *unit);
  300 int dmar_enable_ir(struct dmar_unit *unit);
  301 int dmar_disable_ir(struct dmar_unit *unit);
  302 bool dmar_barrier_enter(struct dmar_unit *dmar, u_int barrier_id);
  303 void dmar_barrier_exit(struct dmar_unit *dmar, u_int barrier_id);
  304 uint64_t dmar_get_timeout(void);
  305 void dmar_update_timeout(uint64_t newval);
  306 
  307 int dmar_fault_intr(void *arg);
  308 void dmar_enable_fault_intr(struct dmar_unit *unit);
  309 void dmar_disable_fault_intr(struct dmar_unit *unit);
  310 int dmar_init_fault_log(struct dmar_unit *unit);
  311 void dmar_fini_fault_log(struct dmar_unit *unit);
  312 
  313 int dmar_qi_intr(void *arg);
  314 void dmar_enable_qi_intr(struct dmar_unit *unit);
  315 void dmar_disable_qi_intr(struct dmar_unit *unit);
  316 int dmar_init_qi(struct dmar_unit *unit);
  317 void dmar_fini_qi(struct dmar_unit *unit);
  318 void dmar_qi_invalidate_locked(struct dmar_domain *domain, dmar_gaddr_t start,
  319     dmar_gaddr_t size, struct dmar_qi_genseq *psec, bool emit_wait);
  320 void dmar_qi_invalidate_ctx_glob_locked(struct dmar_unit *unit);
  321 void dmar_qi_invalidate_iotlb_glob_locked(struct dmar_unit *unit);
  322 void dmar_qi_invalidate_iec_glob(struct dmar_unit *unit);
  323 void dmar_qi_invalidate_iec(struct dmar_unit *unit, u_int start, u_int cnt);
  324 
  325 vm_object_t domain_get_idmap_pgtbl(struct dmar_domain *domain,
  326     dmar_gaddr_t maxaddr);
  327 void put_idmap_pgtbl(vm_object_t obj);
  328 int domain_map_buf(struct dmar_domain *domain, dmar_gaddr_t base,
  329     dmar_gaddr_t size, vm_page_t *ma, uint64_t pflags, int flags);
  330 int domain_unmap_buf(struct dmar_domain *domain, dmar_gaddr_t base,
  331     dmar_gaddr_t size, int flags);
  332 void domain_flush_iotlb_sync(struct dmar_domain *domain, dmar_gaddr_t base,
  333     dmar_gaddr_t size);
  334 int domain_alloc_pgtbl(struct dmar_domain *domain);
  335 void domain_free_pgtbl(struct dmar_domain *domain);
  336 
  337 int dmar_dev_depth(device_t child);
  338 void dmar_dev_path(device_t child, int *busno, void *path1, int depth);
  339 
  340 struct dmar_ctx *dmar_instantiate_ctx(struct dmar_unit *dmar, device_t dev,
  341     bool rmrr);
  342 struct dmar_ctx *dmar_get_ctx_for_dev(struct dmar_unit *dmar, device_t dev,
  343     uint16_t rid, bool id_mapped, bool rmrr_init);
  344 struct dmar_ctx *dmar_get_ctx_for_devpath(struct dmar_unit *dmar, uint16_t rid,
  345     int dev_domain, int dev_busno, const void *dev_path, int dev_path_len,
  346     bool id_mapped, bool rmrr_init);
  347 int dmar_move_ctx_to_domain(struct dmar_domain *domain, struct dmar_ctx *ctx);
  348 void dmar_free_ctx_locked(struct dmar_unit *dmar, struct dmar_ctx *ctx);
  349 void dmar_free_ctx(struct dmar_ctx *ctx);
  350 struct dmar_ctx *dmar_find_ctx_locked(struct dmar_unit *dmar, uint16_t rid);
  351 void dmar_domain_unload_entry(struct dmar_map_entry *entry, bool free);
  352 void dmar_domain_unload(struct dmar_domain *domain,
  353     struct dmar_map_entries_tailq *entries, bool cansleep);
  354 void dmar_domain_free_entry(struct dmar_map_entry *entry, bool free);
  355 
  356 int dmar_init_busdma(struct dmar_unit *unit);
  357 void dmar_fini_busdma(struct dmar_unit *unit);
  358 device_t dmar_get_requester(device_t dev, uint16_t *rid);
  359 
  360 void dmar_gas_init_domain(struct dmar_domain *domain);
  361 void dmar_gas_fini_domain(struct dmar_domain *domain);
  362 struct dmar_map_entry *dmar_gas_alloc_entry(struct dmar_domain *domain,
  363     u_int flags);
  364 void dmar_gas_free_entry(struct dmar_domain *domain,
  365     struct dmar_map_entry *entry);
  366 void dmar_gas_free_space(struct dmar_domain *domain,
  367     struct dmar_map_entry *entry);
  368 int dmar_gas_map(struct dmar_domain *domain,
  369     const struct bus_dma_tag_common *common, dmar_gaddr_t size, int offset,
  370     u_int eflags, u_int flags, vm_page_t *ma, struct dmar_map_entry **res);
  371 void dmar_gas_free_region(struct dmar_domain *domain,
  372     struct dmar_map_entry *entry);
  373 int dmar_gas_map_region(struct dmar_domain *domain,
  374     struct dmar_map_entry *entry, u_int eflags, u_int flags, vm_page_t *ma);
  375 int dmar_gas_reserve_region(struct dmar_domain *domain, dmar_gaddr_t start,
  376     dmar_gaddr_t end);
  377 
  378 void dmar_dev_parse_rmrr(struct dmar_domain *domain, int dev_domain,
  379     int dev_busno, const void *dev_path, int dev_path_len,
  380     struct dmar_map_entries_tailq *rmrr_entries);
  381 int dmar_instantiate_rmrr_ctxs(struct dmar_unit *dmar);
  382 
  383 void dmar_quirks_post_ident(struct dmar_unit *dmar);
  384 void dmar_quirks_pre_use(struct dmar_unit *dmar);
  385 
  386 int dmar_init_irt(struct dmar_unit *unit);
  387 void dmar_fini_irt(struct dmar_unit *unit);
  388 
  389 void dmar_set_buswide_ctx(struct dmar_unit *unit, u_int busno);
  390 bool dmar_is_buswide_ctx(struct dmar_unit *unit, u_int busno);
  391 
  392 #define DMAR_GM_CANWAIT 0x0001
  393 #define DMAR_GM_CANSPLIT 0x0002
  394 #define DMAR_GM_RMRR    0x0004
  395 
  396 #define DMAR_PGF_WAITOK 0x0001
  397 #define DMAR_PGF_ZERO   0x0002
  398 #define DMAR_PGF_ALLOC  0x0004
  399 #define DMAR_PGF_NOALLOC 0x0008
  400 #define DMAR_PGF_OBJL   0x0010
  401 
  402 extern dmar_haddr_t dmar_high;
  403 extern int haw;
  404 extern int dmar_tbl_pagecnt;
  405 extern int dmar_batch_coalesce;
  406 extern int dmar_check_free;
  407 
  408 static inline uint32_t
  409 dmar_read4(const struct dmar_unit *unit, int reg)
  410 {
  411 
  412         return (bus_read_4(unit->regs, reg));
  413 }
  414 
  415 static inline uint64_t
  416 dmar_read8(const struct dmar_unit *unit, int reg)
  417 {
  418 #ifdef __i386__
  419         uint32_t high, low;
  420 
  421         low = bus_read_4(unit->regs, reg);
  422         high = bus_read_4(unit->regs, reg + 4);
  423         return (low | ((uint64_t)high << 32));
  424 #else
  425         return (bus_read_8(unit->regs, reg));
  426 #endif
  427 }
  428 
  429 static inline void
  430 dmar_write4(const struct dmar_unit *unit, int reg, uint32_t val)
  431 {
  432 
  433         KASSERT(reg != DMAR_GCMD_REG || (val & DMAR_GCMD_TE) ==
  434             (unit->hw_gcmd & DMAR_GCMD_TE),
  435             ("dmar%d clearing TE 0x%08x 0x%08x", unit->unit,
  436             unit->hw_gcmd, val));
  437         bus_write_4(unit->regs, reg, val);
  438 }
  439 
  440 static inline void
  441 dmar_write8(const struct dmar_unit *unit, int reg, uint64_t val)
  442 {
  443 
  444         KASSERT(reg != DMAR_GCMD_REG, ("8byte GCMD write"));
  445 #ifdef __i386__
  446         uint32_t high, low;
  447 
  448         low = val;
  449         high = val >> 32;
  450         bus_write_4(unit->regs, reg, low);
  451         bus_write_4(unit->regs, reg + 4, high);
  452 #else
  453         bus_write_8(unit->regs, reg, val);
  454 #endif
  455 }
  456 
  457 /*
  458  * dmar_pte_store and dmar_pte_clear ensure that on i386, 32bit writes
  459  * are issued in the correct order.  For store, the lower word,
  460  * containing the P or R and W bits, is set only after the high word
  461  * is written.  For clear, the P bit is cleared first, then the high
  462  * word is cleared.
  463  *
  464  * dmar_pte_update updates the pte.  For amd64, the update is atomic.
  465  * For i386, it first disables the entry by clearing the word
  466  * containing the P bit, and then defer to dmar_pte_store.  The locked
  467  * cmpxchg8b is probably available on any machine having DMAR support,
  468  * but interrupt translation table may be mapped uncached.
  469  */
  470 static inline void
  471 dmar_pte_store1(volatile uint64_t *dst, uint64_t val)
  472 {
  473 #ifdef __i386__
  474         volatile uint32_t *p;
  475         uint32_t hi, lo;
  476 
  477         hi = val >> 32;
  478         lo = val;
  479         p = (volatile uint32_t *)dst;
  480         *(p + 1) = hi;
  481         *p = lo;
  482 #else
  483         *dst = val;
  484 #endif
  485 }
  486 
  487 static inline void
  488 dmar_pte_store(volatile uint64_t *dst, uint64_t val)
  489 {
  490 
  491         KASSERT(*dst == 0, ("used pte %p oldval %jx newval %jx",
  492             dst, (uintmax_t)*dst, (uintmax_t)val));
  493         dmar_pte_store1(dst, val);
  494 }
  495 
  496 static inline void
  497 dmar_pte_update(volatile uint64_t *dst, uint64_t val)
  498 {
  499 
  500 #ifdef __i386__
  501         volatile uint32_t *p;
  502 
  503         p = (volatile uint32_t *)dst;
  504         *p = 0;
  505 #endif
  506         dmar_pte_store1(dst, val);
  507 }
  508 
  509 static inline void
  510 dmar_pte_clear(volatile uint64_t *dst)
  511 {
  512 #ifdef __i386__
  513         volatile uint32_t *p;
  514 
  515         p = (volatile uint32_t *)dst;
  516         *p = 0;
  517         *(p + 1) = 0;
  518 #else
  519         *dst = 0;
  520 #endif
  521 }
  522 
  523 static inline bool
  524 dmar_test_boundary(dmar_gaddr_t start, dmar_gaddr_t size,
  525     dmar_gaddr_t boundary)
  526 {
  527 
  528         if (boundary == 0)
  529                 return (true);
  530         return (start + size <= ((start + boundary) & ~(boundary - 1)));
  531 }
  532 
  533 extern struct timespec dmar_hw_timeout;
  534 
  535 #define DMAR_WAIT_UNTIL(cond)                                   \
  536 {                                                               \
  537         struct timespec last, curr;                             \
  538         bool forever;                                           \
  539                                                                 \
  540         if (dmar_hw_timeout.tv_sec == 0 &&                      \
  541             dmar_hw_timeout.tv_nsec == 0) {                     \
  542                 forever = true;                                 \
  543         } else {                                                \
  544                 forever = false;                                \
  545                 nanouptime(&curr);                              \
  546                 timespecadd(&curr, &dmar_hw_timeout, &last);    \
  547         }                                                       \
  548         for (;;) {                                              \
  549                 if (cond) {                                     \
  550                         error = 0;                              \
  551                         break;                                  \
  552                 }                                               \
  553                 nanouptime(&curr);                              \
  554                 if (!forever && timespeccmp(&last, &curr, <)) { \
  555                         error = ETIMEDOUT;                      \
  556                         break;                                  \
  557                 }                                               \
  558                 cpu_spinwait();                                 \
  559         }                                                       \
  560 }
  561 
  562 #ifdef INVARIANTS
  563 #define TD_PREP_PINNED_ASSERT                                           \
  564         int old_td_pinned;                                              \
  565         old_td_pinned = curthread->td_pinned
  566 #define TD_PINNED_ASSERT                                                \
  567         KASSERT(curthread->td_pinned == old_td_pinned,                  \
  568             ("pin count leak: %d %d %s:%d", curthread->td_pinned,       \
  569             old_td_pinned, __FILE__, __LINE__))
  570 #else
  571 #define TD_PREP_PINNED_ASSERT
  572 #define TD_PINNED_ASSERT
  573 #endif
  574 
  575 #endif

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