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sys/x86/iommu/intel_drv.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013-2015 The FreeBSD Foundation 5 * 6 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 7 * under sponsorship from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include "opt_acpi.h" 35 #if defined(__amd64__) 36 #define DEV_APIC 37 #else 38 #include "opt_apic.h" 39 #endif 40 #include "opt_ddb.h" 41 42 #include <sys/param.h> 43 #include <sys/bus.h> 44 #include <sys/kernel.h> 45 #include <sys/lock.h> 46 #include <sys/malloc.h> 47 #include <sys/memdesc.h> 48 #include <sys/module.h> 49 #include <sys/mutex.h> 50 #include <sys/rman.h> 51 #include <sys/rwlock.h> 52 #include <sys/smp.h> 53 #include <sys/taskqueue.h> 54 #include <sys/tree.h> 55 #include <sys/vmem.h> 56 #include <vm/vm.h> 57 #include <vm/vm_extern.h> 58 #include <vm/vm_kern.h> 59 #include <vm/vm_object.h> 60 #include <vm/vm_page.h> 61 #include <vm/vm_pager.h> 62 #include <vm/vm_map.h> 63 #include <contrib/dev/acpica/include/acpi.h> 64 #include <contrib/dev/acpica/include/accommon.h> 65 #include <dev/acpica/acpivar.h> 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 #include <machine/bus.h> 69 #include <machine/pci_cfgreg.h> 70 #include <x86/include/busdma_impl.h> 71 #include <dev/iommu/busdma_iommu.h> 72 #include <x86/iommu/intel_reg.h> 73 #include <x86/iommu/intel_dmar.h> 74 75 #ifdef DEV_APIC 76 #include "pcib_if.h" 77 #include <machine/intr_machdep.h> 78 #include <x86/apicreg.h> 79 #include <x86/apicvar.h> 80 #endif 81 82 #define DMAR_FAULT_IRQ_RID 0 83 #define DMAR_QI_IRQ_RID 1 84 #define DMAR_REG_RID 2 85 86 static device_t *dmar_devs; 87 static int dmar_devcnt; 88 89 typedef int (*dmar_iter_t)(ACPI_DMAR_HEADER *, void *); 90 91 static void 92 dmar_iterate_tbl(dmar_iter_t iter, void *arg) 93 { 94 ACPI_TABLE_DMAR *dmartbl; 95 ACPI_DMAR_HEADER *dmarh; 96 char *ptr, *ptrend; 97 ACPI_STATUS status; 98 99 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl); 100 if (ACPI_FAILURE(status)) 101 return; 102 ptr = (char *)dmartbl + sizeof(*dmartbl); 103 ptrend = (char *)dmartbl + dmartbl->Header.Length; 104 for (;;) { 105 if (ptr >= ptrend) 106 break; 107 dmarh = (ACPI_DMAR_HEADER *)ptr; 108 if (dmarh->Length <= 0) { 109 printf("dmar_identify: corrupted DMAR table, l %d\n", 110 dmarh->Length); 111 break; 112 } 113 ptr += dmarh->Length; 114 if (!iter(dmarh, arg)) 115 break; 116 } 117 AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl); 118 } 119 120 struct find_iter_args { 121 int i; 122 ACPI_DMAR_HARDWARE_UNIT *res; 123 }; 124 125 static int 126 dmar_find_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 127 { 128 struct find_iter_args *fia; 129 130 if (dmarh->Type != ACPI_DMAR_TYPE_HARDWARE_UNIT) 131 return (1); 132 133 fia = arg; 134 if (fia->i == 0) { 135 fia->res = (ACPI_DMAR_HARDWARE_UNIT *)dmarh; 136 return (0); 137 } 138 fia->i--; 139 return (1); 140 } 141 142 static ACPI_DMAR_HARDWARE_UNIT * 143 dmar_find_by_index(int idx) 144 { 145 struct find_iter_args fia; 146 147 fia.i = idx; 148 fia.res = NULL; 149 dmar_iterate_tbl(dmar_find_iter, &fia); 150 return (fia.res); 151 } 152 153 static int 154 dmar_count_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 155 { 156 157 if (dmarh->Type == ACPI_DMAR_TYPE_HARDWARE_UNIT) 158 dmar_devcnt++; 159 return (1); 160 } 161 162 static int dmar_enable = 0; 163 static void 164 dmar_identify(driver_t *driver, device_t parent) 165 { 166 ACPI_TABLE_DMAR *dmartbl; 167 ACPI_DMAR_HARDWARE_UNIT *dmarh; 168 ACPI_STATUS status; 169 int i, error; 170 171 if (acpi_disabled("dmar")) 172 return; 173 TUNABLE_INT_FETCH("hw.dmar.enable", &dmar_enable); 174 if (!dmar_enable) 175 return; 176 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl); 177 if (ACPI_FAILURE(status)) 178 return; 179 haw = dmartbl->Width + 1; 180 if ((1ULL << (haw + 1)) > BUS_SPACE_MAXADDR) 181 dmar_high = BUS_SPACE_MAXADDR; 182 else 183 dmar_high = 1ULL << (haw + 1); 184 if (bootverbose) { 185 printf("DMAR HAW=%d flags=<%b>\n", dmartbl->Width, 186 (unsigned)dmartbl->Flags, 187 "\020\001INTR_REMAP\002X2APIC_OPT_OUT"); 188 } 189 AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl); 190 191 dmar_iterate_tbl(dmar_count_iter, NULL); 192 if (dmar_devcnt == 0) 193 return; 194 dmar_devs = malloc(sizeof(device_t) * dmar_devcnt, M_DEVBUF, 195 M_WAITOK | M_ZERO); 196 for (i = 0; i < dmar_devcnt; i++) { 197 dmarh = dmar_find_by_index(i); 198 if (dmarh == NULL) { 199 printf("dmar_identify: cannot find HWUNIT %d\n", i); 200 continue; 201 } 202 dmar_devs[i] = BUS_ADD_CHILD(parent, 1, "dmar", i); 203 if (dmar_devs[i] == NULL) { 204 printf("dmar_identify: cannot create instance %d\n", i); 205 continue; 206 } 207 error = bus_set_resource(dmar_devs[i], SYS_RES_MEMORY, 208 DMAR_REG_RID, dmarh->Address, PAGE_SIZE); 209 if (error != 0) { 210 printf( 211 "dmar%d: unable to alloc register window at 0x%08jx: error %d\n", 212 i, (uintmax_t)dmarh->Address, error); 213 device_delete_child(parent, dmar_devs[i]); 214 dmar_devs[i] = NULL; 215 } 216 } 217 } 218 219 static int 220 dmar_probe(device_t dev) 221 { 222 223 if (acpi_get_handle(dev) != NULL) 224 return (ENXIO); 225 device_set_desc(dev, "DMA remap"); 226 return (BUS_PROBE_NOWILDCARD); 227 } 228 229 static void 230 dmar_release_intr(device_t dev, struct dmar_unit *unit, int idx) 231 { 232 struct dmar_msi_data *dmd; 233 234 dmd = &unit->intrs[idx]; 235 if (dmd->irq == -1) 236 return; 237 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle); 238 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res); 239 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid); 240 PCIB_RELEASE_MSIX(device_get_parent(device_get_parent(dev)), 241 dev, dmd->irq); 242 dmd->irq = -1; 243 } 244 245 static void 246 dmar_release_resources(device_t dev, struct dmar_unit *unit) 247 { 248 int i; 249 250 iommu_fini_busdma(&unit->iommu); 251 dmar_fini_irt(unit); 252 dmar_fini_qi(unit); 253 dmar_fini_fault_log(unit); 254 for (i = 0; i < DMAR_INTR_TOTAL; i++) 255 dmar_release_intr(dev, unit, i); 256 if (unit->regs != NULL) { 257 bus_deactivate_resource(dev, SYS_RES_MEMORY, unit->reg_rid, 258 unit->regs); 259 bus_release_resource(dev, SYS_RES_MEMORY, unit->reg_rid, 260 unit->regs); 261 unit->regs = NULL; 262 } 263 if (unit->domids != NULL) { 264 delete_unrhdr(unit->domids); 265 unit->domids = NULL; 266 } 267 if (unit->ctx_obj != NULL) { 268 vm_object_deallocate(unit->ctx_obj); 269 unit->ctx_obj = NULL; 270 } 271 } 272 273 static int 274 dmar_alloc_irq(device_t dev, struct dmar_unit *unit, int idx) 275 { 276 device_t pcib; 277 struct dmar_msi_data *dmd; 278 uint64_t msi_addr; 279 uint32_t msi_data; 280 int error; 281 282 dmd = &unit->intrs[idx]; 283 pcib = device_get_parent(device_get_parent(dev)); /* Really not pcib */ 284 error = PCIB_ALLOC_MSIX(pcib, dev, &dmd->irq); 285 if (error != 0) { 286 device_printf(dev, "cannot allocate %s interrupt, %d\n", 287 dmd->name, error); 288 goto err1; 289 } 290 error = bus_set_resource(dev, SYS_RES_IRQ, dmd->irq_rid, 291 dmd->irq, 1); 292 if (error != 0) { 293 device_printf(dev, "cannot set %s interrupt resource, %d\n", 294 dmd->name, error); 295 goto err2; 296 } 297 dmd->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 298 &dmd->irq_rid, RF_ACTIVE); 299 if (dmd->irq_res == NULL) { 300 device_printf(dev, 301 "cannot allocate resource for %s interrupt\n", dmd->name); 302 error = ENXIO; 303 goto err3; 304 } 305 error = bus_setup_intr(dev, dmd->irq_res, INTR_TYPE_MISC, 306 dmd->handler, NULL, unit, &dmd->intr_handle); 307 if (error != 0) { 308 device_printf(dev, "cannot setup %s interrupt, %d\n", 309 dmd->name, error); 310 goto err4; 311 } 312 bus_describe_intr(dev, dmd->irq_res, dmd->intr_handle, "%s", dmd->name); 313 error = PCIB_MAP_MSI(pcib, dev, dmd->irq, &msi_addr, &msi_data); 314 if (error != 0) { 315 device_printf(dev, "cannot map %s interrupt, %d\n", 316 dmd->name, error); 317 goto err5; 318 } 319 dmar_write4(unit, dmd->msi_data_reg, msi_data); 320 dmar_write4(unit, dmd->msi_addr_reg, msi_addr); 321 /* Only for xAPIC mode */ 322 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32); 323 return (0); 324 325 err5: 326 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle); 327 err4: 328 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res); 329 err3: 330 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid); 331 err2: 332 PCIB_RELEASE_MSIX(pcib, dev, dmd->irq); 333 dmd->irq = -1; 334 err1: 335 return (error); 336 } 337 338 #ifdef DEV_APIC 339 static int 340 dmar_remap_intr(device_t dev, device_t child, u_int irq) 341 { 342 struct dmar_unit *unit; 343 struct dmar_msi_data *dmd; 344 uint64_t msi_addr; 345 uint32_t msi_data; 346 int i, error; 347 348 unit = device_get_softc(dev); 349 for (i = 0; i < DMAR_INTR_TOTAL; i++) { 350 dmd = &unit->intrs[i]; 351 if (irq == dmd->irq) { 352 error = PCIB_MAP_MSI(device_get_parent( 353 device_get_parent(dev)), 354 dev, irq, &msi_addr, &msi_data); 355 if (error != 0) 356 return (error); 357 DMAR_LOCK(unit); 358 (dmd->disable_intr)(unit); 359 dmar_write4(unit, dmd->msi_data_reg, msi_data); 360 dmar_write4(unit, dmd->msi_addr_reg, msi_addr); 361 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32); 362 (dmd->enable_intr)(unit); 363 DMAR_UNLOCK(unit); 364 return (0); 365 } 366 } 367 return (ENOENT); 368 } 369 #endif 370 371 static void 372 dmar_print_caps(device_t dev, struct dmar_unit *unit, 373 ACPI_DMAR_HARDWARE_UNIT *dmaru) 374 { 375 uint32_t caphi, ecaphi; 376 377 device_printf(dev, "regs@0x%08jx, ver=%d.%d, seg=%d, flags=<%b>\n", 378 (uintmax_t)dmaru->Address, DMAR_MAJOR_VER(unit->hw_ver), 379 DMAR_MINOR_VER(unit->hw_ver), dmaru->Segment, 380 dmaru->Flags, "\020\001INCLUDE_ALL_PCI"); 381 caphi = unit->hw_cap >> 32; 382 device_printf(dev, "cap=%b,", (u_int)unit->hw_cap, 383 "\020\004AFL\005WBF\006PLMR\007PHMR\010CM\027ZLR\030ISOCH"); 384 printf("%b, ", caphi, "\020\010PSI\027DWD\030DRD\031FL1GP\034PSI"); 385 printf("ndoms=%d, sagaw=%d, mgaw=%d, fro=%d, nfr=%d, superp=%d", 386 DMAR_CAP_ND(unit->hw_cap), DMAR_CAP_SAGAW(unit->hw_cap), 387 DMAR_CAP_MGAW(unit->hw_cap), DMAR_CAP_FRO(unit->hw_cap), 388 DMAR_CAP_NFR(unit->hw_cap), DMAR_CAP_SPS(unit->hw_cap)); 389 if ((unit->hw_cap & DMAR_CAP_PSI) != 0) 390 printf(", mamv=%d", DMAR_CAP_MAMV(unit->hw_cap)); 391 printf("\n"); 392 ecaphi = unit->hw_ecap >> 32; 393 device_printf(dev, "ecap=%b,", (u_int)unit->hw_ecap, 394 "\020\001C\002QI\003DI\004IR\005EIM\007PT\010SC\031ECS\032MTS" 395 "\033NEST\034DIS\035PASID\036PRS\037ERS\040SRS"); 396 printf("%b, ", ecaphi, "\020\002NWFS\003EAFS"); 397 printf("mhmw=%d, iro=%d\n", DMAR_ECAP_MHMV(unit->hw_ecap), 398 DMAR_ECAP_IRO(unit->hw_ecap)); 399 } 400 401 static int 402 dmar_attach(device_t dev) 403 { 404 struct dmar_unit *unit; 405 ACPI_DMAR_HARDWARE_UNIT *dmaru; 406 uint64_t timeout; 407 int disable_pmr; 408 int i, error; 409 410 unit = device_get_softc(dev); 411 unit->dev = dev; 412 unit->iommu.unit = device_get_unit(dev); 413 unit->iommu.dev = dev; 414 dmaru = dmar_find_by_index(unit->iommu.unit); 415 if (dmaru == NULL) 416 return (EINVAL); 417 unit->segment = dmaru->Segment; 418 unit->base = dmaru->Address; 419 unit->reg_rid = DMAR_REG_RID; 420 unit->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 421 &unit->reg_rid, RF_ACTIVE); 422 if (unit->regs == NULL) { 423 device_printf(dev, "cannot allocate register window\n"); 424 return (ENOMEM); 425 } 426 unit->hw_ver = dmar_read4(unit, DMAR_VER_REG); 427 unit->hw_cap = dmar_read8(unit, DMAR_CAP_REG); 428 unit->hw_ecap = dmar_read8(unit, DMAR_ECAP_REG); 429 if (bootverbose) 430 dmar_print_caps(dev, unit, dmaru); 431 dmar_quirks_post_ident(unit); 432 433 timeout = dmar_get_timeout(); 434 TUNABLE_UINT64_FETCH("hw.dmar.timeout", &timeout); 435 dmar_update_timeout(timeout); 436 437 for (i = 0; i < DMAR_INTR_TOTAL; i++) 438 unit->intrs[i].irq = -1; 439 440 unit->intrs[DMAR_INTR_FAULT].name = "fault"; 441 unit->intrs[DMAR_INTR_FAULT].irq_rid = DMAR_FAULT_IRQ_RID; 442 unit->intrs[DMAR_INTR_FAULT].handler = dmar_fault_intr; 443 unit->intrs[DMAR_INTR_FAULT].msi_data_reg = DMAR_FEDATA_REG; 444 unit->intrs[DMAR_INTR_FAULT].msi_addr_reg = DMAR_FEADDR_REG; 445 unit->intrs[DMAR_INTR_FAULT].msi_uaddr_reg = DMAR_FEUADDR_REG; 446 unit->intrs[DMAR_INTR_FAULT].enable_intr = dmar_enable_fault_intr; 447 unit->intrs[DMAR_INTR_FAULT].disable_intr = dmar_disable_fault_intr; 448 error = dmar_alloc_irq(dev, unit, DMAR_INTR_FAULT); 449 if (error != 0) { 450 dmar_release_resources(dev, unit); 451 return (error); 452 } 453 if (DMAR_HAS_QI(unit)) { 454 unit->intrs[DMAR_INTR_QI].name = "qi"; 455 unit->intrs[DMAR_INTR_QI].irq_rid = DMAR_QI_IRQ_RID; 456 unit->intrs[DMAR_INTR_QI].handler = dmar_qi_intr; 457 unit->intrs[DMAR_INTR_QI].msi_data_reg = DMAR_IEDATA_REG; 458 unit->intrs[DMAR_INTR_QI].msi_addr_reg = DMAR_IEADDR_REG; 459 unit->intrs[DMAR_INTR_QI].msi_uaddr_reg = DMAR_IEUADDR_REG; 460 unit->intrs[DMAR_INTR_QI].enable_intr = dmar_enable_qi_intr; 461 unit->intrs[DMAR_INTR_QI].disable_intr = dmar_disable_qi_intr; 462 error = dmar_alloc_irq(dev, unit, DMAR_INTR_QI); 463 if (error != 0) { 464 dmar_release_resources(dev, unit); 465 return (error); 466 } 467 } 468 469 mtx_init(&unit->iommu.lock, "dmarhw", NULL, MTX_DEF); 470 unit->domids = new_unrhdr(0, dmar_nd2mask(DMAR_CAP_ND(unit->hw_cap)), 471 &unit->iommu.lock); 472 LIST_INIT(&unit->domains); 473 474 /* 475 * 9.2 "Context Entry": 476 * When Caching Mode (CM) field is reported as Set, the 477 * domain-id value of zero is architecturally reserved. 478 * Software must not use domain-id value of zero 479 * when CM is Set. 480 */ 481 if ((unit->hw_cap & DMAR_CAP_CM) != 0) 482 alloc_unr_specific(unit->domids, 0); 483 484 unit->ctx_obj = vm_pager_allocate(OBJT_PHYS, NULL, IDX_TO_OFF(1 + 485 DMAR_CTX_CNT), 0, 0, NULL); 486 487 /* 488 * Allocate and load the root entry table pointer. Enable the 489 * address translation after the required invalidations are 490 * done. 491 */ 492 dmar_pgalloc(unit->ctx_obj, 0, IOMMU_PGF_WAITOK | IOMMU_PGF_ZERO); 493 DMAR_LOCK(unit); 494 error = dmar_load_root_entry_ptr(unit); 495 if (error != 0) { 496 DMAR_UNLOCK(unit); 497 dmar_release_resources(dev, unit); 498 return (error); 499 } 500 error = dmar_inv_ctx_glob(unit); 501 if (error != 0) { 502 DMAR_UNLOCK(unit); 503 dmar_release_resources(dev, unit); 504 return (error); 505 } 506 if ((unit->hw_ecap & DMAR_ECAP_DI) != 0) { 507 error = dmar_inv_iotlb_glob(unit); 508 if (error != 0) { 509 DMAR_UNLOCK(unit); 510 dmar_release_resources(dev, unit); 511 return (error); 512 } 513 } 514 515 DMAR_UNLOCK(unit); 516 error = dmar_init_fault_log(unit); 517 if (error != 0) { 518 dmar_release_resources(dev, unit); 519 return (error); 520 } 521 error = dmar_init_qi(unit); 522 if (error != 0) { 523 dmar_release_resources(dev, unit); 524 return (error); 525 } 526 error = dmar_init_irt(unit); 527 if (error != 0) { 528 dmar_release_resources(dev, unit); 529 return (error); 530 } 531 532 disable_pmr = 0; 533 TUNABLE_INT_FETCH("hw.dmar.pmr.disable", &disable_pmr); 534 if (disable_pmr) { 535 error = dmar_disable_protected_regions(unit); 536 if (error != 0) 537 device_printf(dev, 538 "Failed to disable protected regions\n"); 539 } 540 541 error = iommu_init_busdma(&unit->iommu); 542 if (error != 0) { 543 dmar_release_resources(dev, unit); 544 return (error); 545 } 546 547 #ifdef NOTYET 548 DMAR_LOCK(unit); 549 error = dmar_enable_translation(unit); 550 if (error != 0) { 551 DMAR_UNLOCK(unit); 552 dmar_release_resources(dev, unit); 553 return (error); 554 } 555 DMAR_UNLOCK(unit); 556 #endif 557 558 return (0); 559 } 560 561 static int 562 dmar_detach(device_t dev) 563 { 564 565 return (EBUSY); 566 } 567 568 static int 569 dmar_suspend(device_t dev) 570 { 571 572 return (0); 573 } 574 575 static int 576 dmar_resume(device_t dev) 577 { 578 579 /* XXXKIB */ 580 return (0); 581 } 582 583 static device_method_t dmar_methods[] = { 584 DEVMETHOD(device_identify, dmar_identify), 585 DEVMETHOD(device_probe, dmar_probe), 586 DEVMETHOD(device_attach, dmar_attach), 587 DEVMETHOD(device_detach, dmar_detach), 588 DEVMETHOD(device_suspend, dmar_suspend), 589 DEVMETHOD(device_resume, dmar_resume), 590 #ifdef DEV_APIC 591 DEVMETHOD(bus_remap_intr, dmar_remap_intr), 592 #endif 593 DEVMETHOD_END 594 }; 595 596 static driver_t dmar_driver = { 597 "dmar", 598 dmar_methods, 599 sizeof(struct dmar_unit), 600 }; 601 602 DRIVER_MODULE(dmar, acpi, dmar_driver, 0, 0); 603 MODULE_DEPEND(dmar, acpi, 1, 1, 1); 604 605 static void 606 dmar_print_path(int busno, int depth, const ACPI_DMAR_PCI_PATH *path) 607 { 608 int i; 609 610 printf("[%d, ", busno); 611 for (i = 0; i < depth; i++) { 612 if (i != 0) 613 printf(", "); 614 printf("(%d, %d)", path[i].Device, path[i].Function); 615 } 616 printf("]"); 617 } 618 619 int 620 dmar_dev_depth(device_t child) 621 { 622 devclass_t pci_class; 623 device_t bus, pcib; 624 int depth; 625 626 pci_class = devclass_find("pci"); 627 for (depth = 1; ; depth++) { 628 bus = device_get_parent(child); 629 pcib = device_get_parent(bus); 630 if (device_get_devclass(device_get_parent(pcib)) != 631 pci_class) 632 return (depth); 633 child = pcib; 634 } 635 } 636 637 void 638 dmar_dev_path(device_t child, int *busno, void *path1, int depth) 639 { 640 devclass_t pci_class; 641 device_t bus, pcib; 642 ACPI_DMAR_PCI_PATH *path; 643 644 pci_class = devclass_find("pci"); 645 path = path1; 646 for (depth--; depth != -1; depth--) { 647 path[depth].Device = pci_get_slot(child); 648 path[depth].Function = pci_get_function(child); 649 bus = device_get_parent(child); 650 pcib = device_get_parent(bus); 651 if (device_get_devclass(device_get_parent(pcib)) != 652 pci_class) { 653 /* reached a host bridge */ 654 *busno = pcib_get_bus(bus); 655 return; 656 } 657 child = pcib; 658 } 659 panic("wrong depth"); 660 } 661 662 static int 663 dmar_match_pathes(int busno1, const ACPI_DMAR_PCI_PATH *path1, int depth1, 664 int busno2, const ACPI_DMAR_PCI_PATH *path2, int depth2, 665 enum AcpiDmarScopeType scope_type) 666 { 667 int i, depth; 668 669 if (busno1 != busno2) 670 return (0); 671 if (scope_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && depth1 != depth2) 672 return (0); 673 depth = depth1; 674 if (depth2 < depth) 675 depth = depth2; 676 for (i = 0; i < depth; i++) { 677 if (path1[i].Device != path2[i].Device || 678 path1[i].Function != path2[i].Function) 679 return (0); 680 } 681 return (1); 682 } 683 684 static int 685 dmar_match_devscope(ACPI_DMAR_DEVICE_SCOPE *devscope, int dev_busno, 686 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len) 687 { 688 ACPI_DMAR_PCI_PATH *path; 689 int path_len; 690 691 if (devscope->Length < sizeof(*devscope)) { 692 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n", 693 devscope->Length); 694 return (-1); 695 } 696 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT && 697 devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_BRIDGE) 698 return (0); 699 path_len = devscope->Length - sizeof(*devscope); 700 if (path_len % 2 != 0) { 701 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n", 702 devscope->Length); 703 return (-1); 704 } 705 path_len /= 2; 706 path = (ACPI_DMAR_PCI_PATH *)(devscope + 1); 707 if (path_len == 0) { 708 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n", 709 devscope->Length); 710 return (-1); 711 } 712 713 return (dmar_match_pathes(devscope->Bus, path, path_len, dev_busno, 714 dev_path, dev_path_len, devscope->EntryType)); 715 } 716 717 static bool 718 dmar_match_by_path(struct dmar_unit *unit, int dev_domain, int dev_busno, 719 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len, const char **banner) 720 { 721 ACPI_DMAR_HARDWARE_UNIT *dmarh; 722 ACPI_DMAR_DEVICE_SCOPE *devscope; 723 char *ptr, *ptrend; 724 int match; 725 726 dmarh = dmar_find_by_index(unit->iommu.unit); 727 if (dmarh == NULL) 728 return (false); 729 if (dmarh->Segment != dev_domain) 730 return (false); 731 if ((dmarh->Flags & ACPI_DMAR_INCLUDE_ALL) != 0) { 732 if (banner != NULL) 733 *banner = "INCLUDE_ALL"; 734 return (true); 735 } 736 ptr = (char *)dmarh + sizeof(*dmarh); 737 ptrend = (char *)dmarh + dmarh->Header.Length; 738 while (ptr < ptrend) { 739 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 740 ptr += devscope->Length; 741 match = dmar_match_devscope(devscope, dev_busno, dev_path, 742 dev_path_len); 743 if (match == -1) 744 return (false); 745 if (match == 1) { 746 if (banner != NULL) 747 *banner = "specific match"; 748 return (true); 749 } 750 } 751 return (false); 752 } 753 754 static struct dmar_unit * 755 dmar_find_by_scope(int dev_domain, int dev_busno, 756 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len) 757 { 758 struct dmar_unit *unit; 759 int i; 760 761 for (i = 0; i < dmar_devcnt; i++) { 762 if (dmar_devs[i] == NULL) 763 continue; 764 unit = device_get_softc(dmar_devs[i]); 765 if (dmar_match_by_path(unit, dev_domain, dev_busno, dev_path, 766 dev_path_len, NULL)) 767 return (unit); 768 } 769 return (NULL); 770 } 771 772 struct dmar_unit * 773 dmar_find(device_t dev, bool verbose) 774 { 775 struct dmar_unit *unit; 776 const char *banner; 777 int i, dev_domain, dev_busno, dev_path_len; 778 779 /* 780 * This function can only handle PCI(e) devices. 781 */ 782 if (device_get_devclass(device_get_parent(dev)) != 783 devclass_find("pci")) 784 return (NULL); 785 786 dev_domain = pci_get_domain(dev); 787 dev_path_len = dmar_dev_depth(dev); 788 ACPI_DMAR_PCI_PATH dev_path[dev_path_len]; 789 dmar_dev_path(dev, &dev_busno, dev_path, dev_path_len); 790 banner = ""; 791 792 for (i = 0; i < dmar_devcnt; i++) { 793 if (dmar_devs[i] == NULL) 794 continue; 795 unit = device_get_softc(dmar_devs[i]); 796 if (dmar_match_by_path(unit, dev_domain, dev_busno, 797 dev_path, dev_path_len, &banner)) 798 break; 799 } 800 if (i == dmar_devcnt) 801 return (NULL); 802 803 if (verbose) { 804 device_printf(dev, "pci%d:%d:%d:%d matched dmar%d by %s", 805 dev_domain, pci_get_bus(dev), pci_get_slot(dev), 806 pci_get_function(dev), unit->iommu.unit, banner); 807 printf(" scope path "); 808 dmar_print_path(dev_busno, dev_path_len, dev_path); 809 printf("\n"); 810 } 811 return (unit); 812 } 813 814 static struct dmar_unit * 815 dmar_find_nonpci(u_int id, u_int entry_type, uint16_t *rid) 816 { 817 device_t dmar_dev; 818 struct dmar_unit *unit; 819 ACPI_DMAR_HARDWARE_UNIT *dmarh; 820 ACPI_DMAR_DEVICE_SCOPE *devscope; 821 ACPI_DMAR_PCI_PATH *path; 822 char *ptr, *ptrend; 823 #ifdef DEV_APIC 824 int error; 825 #endif 826 int i; 827 828 for (i = 0; i < dmar_devcnt; i++) { 829 dmar_dev = dmar_devs[i]; 830 if (dmar_dev == NULL) 831 continue; 832 unit = (struct dmar_unit *)device_get_softc(dmar_dev); 833 dmarh = dmar_find_by_index(i); 834 if (dmarh == NULL) 835 continue; 836 ptr = (char *)dmarh + sizeof(*dmarh); 837 ptrend = (char *)dmarh + dmarh->Header.Length; 838 for (;;) { 839 if (ptr >= ptrend) 840 break; 841 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 842 ptr += devscope->Length; 843 if (devscope->EntryType != entry_type) 844 continue; 845 if (devscope->EnumerationId != id) 846 continue; 847 #ifdef DEV_APIC 848 if (entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) { 849 error = ioapic_get_rid(id, rid); 850 /* 851 * If our IOAPIC has PCI bindings then 852 * use the PCI device rid. 853 */ 854 if (error == 0) 855 return (unit); 856 } 857 #endif 858 if (devscope->Length - sizeof(ACPI_DMAR_DEVICE_SCOPE) 859 == 2) { 860 if (rid != NULL) { 861 path = (ACPI_DMAR_PCI_PATH *) 862 (devscope + 1); 863 *rid = PCI_RID(devscope->Bus, 864 path->Device, path->Function); 865 } 866 return (unit); 867 } 868 printf( 869 "dmar_find_nonpci: id %d type %d path length != 2\n", 870 id, entry_type); 871 break; 872 } 873 } 874 return (NULL); 875 } 876 877 struct dmar_unit * 878 dmar_find_hpet(device_t dev, uint16_t *rid) 879 { 880 881 return (dmar_find_nonpci(hpet_get_uid(dev), ACPI_DMAR_SCOPE_TYPE_HPET, 882 rid)); 883 } 884 885 struct dmar_unit * 886 dmar_find_ioapic(u_int apic_id, uint16_t *rid) 887 { 888 889 return (dmar_find_nonpci(apic_id, ACPI_DMAR_SCOPE_TYPE_IOAPIC, rid)); 890 } 891 892 struct rmrr_iter_args { 893 struct dmar_domain *domain; 894 int dev_domain; 895 int dev_busno; 896 const ACPI_DMAR_PCI_PATH *dev_path; 897 int dev_path_len; 898 struct iommu_map_entries_tailq *rmrr_entries; 899 }; 900 901 static int 902 dmar_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 903 { 904 struct rmrr_iter_args *ria; 905 ACPI_DMAR_RESERVED_MEMORY *resmem; 906 ACPI_DMAR_DEVICE_SCOPE *devscope; 907 struct iommu_map_entry *entry; 908 char *ptr, *ptrend; 909 int match; 910 911 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY) 912 return (1); 913 914 ria = arg; 915 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh; 916 if (resmem->Segment != ria->dev_domain) 917 return (1); 918 919 ptr = (char *)resmem + sizeof(*resmem); 920 ptrend = (char *)resmem + resmem->Header.Length; 921 for (;;) { 922 if (ptr >= ptrend) 923 break; 924 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 925 ptr += devscope->Length; 926 match = dmar_match_devscope(devscope, ria->dev_busno, 927 ria->dev_path, ria->dev_path_len); 928 if (match == 1) { 929 entry = iommu_gas_alloc_entry(DOM2IODOM(ria->domain), 930 IOMMU_PGF_WAITOK); 931 entry->start = resmem->BaseAddress; 932 /* The RMRR entry end address is inclusive. */ 933 entry->end = resmem->EndAddress; 934 TAILQ_INSERT_TAIL(ria->rmrr_entries, entry, 935 dmamap_link); 936 } 937 } 938 939 return (1); 940 } 941 942 void 943 dmar_dev_parse_rmrr(struct dmar_domain *domain, int dev_domain, int dev_busno, 944 const void *dev_path, int dev_path_len, 945 struct iommu_map_entries_tailq *rmrr_entries) 946 { 947 struct rmrr_iter_args ria; 948 949 ria.domain = domain; 950 ria.dev_domain = dev_domain; 951 ria.dev_busno = dev_busno; 952 ria.dev_path = (const ACPI_DMAR_PCI_PATH *)dev_path; 953 ria.dev_path_len = dev_path_len; 954 ria.rmrr_entries = rmrr_entries; 955 dmar_iterate_tbl(dmar_rmrr_iter, &ria); 956 } 957 958 struct inst_rmrr_iter_args { 959 struct dmar_unit *dmar; 960 }; 961 962 static device_t 963 dmar_path_dev(int segment, int path_len, int busno, 964 const ACPI_DMAR_PCI_PATH *path, uint16_t *rid) 965 { 966 device_t dev; 967 int i; 968 969 dev = NULL; 970 for (i = 0; i < path_len; i++) { 971 dev = pci_find_dbsf(segment, busno, path->Device, 972 path->Function); 973 if (i != path_len - 1) { 974 busno = pci_cfgregread(busno, path->Device, 975 path->Function, PCIR_SECBUS_1, 1); 976 path++; 977 } 978 } 979 *rid = PCI_RID(busno, path->Device, path->Function); 980 return (dev); 981 } 982 983 static int 984 dmar_inst_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 985 { 986 const ACPI_DMAR_RESERVED_MEMORY *resmem; 987 const ACPI_DMAR_DEVICE_SCOPE *devscope; 988 struct inst_rmrr_iter_args *iria; 989 const char *ptr, *ptrend; 990 device_t dev; 991 struct dmar_unit *unit; 992 int dev_path_len; 993 uint16_t rid; 994 995 iria = arg; 996 997 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY) 998 return (1); 999 1000 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh; 1001 if (resmem->Segment != iria->dmar->segment) 1002 return (1); 1003 1004 ptr = (const char *)resmem + sizeof(*resmem); 1005 ptrend = (const char *)resmem + resmem->Header.Length; 1006 for (;;) { 1007 if (ptr >= ptrend) 1008 break; 1009 devscope = (const ACPI_DMAR_DEVICE_SCOPE *)ptr; 1010 ptr += devscope->Length; 1011 /* XXXKIB bridge */ 1012 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT) 1013 continue; 1014 rid = 0; 1015 dev_path_len = (devscope->Length - 1016 sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2; 1017 dev = dmar_path_dev(resmem->Segment, dev_path_len, 1018 devscope->Bus, 1019 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), &rid); 1020 if (dev == NULL) { 1021 if (bootverbose) { 1022 printf("dmar%d no dev found for RMRR " 1023 "[%#jx, %#jx] rid %#x scope path ", 1024 iria->dmar->iommu.unit, 1025 (uintmax_t)resmem->BaseAddress, 1026 (uintmax_t)resmem->EndAddress, 1027 rid); 1028 dmar_print_path(devscope->Bus, dev_path_len, 1029 (const ACPI_DMAR_PCI_PATH *)(devscope + 1)); 1030 printf("\n"); 1031 } 1032 unit = dmar_find_by_scope(resmem->Segment, 1033 devscope->Bus, 1034 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), 1035 dev_path_len); 1036 if (iria->dmar != unit) 1037 continue; 1038 dmar_get_ctx_for_devpath(iria->dmar, rid, 1039 resmem->Segment, devscope->Bus, 1040 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), 1041 dev_path_len, false, true); 1042 } else { 1043 unit = dmar_find(dev, false); 1044 if (iria->dmar != unit) 1045 continue; 1046 iommu_instantiate_ctx(&(iria)->dmar->iommu, 1047 dev, true); 1048 } 1049 } 1050 1051 return (1); 1052 1053 } 1054 1055 /* 1056 * Pre-create all contexts for the DMAR which have RMRR entries. 1057 */ 1058 int 1059 dmar_instantiate_rmrr_ctxs(struct iommu_unit *unit) 1060 { 1061 struct dmar_unit *dmar; 1062 struct inst_rmrr_iter_args iria; 1063 int error; 1064 1065 dmar = IOMMU2DMAR(unit); 1066 1067 if (!dmar_barrier_enter(dmar, DMAR_BARRIER_RMRR)) 1068 return (0); 1069 1070 error = 0; 1071 iria.dmar = dmar; 1072 dmar_iterate_tbl(dmar_inst_rmrr_iter, &iria); 1073 DMAR_LOCK(dmar); 1074 if (!LIST_EMPTY(&dmar->domains)) { 1075 KASSERT((dmar->hw_gcmd & DMAR_GCMD_TE) == 0, 1076 ("dmar%d: RMRR not handled but translation is already enabled", 1077 dmar->iommu.unit)); 1078 error = dmar_disable_protected_regions(dmar); 1079 if (error != 0) 1080 printf("dmar%d: Failed to disable protected regions\n", 1081 dmar->iommu.unit); 1082 error = dmar_enable_translation(dmar); 1083 if (bootverbose) { 1084 if (error == 0) { 1085 printf("dmar%d: enabled translation\n", 1086 dmar->iommu.unit); 1087 } else { 1088 printf("dmar%d: enabling translation failed, " 1089 "error %d\n", dmar->iommu.unit, error); 1090 } 1091 } 1092 } 1093 dmar_barrier_exit(dmar, DMAR_BARRIER_RMRR); 1094 return (error); 1095 } 1096 1097 #ifdef DDB 1098 #include <ddb/ddb.h> 1099 #include <ddb/db_lex.h> 1100 1101 static void 1102 dmar_print_domain_entry(const struct iommu_map_entry *entry) 1103 { 1104 struct iommu_map_entry *l, *r; 1105 1106 db_printf( 1107 " start %jx end %jx first %jx last %jx free_down %jx flags %x ", 1108 entry->start, entry->end, entry->first, entry->last, 1109 entry->free_down, entry->flags); 1110 db_printf("left "); 1111 l = RB_LEFT(entry, rb_entry); 1112 if (l == NULL) 1113 db_printf("NULL "); 1114 else 1115 db_printf("%jx ", l->start); 1116 db_printf("right "); 1117 r = RB_RIGHT(entry, rb_entry); 1118 if (r == NULL) 1119 db_printf("NULL"); 1120 else 1121 db_printf("%jx", r->start); 1122 db_printf("\n"); 1123 } 1124 1125 static void 1126 dmar_print_ctx(struct dmar_ctx *ctx) 1127 { 1128 1129 db_printf( 1130 " @%p pci%d:%d:%d refs %d flags %x loads %lu unloads %lu\n", 1131 ctx, pci_get_bus(ctx->context.tag->owner), 1132 pci_get_slot(ctx->context.tag->owner), 1133 pci_get_function(ctx->context.tag->owner), ctx->refs, 1134 ctx->context.flags, ctx->context.loads, ctx->context.unloads); 1135 } 1136 1137 static void 1138 dmar_print_domain(struct dmar_domain *domain, bool show_mappings) 1139 { 1140 struct iommu_domain *iodom; 1141 struct iommu_map_entry *entry; 1142 struct dmar_ctx *ctx; 1143 1144 iodom = DOM2IODOM(domain); 1145 1146 db_printf( 1147 " @%p dom %d mgaw %d agaw %d pglvl %d end %jx refs %d\n" 1148 " ctx_cnt %d flags %x pgobj %p map_ents %u\n", 1149 domain, domain->domain, domain->mgaw, domain->agaw, domain->pglvl, 1150 (uintmax_t)domain->iodom.end, domain->refs, domain->ctx_cnt, 1151 domain->iodom.flags, domain->pgtbl_obj, domain->iodom.entries_cnt); 1152 if (!LIST_EMPTY(&domain->contexts)) { 1153 db_printf(" Contexts:\n"); 1154 LIST_FOREACH(ctx, &domain->contexts, link) 1155 dmar_print_ctx(ctx); 1156 } 1157 if (!show_mappings) 1158 return; 1159 db_printf(" mapped:\n"); 1160 RB_FOREACH(entry, iommu_gas_entries_tree, &iodom->rb_root) { 1161 dmar_print_domain_entry(entry); 1162 if (db_pager_quit) 1163 break; 1164 } 1165 if (db_pager_quit) 1166 return; 1167 db_printf(" unloading:\n"); 1168 TAILQ_FOREACH(entry, &domain->iodom.unload_entries, dmamap_link) { 1169 dmar_print_domain_entry(entry); 1170 if (db_pager_quit) 1171 break; 1172 } 1173 } 1174 1175 DB_SHOW_COMMAND_FLAGS(dmar_domain, db_dmar_print_domain, CS_OWN) 1176 { 1177 struct dmar_unit *unit; 1178 struct dmar_domain *domain; 1179 struct dmar_ctx *ctx; 1180 bool show_mappings, valid; 1181 int pci_domain, bus, device, function, i, t; 1182 db_expr_t radix; 1183 1184 valid = false; 1185 radix = db_radix; 1186 db_radix = 10; 1187 t = db_read_token(); 1188 if (t == tSLASH) { 1189 t = db_read_token(); 1190 if (t != tIDENT) { 1191 db_printf("Bad modifier\n"); 1192 db_radix = radix; 1193 db_skip_to_eol(); 1194 return; 1195 } 1196 show_mappings = strchr(db_tok_string, 'm') != NULL; 1197 t = db_read_token(); 1198 } else { 1199 show_mappings = false; 1200 } 1201 if (t == tNUMBER) { 1202 pci_domain = db_tok_number; 1203 t = db_read_token(); 1204 if (t == tNUMBER) { 1205 bus = db_tok_number; 1206 t = db_read_token(); 1207 if (t == tNUMBER) { 1208 device = db_tok_number; 1209 t = db_read_token(); 1210 if (t == tNUMBER) { 1211 function = db_tok_number; 1212 valid = true; 1213 } 1214 } 1215 } 1216 } 1217 db_radix = radix; 1218 db_skip_to_eol(); 1219 if (!valid) { 1220 db_printf("usage: show dmar_domain [/m] " 1221 "<domain> <bus> <device> <func>\n"); 1222 return; 1223 } 1224 for (i = 0; i < dmar_devcnt; i++) { 1225 unit = device_get_softc(dmar_devs[i]); 1226 LIST_FOREACH(domain, &unit->domains, link) { 1227 LIST_FOREACH(ctx, &domain->contexts, link) { 1228 if (pci_domain == unit->segment && 1229 bus == pci_get_bus(ctx->context.tag->owner) && 1230 device == 1231 pci_get_slot(ctx->context.tag->owner) && 1232 function == 1233 pci_get_function(ctx->context.tag->owner)) { 1234 dmar_print_domain(domain, 1235 show_mappings); 1236 goto out; 1237 } 1238 } 1239 } 1240 } 1241 out:; 1242 } 1243 1244 static void 1245 dmar_print_one(int idx, bool show_domains, bool show_mappings) 1246 { 1247 struct dmar_unit *unit; 1248 struct dmar_domain *domain; 1249 int i, frir; 1250 1251 unit = device_get_softc(dmar_devs[idx]); 1252 db_printf("dmar%d at %p, root at 0x%jx, ver 0x%x\n", unit->iommu.unit, 1253 unit, dmar_read8(unit, DMAR_RTADDR_REG), 1254 dmar_read4(unit, DMAR_VER_REG)); 1255 db_printf("cap 0x%jx ecap 0x%jx gsts 0x%x fsts 0x%x fectl 0x%x\n", 1256 (uintmax_t)dmar_read8(unit, DMAR_CAP_REG), 1257 (uintmax_t)dmar_read8(unit, DMAR_ECAP_REG), 1258 dmar_read4(unit, DMAR_GSTS_REG), 1259 dmar_read4(unit, DMAR_FSTS_REG), 1260 dmar_read4(unit, DMAR_FECTL_REG)); 1261 if (unit->ir_enabled) { 1262 db_printf("ir is enabled; IRT @%p phys 0x%jx maxcnt %d\n", 1263 unit->irt, (uintmax_t)unit->irt_phys, unit->irte_cnt); 1264 } 1265 db_printf("fed 0x%x fea 0x%x feua 0x%x\n", 1266 dmar_read4(unit, DMAR_FEDATA_REG), 1267 dmar_read4(unit, DMAR_FEADDR_REG), 1268 dmar_read4(unit, DMAR_FEUADDR_REG)); 1269 db_printf("primary fault log:\n"); 1270 for (i = 0; i < DMAR_CAP_NFR(unit->hw_cap); i++) { 1271 frir = (DMAR_CAP_FRO(unit->hw_cap) + i) * 16; 1272 db_printf(" %d at 0x%x: %jx %jx\n", i, frir, 1273 (uintmax_t)dmar_read8(unit, frir), 1274 (uintmax_t)dmar_read8(unit, frir + 8)); 1275 } 1276 if (DMAR_HAS_QI(unit)) { 1277 db_printf("ied 0x%x iea 0x%x ieua 0x%x\n", 1278 dmar_read4(unit, DMAR_IEDATA_REG), 1279 dmar_read4(unit, DMAR_IEADDR_REG), 1280 dmar_read4(unit, DMAR_IEUADDR_REG)); 1281 if (unit->qi_enabled) { 1282 db_printf("qi is enabled: queue @0x%jx (IQA 0x%jx) " 1283 "size 0x%jx\n" 1284 " head 0x%x tail 0x%x avail 0x%x status 0x%x ctrl 0x%x\n" 1285 " hw compl 0x%x@%p/phys@%jx next seq 0x%x gen 0x%x\n", 1286 (uintmax_t)unit->inv_queue, 1287 (uintmax_t)dmar_read8(unit, DMAR_IQA_REG), 1288 (uintmax_t)unit->inv_queue_size, 1289 dmar_read4(unit, DMAR_IQH_REG), 1290 dmar_read4(unit, DMAR_IQT_REG), 1291 unit->inv_queue_avail, 1292 dmar_read4(unit, DMAR_ICS_REG), 1293 dmar_read4(unit, DMAR_IECTL_REG), 1294 unit->inv_waitd_seq_hw, 1295 &unit->inv_waitd_seq_hw, 1296 (uintmax_t)unit->inv_waitd_seq_hw_phys, 1297 unit->inv_waitd_seq, 1298 unit->inv_waitd_gen); 1299 } else { 1300 db_printf("qi is disabled\n"); 1301 } 1302 } 1303 if (show_domains) { 1304 db_printf("domains:\n"); 1305 LIST_FOREACH(domain, &unit->domains, link) { 1306 dmar_print_domain(domain, show_mappings); 1307 if (db_pager_quit) 1308 break; 1309 } 1310 } 1311 } 1312 1313 DB_SHOW_COMMAND(dmar, db_dmar_print) 1314 { 1315 bool show_domains, show_mappings; 1316 1317 show_domains = strchr(modif, 'd') != NULL; 1318 show_mappings = strchr(modif, 'm') != NULL; 1319 if (!have_addr) { 1320 db_printf("usage: show dmar [/d] [/m] index\n"); 1321 return; 1322 } 1323 dmar_print_one((int)addr, show_domains, show_mappings); 1324 } 1325 1326 DB_SHOW_ALL_COMMAND(dmars, db_show_all_dmars) 1327 { 1328 int i; 1329 bool show_domains, show_mappings; 1330 1331 show_domains = strchr(modif, 'd') != NULL; 1332 show_mappings = strchr(modif, 'm') != NULL; 1333 1334 for (i = 0; i < dmar_devcnt; i++) { 1335 dmar_print_one(i, show_domains, show_mappings); 1336 if (db_pager_quit) 1337 break; 1338 } 1339 } 1340 #endif 1341 1342 struct iommu_unit * 1343 iommu_find(device_t dev, bool verbose) 1344 { 1345 struct dmar_unit *dmar; 1346 1347 dmar = dmar_find(dev, verbose); 1348 1349 return (&dmar->iommu); 1350 }
Cache object: 9e0d73680ac38bb6e7092041c24264e3
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