The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/x86/iommu/intel_drv.c

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    1 /*-
    2  * Copyright (c) 2013-2015 The FreeBSD Foundation
    3  * All rights reserved.
    4  *
    5  * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
    6  * under sponsorship from the FreeBSD Foundation.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  */
   29 
   30 #include <sys/cdefs.h>
   31 __FBSDID("$FreeBSD: releng/11.2/sys/x86/iommu/intel_drv.c 323921 2017-09-22 10:51:32Z kib $");
   32 
   33 #include "opt_acpi.h"
   34 #if defined(__amd64__)
   35 #define DEV_APIC
   36 #else
   37 #include "opt_apic.h"
   38 #endif
   39 #include "opt_ddb.h"
   40 
   41 #include <sys/param.h>
   42 #include <sys/bus.h>
   43 #include <sys/kernel.h>
   44 #include <sys/lock.h>
   45 #include <sys/malloc.h>
   46 #include <sys/memdesc.h>
   47 #include <sys/module.h>
   48 #include <sys/rman.h>
   49 #include <sys/rwlock.h>
   50 #include <sys/smp.h>
   51 #include <sys/taskqueue.h>
   52 #include <sys/tree.h>
   53 #include <sys/vmem.h>
   54 #include <machine/bus.h>
   55 #include <contrib/dev/acpica/include/acpi.h>
   56 #include <contrib/dev/acpica/include/accommon.h>
   57 #include <dev/acpica/acpivar.h>
   58 #include <vm/vm.h>
   59 #include <vm/vm_extern.h>
   60 #include <vm/vm_kern.h>
   61 #include <vm/vm_object.h>
   62 #include <vm/vm_page.h>
   63 #include <vm/vm_pager.h>
   64 #include <vm/vm_map.h>
   65 #include <x86/include/busdma_impl.h>
   66 #include <x86/iommu/intel_reg.h>
   67 #include <x86/iommu/busdma_dmar.h>
   68 #include <x86/iommu/intel_dmar.h>
   69 #include <dev/pci/pcireg.h>
   70 #include <dev/pci/pcivar.h>
   71 
   72 #ifdef DEV_APIC
   73 #include "pcib_if.h"
   74 #include <machine/intr_machdep.h>
   75 #include <x86/apicreg.h>
   76 #include <x86/apicvar.h>
   77 #endif
   78 
   79 #define DMAR_FAULT_IRQ_RID      0
   80 #define DMAR_QI_IRQ_RID         1
   81 #define DMAR_REG_RID            2
   82 
   83 static devclass_t dmar_devclass;
   84 static device_t *dmar_devs;
   85 static int dmar_devcnt;
   86 
   87 typedef int (*dmar_iter_t)(ACPI_DMAR_HEADER *, void *);
   88 
   89 static void
   90 dmar_iterate_tbl(dmar_iter_t iter, void *arg)
   91 {
   92         ACPI_TABLE_DMAR *dmartbl;
   93         ACPI_DMAR_HEADER *dmarh;
   94         char *ptr, *ptrend;
   95         ACPI_STATUS status;
   96 
   97         status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl);
   98         if (ACPI_FAILURE(status))
   99                 return;
  100         ptr = (char *)dmartbl + sizeof(*dmartbl);
  101         ptrend = (char *)dmartbl + dmartbl->Header.Length;
  102         for (;;) {
  103                 if (ptr >= ptrend)
  104                         break;
  105                 dmarh = (ACPI_DMAR_HEADER *)ptr;
  106                 if (dmarh->Length <= 0) {
  107                         printf("dmar_identify: corrupted DMAR table, l %d\n",
  108                             dmarh->Length);
  109                         break;
  110                 }
  111                 ptr += dmarh->Length;
  112                 if (!iter(dmarh, arg))
  113                         break;
  114         }
  115         AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl);
  116 }
  117 
  118 struct find_iter_args {
  119         int i;
  120         ACPI_DMAR_HARDWARE_UNIT *res;
  121 };
  122 
  123 static int
  124 dmar_find_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
  125 {
  126         struct find_iter_args *fia;
  127 
  128         if (dmarh->Type != ACPI_DMAR_TYPE_HARDWARE_UNIT)
  129                 return (1);
  130 
  131         fia = arg;
  132         if (fia->i == 0) {
  133                 fia->res = (ACPI_DMAR_HARDWARE_UNIT *)dmarh;
  134                 return (0);
  135         }
  136         fia->i--;
  137         return (1);
  138 }
  139 
  140 static ACPI_DMAR_HARDWARE_UNIT *
  141 dmar_find_by_index(int idx)
  142 {
  143         struct find_iter_args fia;
  144 
  145         fia.i = idx;
  146         fia.res = NULL;
  147         dmar_iterate_tbl(dmar_find_iter, &fia);
  148         return (fia.res);
  149 }
  150 
  151 static int
  152 dmar_count_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
  153 {
  154 
  155         if (dmarh->Type == ACPI_DMAR_TYPE_HARDWARE_UNIT)
  156                 dmar_devcnt++;
  157         return (1);
  158 }
  159 
  160 static int dmar_enable = 0;
  161 static void
  162 dmar_identify(driver_t *driver, device_t parent)
  163 {
  164         ACPI_TABLE_DMAR *dmartbl;
  165         ACPI_DMAR_HARDWARE_UNIT *dmarh;
  166         ACPI_STATUS status;
  167         int i, error;
  168 
  169         if (acpi_disabled("dmar"))
  170                 return;
  171         TUNABLE_INT_FETCH("hw.dmar.enable", &dmar_enable);
  172         if (!dmar_enable)
  173                 return;
  174 #ifdef INVARIANTS
  175         TUNABLE_INT_FETCH("hw.dmar.check_free", &dmar_check_free);
  176 #endif
  177         TUNABLE_INT_FETCH("hw.dmar.match_verbose", &dmar_match_verbose);
  178         status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl);
  179         if (ACPI_FAILURE(status))
  180                 return;
  181         haw = dmartbl->Width + 1;
  182         if ((1ULL << (haw + 1)) > BUS_SPACE_MAXADDR)
  183                 dmar_high = BUS_SPACE_MAXADDR;
  184         else
  185                 dmar_high = 1ULL << (haw + 1);
  186         if (bootverbose) {
  187                 printf("DMAR HAW=%d flags=<%b>\n", dmartbl->Width,
  188                     (unsigned)dmartbl->Flags,
  189                     "\020\001INTR_REMAP\002X2APIC_OPT_OUT");
  190         }
  191         AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl);
  192 
  193         dmar_iterate_tbl(dmar_count_iter, NULL);
  194         if (dmar_devcnt == 0)
  195                 return;
  196         dmar_devs = malloc(sizeof(device_t) * dmar_devcnt, M_DEVBUF,
  197             M_WAITOK | M_ZERO);
  198         for (i = 0; i < dmar_devcnt; i++) {
  199                 dmarh = dmar_find_by_index(i);
  200                 if (dmarh == NULL) {
  201                         printf("dmar_identify: cannot find HWUNIT %d\n", i);
  202                         continue;
  203                 }
  204                 dmar_devs[i] = BUS_ADD_CHILD(parent, 1, "dmar", i);
  205                 if (dmar_devs[i] == NULL) {
  206                         printf("dmar_identify: cannot create instance %d\n", i);
  207                         continue;
  208                 }
  209                 error = bus_set_resource(dmar_devs[i], SYS_RES_MEMORY,
  210                     DMAR_REG_RID, dmarh->Address, PAGE_SIZE);
  211                 if (error != 0) {
  212                         printf(
  213         "dmar%d: unable to alloc register window at 0x%08jx: error %d\n",
  214                             i, (uintmax_t)dmarh->Address, error);
  215                         device_delete_child(parent, dmar_devs[i]);
  216                         dmar_devs[i] = NULL;
  217                 }
  218         }
  219 }
  220 
  221 static int
  222 dmar_probe(device_t dev)
  223 {
  224 
  225         if (acpi_get_handle(dev) != NULL)
  226                 return (ENXIO);
  227         device_set_desc(dev, "DMA remap");
  228         return (BUS_PROBE_NOWILDCARD);
  229 }
  230 
  231 static void
  232 dmar_release_intr(device_t dev, struct dmar_unit *unit, int idx)
  233 {
  234         struct dmar_msi_data *dmd;
  235 
  236         dmd = &unit->intrs[idx];
  237         if (dmd->irq == -1)
  238                 return;
  239         bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle);
  240         bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res);
  241         bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid);
  242         PCIB_RELEASE_MSIX(device_get_parent(device_get_parent(dev)),
  243             dev, dmd->irq);
  244         dmd->irq = -1;
  245 }
  246 
  247 static void
  248 dmar_release_resources(device_t dev, struct dmar_unit *unit)
  249 {
  250         int i;
  251 
  252         dmar_fini_busdma(unit);
  253         dmar_fini_irt(unit);
  254         dmar_fini_qi(unit);
  255         dmar_fini_fault_log(unit);
  256         for (i = 0; i < DMAR_INTR_TOTAL; i++)
  257                 dmar_release_intr(dev, unit, i);
  258         if (unit->regs != NULL) {
  259                 bus_deactivate_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
  260                     unit->regs);
  261                 bus_release_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
  262                     unit->regs);
  263                 unit->regs = NULL;
  264         }
  265         if (unit->domids != NULL) {
  266                 delete_unrhdr(unit->domids);
  267                 unit->domids = NULL;
  268         }
  269         if (unit->ctx_obj != NULL) {
  270                 vm_object_deallocate(unit->ctx_obj);
  271                 unit->ctx_obj = NULL;
  272         }
  273 }
  274 
  275 static int
  276 dmar_alloc_irq(device_t dev, struct dmar_unit *unit, int idx)
  277 {
  278         device_t pcib;
  279         struct dmar_msi_data *dmd;
  280         uint64_t msi_addr;
  281         uint32_t msi_data;
  282         int error;
  283 
  284         dmd = &unit->intrs[idx];
  285         pcib = device_get_parent(device_get_parent(dev)); /* Really not pcib */
  286         error = PCIB_ALLOC_MSIX(pcib, dev, &dmd->irq);
  287         if (error != 0) {
  288                 device_printf(dev, "cannot allocate %s interrupt, %d\n",
  289                     dmd->name, error);
  290                 goto err1;
  291         }
  292         error = bus_set_resource(dev, SYS_RES_IRQ, dmd->irq_rid,
  293             dmd->irq, 1);
  294         if (error != 0) {
  295                 device_printf(dev, "cannot set %s interrupt resource, %d\n",
  296                     dmd->name, error);
  297                 goto err2;
  298         }
  299         dmd->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
  300             &dmd->irq_rid, RF_ACTIVE);
  301         if (dmd->irq_res == NULL) {
  302                 device_printf(dev,
  303                     "cannot allocate resource for %s interrupt\n", dmd->name);
  304                 error = ENXIO;
  305                 goto err3;
  306         }
  307         error = bus_setup_intr(dev, dmd->irq_res, INTR_TYPE_MISC,
  308             dmd->handler, NULL, unit, &dmd->intr_handle);
  309         if (error != 0) {
  310                 device_printf(dev, "cannot setup %s interrupt, %d\n",
  311                     dmd->name, error);
  312                 goto err4;
  313         }
  314         bus_describe_intr(dev, dmd->irq_res, dmd->intr_handle, "%s", dmd->name);
  315         error = PCIB_MAP_MSI(pcib, dev, dmd->irq, &msi_addr, &msi_data);
  316         if (error != 0) {
  317                 device_printf(dev, "cannot map %s interrupt, %d\n",
  318                     dmd->name, error);
  319                 goto err5;
  320         }
  321         dmar_write4(unit, dmd->msi_data_reg, msi_data);
  322         dmar_write4(unit, dmd->msi_addr_reg, msi_addr);
  323         /* Only for xAPIC mode */
  324         dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32);
  325         return (0);
  326 
  327 err5:
  328         bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle);
  329 err4:
  330         bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res);
  331 err3:
  332         bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid);
  333 err2:
  334         PCIB_RELEASE_MSIX(pcib, dev, dmd->irq);
  335         dmd->irq = -1;
  336 err1:
  337         return (error);
  338 }
  339 
  340 #ifdef DEV_APIC
  341 static int
  342 dmar_remap_intr(device_t dev, device_t child, u_int irq)
  343 {
  344         struct dmar_unit *unit;
  345         struct dmar_msi_data *dmd;
  346         uint64_t msi_addr;
  347         uint32_t msi_data;
  348         int i, error;
  349 
  350         unit = device_get_softc(dev);
  351         for (i = 0; i < DMAR_INTR_TOTAL; i++) {
  352                 dmd = &unit->intrs[i];
  353                 if (irq == dmd->irq) {
  354                         error = PCIB_MAP_MSI(device_get_parent(
  355                             device_get_parent(dev)),
  356                             dev, irq, &msi_addr, &msi_data);
  357                         if (error != 0)
  358                                 return (error);
  359                         DMAR_LOCK(unit);
  360                         (dmd->disable_intr)(unit);
  361                         dmar_write4(unit, dmd->msi_data_reg, msi_data);
  362                         dmar_write4(unit, dmd->msi_addr_reg, msi_addr);
  363                         dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32);
  364                         (dmd->enable_intr)(unit);
  365                         DMAR_UNLOCK(unit);
  366                         return (0);
  367                 }
  368         }
  369         return (ENOENT);
  370 }
  371 #endif
  372 
  373 static void
  374 dmar_print_caps(device_t dev, struct dmar_unit *unit,
  375     ACPI_DMAR_HARDWARE_UNIT *dmaru)
  376 {
  377         uint32_t caphi, ecaphi;
  378 
  379         device_printf(dev, "regs@0x%08jx, ver=%d.%d, seg=%d, flags=<%b>\n",
  380             (uintmax_t)dmaru->Address, DMAR_MAJOR_VER(unit->hw_ver),
  381             DMAR_MINOR_VER(unit->hw_ver), dmaru->Segment,
  382             dmaru->Flags, "\020\001INCLUDE_ALL_PCI");
  383         caphi = unit->hw_cap >> 32;
  384         device_printf(dev, "cap=%b,", (u_int)unit->hw_cap,
  385             "\020\004AFL\005WBF\006PLMR\007PHMR\010CM\027ZLR\030ISOCH");
  386         printf("%b, ", caphi, "\020\010PSI\027DWD\030DRD\031FL1GP\034PSI");
  387         printf("ndoms=%d, sagaw=%d, mgaw=%d, fro=%d, nfr=%d, superp=%d",
  388             DMAR_CAP_ND(unit->hw_cap), DMAR_CAP_SAGAW(unit->hw_cap),
  389             DMAR_CAP_MGAW(unit->hw_cap), DMAR_CAP_FRO(unit->hw_cap),
  390             DMAR_CAP_NFR(unit->hw_cap), DMAR_CAP_SPS(unit->hw_cap));
  391         if ((unit->hw_cap & DMAR_CAP_PSI) != 0)
  392                 printf(", mamv=%d", DMAR_CAP_MAMV(unit->hw_cap));
  393         printf("\n");
  394         ecaphi = unit->hw_ecap >> 32;
  395         device_printf(dev, "ecap=%b,", (u_int)unit->hw_ecap,
  396             "\020\001C\002QI\003DI\004IR\005EIM\007PT\010SC\031ECS\032MTS"
  397             "\033NEST\034DIS\035PASID\036PRS\037ERS\040SRS");
  398         printf("%b, ", ecaphi, "\020\002NWFS\003EAFS");
  399         printf("mhmw=%d, iro=%d\n", DMAR_ECAP_MHMV(unit->hw_ecap),
  400             DMAR_ECAP_IRO(unit->hw_ecap));
  401 }
  402 
  403 static int
  404 dmar_attach(device_t dev)
  405 {
  406         struct dmar_unit *unit;
  407         ACPI_DMAR_HARDWARE_UNIT *dmaru;
  408         uint64_t timeout;
  409         int i, error;
  410 
  411         unit = device_get_softc(dev);
  412         unit->dev = dev;
  413         unit->unit = device_get_unit(dev);
  414         dmaru = dmar_find_by_index(unit->unit);
  415         if (dmaru == NULL)
  416                 return (EINVAL);
  417         unit->segment = dmaru->Segment;
  418         unit->base = dmaru->Address;
  419         unit->reg_rid = DMAR_REG_RID;
  420         unit->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
  421             &unit->reg_rid, RF_ACTIVE);
  422         if (unit->regs == NULL) {
  423                 device_printf(dev, "cannot allocate register window\n");
  424                 return (ENOMEM);
  425         }
  426         unit->hw_ver = dmar_read4(unit, DMAR_VER_REG);
  427         unit->hw_cap = dmar_read8(unit, DMAR_CAP_REG);
  428         unit->hw_ecap = dmar_read8(unit, DMAR_ECAP_REG);
  429         if (bootverbose)
  430                 dmar_print_caps(dev, unit, dmaru);
  431         dmar_quirks_post_ident(unit);
  432 
  433         timeout = dmar_get_timeout();
  434         TUNABLE_UINT64_FETCH("hw.dmar.timeout", &timeout);
  435         dmar_update_timeout(timeout);
  436 
  437         for (i = 0; i < DMAR_INTR_TOTAL; i++)
  438                 unit->intrs[i].irq = -1;
  439 
  440         unit->intrs[DMAR_INTR_FAULT].name = "fault";
  441         unit->intrs[DMAR_INTR_FAULT].irq_rid = DMAR_FAULT_IRQ_RID;
  442         unit->intrs[DMAR_INTR_FAULT].handler = dmar_fault_intr;
  443         unit->intrs[DMAR_INTR_FAULT].msi_data_reg = DMAR_FEDATA_REG;
  444         unit->intrs[DMAR_INTR_FAULT].msi_addr_reg = DMAR_FEADDR_REG;
  445         unit->intrs[DMAR_INTR_FAULT].msi_uaddr_reg = DMAR_FEUADDR_REG;
  446         unit->intrs[DMAR_INTR_FAULT].enable_intr = dmar_enable_fault_intr;
  447         unit->intrs[DMAR_INTR_FAULT].disable_intr = dmar_disable_fault_intr;
  448         error = dmar_alloc_irq(dev, unit, DMAR_INTR_FAULT);
  449         if (error != 0) {
  450                 dmar_release_resources(dev, unit);
  451                 return (error);
  452         }
  453         if (DMAR_HAS_QI(unit)) {
  454                 unit->intrs[DMAR_INTR_QI].name = "qi";
  455                 unit->intrs[DMAR_INTR_QI].irq_rid = DMAR_QI_IRQ_RID;
  456                 unit->intrs[DMAR_INTR_QI].handler = dmar_qi_intr;
  457                 unit->intrs[DMAR_INTR_QI].msi_data_reg = DMAR_IEDATA_REG;
  458                 unit->intrs[DMAR_INTR_QI].msi_addr_reg = DMAR_IEADDR_REG;
  459                 unit->intrs[DMAR_INTR_QI].msi_uaddr_reg = DMAR_IEUADDR_REG;
  460                 unit->intrs[DMAR_INTR_QI].enable_intr = dmar_enable_qi_intr;
  461                 unit->intrs[DMAR_INTR_QI].disable_intr = dmar_disable_qi_intr;
  462                 error = dmar_alloc_irq(dev, unit, DMAR_INTR_QI);
  463                 if (error != 0) {
  464                         dmar_release_resources(dev, unit);
  465                         return (error);
  466                 }
  467         }
  468 
  469         mtx_init(&unit->lock, "dmarhw", NULL, MTX_DEF);
  470         unit->domids = new_unrhdr(0, dmar_nd2mask(DMAR_CAP_ND(unit->hw_cap)),
  471             &unit->lock);
  472         LIST_INIT(&unit->domains);
  473 
  474         /*
  475          * 9.2 "Context Entry":
  476          * When Caching Mode (CM) field is reported as Set, the
  477          * domain-id value of zero is architecturally reserved.
  478          * Software must not use domain-id value of zero
  479          * when CM is Set.
  480          */
  481         if ((unit->hw_cap & DMAR_CAP_CM) != 0)
  482                 alloc_unr_specific(unit->domids, 0);
  483 
  484         unit->ctx_obj = vm_pager_allocate(OBJT_PHYS, NULL, IDX_TO_OFF(1 +
  485             DMAR_CTX_CNT), 0, 0, NULL);
  486 
  487         /*
  488          * Allocate and load the root entry table pointer.  Enable the
  489          * address translation after the required invalidations are
  490          * done.
  491          */
  492         dmar_pgalloc(unit->ctx_obj, 0, DMAR_PGF_WAITOK | DMAR_PGF_ZERO);
  493         DMAR_LOCK(unit);
  494         error = dmar_load_root_entry_ptr(unit);
  495         if (error != 0) {
  496                 DMAR_UNLOCK(unit);
  497                 dmar_release_resources(dev, unit);
  498                 return (error);
  499         }
  500         error = dmar_inv_ctx_glob(unit);
  501         if (error != 0) {
  502                 DMAR_UNLOCK(unit);
  503                 dmar_release_resources(dev, unit);
  504                 return (error);
  505         }
  506         if ((unit->hw_ecap & DMAR_ECAP_DI) != 0) {
  507                 error = dmar_inv_iotlb_glob(unit);
  508                 if (error != 0) {
  509                         DMAR_UNLOCK(unit);
  510                         dmar_release_resources(dev, unit);
  511                         return (error);
  512                 }
  513         }
  514 
  515         DMAR_UNLOCK(unit);
  516         error = dmar_init_fault_log(unit);
  517         if (error != 0) {
  518                 dmar_release_resources(dev, unit);
  519                 return (error);
  520         }
  521         error = dmar_init_qi(unit);
  522         if (error != 0) {
  523                 dmar_release_resources(dev, unit);
  524                 return (error);
  525         }
  526         error = dmar_init_irt(unit);
  527         if (error != 0) {
  528                 dmar_release_resources(dev, unit);
  529                 return (error);
  530         }
  531         error = dmar_init_busdma(unit);
  532         if (error != 0) {
  533                 dmar_release_resources(dev, unit);
  534                 return (error);
  535         }
  536 
  537 #ifdef NOTYET
  538         DMAR_LOCK(unit);
  539         error = dmar_enable_translation(unit);
  540         if (error != 0) {
  541                 DMAR_UNLOCK(unit);
  542                 dmar_release_resources(dev, unit);
  543                 return (error);
  544         }
  545         DMAR_UNLOCK(unit);
  546 #endif
  547 
  548         return (0);
  549 }
  550 
  551 static int
  552 dmar_detach(device_t dev)
  553 {
  554 
  555         return (EBUSY);
  556 }
  557 
  558 static int
  559 dmar_suspend(device_t dev)
  560 {
  561 
  562         return (0);
  563 }
  564 
  565 static int
  566 dmar_resume(device_t dev)
  567 {
  568 
  569         /* XXXKIB */
  570         return (0);
  571 }
  572 
  573 static device_method_t dmar_methods[] = {
  574         DEVMETHOD(device_identify, dmar_identify),
  575         DEVMETHOD(device_probe, dmar_probe),
  576         DEVMETHOD(device_attach, dmar_attach),
  577         DEVMETHOD(device_detach, dmar_detach),
  578         DEVMETHOD(device_suspend, dmar_suspend),
  579         DEVMETHOD(device_resume, dmar_resume),
  580 #ifdef DEV_APIC
  581         DEVMETHOD(bus_remap_intr, dmar_remap_intr),
  582 #endif
  583         DEVMETHOD_END
  584 };
  585 
  586 static driver_t dmar_driver = {
  587         "dmar",
  588         dmar_methods,
  589         sizeof(struct dmar_unit),
  590 };
  591 
  592 DRIVER_MODULE(dmar, acpi, dmar_driver, dmar_devclass, 0, 0);
  593 MODULE_DEPEND(dmar, acpi, 1, 1, 1);
  594 
  595 static void
  596 dmar_print_path(device_t dev, const char *banner, int busno, int depth,
  597     const ACPI_DMAR_PCI_PATH *path)
  598 {
  599         int i;
  600 
  601         device_printf(dev, "%s [%d, ", banner, busno);
  602         for (i = 0; i < depth; i++) {
  603                 if (i != 0)
  604                         printf(", ");
  605                 printf("(%d, %d)", path[i].Device, path[i].Function);
  606         }
  607         printf("]\n");
  608 }
  609 
  610 static int
  611 dmar_dev_depth(device_t child)
  612 {
  613         devclass_t pci_class;
  614         device_t bus, pcib;
  615         int depth;
  616 
  617         pci_class = devclass_find("pci");
  618         for (depth = 1; ; depth++) {
  619                 bus = device_get_parent(child);
  620                 pcib = device_get_parent(bus);
  621                 if (device_get_devclass(device_get_parent(pcib)) !=
  622                     pci_class)
  623                         return (depth);
  624                 child = pcib;
  625         }
  626 }
  627 
  628 static void
  629 dmar_dev_path(device_t child, int *busno, ACPI_DMAR_PCI_PATH *path, int depth)
  630 {
  631         devclass_t pci_class;
  632         device_t bus, pcib;
  633 
  634         pci_class = devclass_find("pci");
  635         for (depth--; depth != -1; depth--) {
  636                 path[depth].Device = pci_get_slot(child);
  637                 path[depth].Function = pci_get_function(child);
  638                 bus = device_get_parent(child);
  639                 pcib = device_get_parent(bus);
  640                 if (device_get_devclass(device_get_parent(pcib)) !=
  641                     pci_class) {
  642                         /* reached a host bridge */
  643                         *busno = pcib_get_bus(bus);
  644                         return;
  645                 }
  646                 child = pcib;
  647         }
  648         panic("wrong depth");
  649 }
  650 
  651 static int
  652 dmar_match_pathes(int busno1, const ACPI_DMAR_PCI_PATH *path1, int depth1,
  653     int busno2, const ACPI_DMAR_PCI_PATH *path2, int depth2,
  654     enum AcpiDmarScopeType scope_type)
  655 {
  656         int i, depth;
  657 
  658         if (busno1 != busno2)
  659                 return (0);
  660         if (scope_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && depth1 != depth2)
  661                 return (0);
  662         depth = depth1;
  663         if (depth2 < depth)
  664                 depth = depth2;
  665         for (i = 0; i < depth; i++) {
  666                 if (path1[i].Device != path2[i].Device ||
  667                     path1[i].Function != path2[i].Function)
  668                         return (0);
  669         }
  670         return (1);
  671 }
  672 
  673 static int
  674 dmar_match_devscope(ACPI_DMAR_DEVICE_SCOPE *devscope, device_t dev,
  675     int dev_busno, const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len)
  676 {
  677         ACPI_DMAR_PCI_PATH *path;
  678         int path_len;
  679 
  680         if (devscope->Length < sizeof(*devscope)) {
  681                 printf("dmar_find: corrupted DMAR table, dl %d\n",
  682                     devscope->Length);
  683                 return (-1);
  684         }
  685         if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
  686             devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_BRIDGE)
  687                 return (0);
  688         path_len = devscope->Length - sizeof(*devscope);
  689         if (path_len % 2 != 0) {
  690                 printf("dmar_find_bsf: corrupted DMAR table, dl %d\n",
  691                     devscope->Length);
  692                 return (-1);
  693         }
  694         path_len /= 2;
  695         path = (ACPI_DMAR_PCI_PATH *)(devscope + 1);
  696         if (path_len == 0) {
  697                 printf("dmar_find: corrupted DMAR table, dl %d\n",
  698                     devscope->Length);
  699                 return (-1);
  700         }
  701         if (dmar_match_verbose)
  702                 dmar_print_path(dev, "DMAR", devscope->Bus, path_len, path);
  703 
  704         return (dmar_match_pathes(devscope->Bus, path, path_len, dev_busno,
  705             dev_path, dev_path_len, devscope->EntryType));
  706 }
  707 
  708 struct dmar_unit *
  709 dmar_find(device_t dev)
  710 {
  711         device_t dmar_dev;
  712         ACPI_DMAR_HARDWARE_UNIT *dmarh;
  713         ACPI_DMAR_DEVICE_SCOPE *devscope;
  714         char *ptr, *ptrend;
  715         int i, match, dev_domain, dev_busno, dev_path_len;
  716 
  717         dmar_dev = NULL;
  718         dev_domain = pci_get_domain(dev);
  719         dev_path_len = dmar_dev_depth(dev);
  720         ACPI_DMAR_PCI_PATH dev_path[dev_path_len];
  721         dmar_dev_path(dev, &dev_busno, dev_path, dev_path_len);
  722         if (dmar_match_verbose)
  723                 dmar_print_path(dev, "PCI", dev_busno, dev_path_len, dev_path);
  724 
  725         for (i = 0; i < dmar_devcnt; i++) {
  726                 if (dmar_devs[i] == NULL)
  727                         continue;
  728                 dmarh = dmar_find_by_index(i);
  729                 if (dmarh == NULL)
  730                         continue;
  731                 if (dmarh->Segment != dev_domain)
  732                         continue;
  733                 if ((dmarh->Flags & ACPI_DMAR_INCLUDE_ALL) != 0) {
  734                         dmar_dev = dmar_devs[i];
  735                         if (dmar_match_verbose) {
  736                                 device_printf(dev,
  737                                     "pci%d:%d:%d:%d matched dmar%d INCLUDE_ALL\n",
  738                                     dev_domain, pci_get_bus(dev),
  739                                     pci_get_slot(dev),
  740                                     pci_get_function(dev),
  741                                     ((struct dmar_unit *)device_get_softc(
  742                                     dmar_dev))->unit);
  743                         }
  744                         goto found;
  745                 }
  746                 ptr = (char *)dmarh + sizeof(*dmarh);
  747                 ptrend = (char *)dmarh + dmarh->Header.Length;
  748                 for (;;) {
  749                         if (ptr >= ptrend)
  750                                 break;
  751                         devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
  752                         ptr += devscope->Length;
  753                         if (dmar_match_verbose) {
  754                                 device_printf(dev,
  755                                     "pci%d:%d:%d:%d matching dmar%d\n",
  756                                     dev_domain, pci_get_bus(dev),
  757                                     pci_get_slot(dev),
  758                                     pci_get_function(dev),
  759                                     ((struct dmar_unit *)device_get_softc(
  760                                     dmar_devs[i]))->unit);
  761                         }
  762                         match = dmar_match_devscope(devscope, dev, dev_busno,
  763                             dev_path, dev_path_len);
  764                         if (dmar_match_verbose) {
  765                                 if (match == -1)
  766                                         printf("table error\n");
  767                                 else if (match == 0)
  768                                         printf("not matched\n");
  769                                 else
  770                                         printf("matched\n");
  771                         }
  772                         if (match == -1)
  773                                 return (NULL);
  774                         else if (match == 1) {
  775                                 dmar_dev = dmar_devs[i];
  776                                 goto found;
  777                         }
  778                 }
  779         }
  780         return (NULL);
  781 found:
  782         return (device_get_softc(dmar_dev));
  783 }
  784 
  785 static struct dmar_unit *
  786 dmar_find_nonpci(u_int id, u_int entry_type, uint16_t *rid)
  787 {
  788         device_t dmar_dev;
  789         struct dmar_unit *unit;
  790         ACPI_DMAR_HARDWARE_UNIT *dmarh;
  791         ACPI_DMAR_DEVICE_SCOPE *devscope;
  792         ACPI_DMAR_PCI_PATH *path;
  793         char *ptr, *ptrend;
  794 #ifdef DEV_APIC
  795         int error;
  796 #endif
  797         int i;
  798 
  799         for (i = 0; i < dmar_devcnt; i++) {
  800                 dmar_dev = dmar_devs[i];
  801                 if (dmar_dev == NULL)
  802                         continue;
  803                 unit = (struct dmar_unit *)device_get_softc(dmar_dev);
  804                 dmarh = dmar_find_by_index(i);
  805                 if (dmarh == NULL)
  806                         continue;
  807                 ptr = (char *)dmarh + sizeof(*dmarh);
  808                 ptrend = (char *)dmarh + dmarh->Header.Length;
  809                 for (;;) {
  810                         if (ptr >= ptrend)
  811                                 break;
  812                         devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
  813                         ptr += devscope->Length;
  814                         if (devscope->EntryType != entry_type)
  815                                 continue;
  816                         if (devscope->EnumerationId != id)
  817                                 continue;
  818 #ifdef DEV_APIC
  819                         if (entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) {
  820                                 error = ioapic_get_rid(id, rid);
  821                                 /*
  822                                  * If our IOAPIC has PCI bindings then
  823                                  * use the PCI device rid.
  824                                  */
  825                                 if (error == 0)
  826                                         return (unit);
  827                         }
  828 #endif
  829                         if (devscope->Length - sizeof(ACPI_DMAR_DEVICE_SCOPE)
  830                             == 2) {
  831                                 if (rid != NULL) {
  832                                         path = (ACPI_DMAR_PCI_PATH *)
  833                                             (devscope + 1);
  834                                         *rid = PCI_RID(devscope->Bus,
  835                                             path->Device, path->Function);
  836                                 }
  837                                 return (unit);
  838                         }
  839                         printf(
  840                            "dmar_find_nonpci: id %d type %d path length != 2\n",
  841                             id, entry_type);
  842                         break;
  843                 }
  844         }
  845         return (NULL);
  846 }
  847 
  848 
  849 struct dmar_unit *
  850 dmar_find_hpet(device_t dev, uint16_t *rid)
  851 {
  852 
  853         return (dmar_find_nonpci(hpet_get_uid(dev), ACPI_DMAR_SCOPE_TYPE_HPET,
  854             rid));
  855 }
  856 
  857 struct dmar_unit *
  858 dmar_find_ioapic(u_int apic_id, uint16_t *rid)
  859 {
  860 
  861         return (dmar_find_nonpci(apic_id, ACPI_DMAR_SCOPE_TYPE_IOAPIC, rid));
  862 }
  863 
  864 struct rmrr_iter_args {
  865         struct dmar_domain *domain;
  866         device_t dev;
  867         int dev_domain;
  868         int dev_busno;
  869         ACPI_DMAR_PCI_PATH *dev_path;
  870         int dev_path_len;
  871         struct dmar_map_entries_tailq *rmrr_entries;
  872 };
  873 
  874 static int
  875 dmar_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
  876 {
  877         struct rmrr_iter_args *ria;
  878         ACPI_DMAR_RESERVED_MEMORY *resmem;
  879         ACPI_DMAR_DEVICE_SCOPE *devscope;
  880         struct dmar_map_entry *entry;
  881         char *ptr, *ptrend;
  882         int match;
  883 
  884         if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY)
  885                 return (1);
  886 
  887         ria = arg;
  888         resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh;
  889         if (dmar_match_verbose) {
  890                 printf("RMRR [%jx,%jx] segment %d\n",
  891                     (uintmax_t)resmem->BaseAddress,
  892                     (uintmax_t)resmem->EndAddress,
  893                     resmem->Segment);
  894         }
  895         if (resmem->Segment != ria->dev_domain)
  896                 return (1);
  897 
  898         ptr = (char *)resmem + sizeof(*resmem);
  899         ptrend = (char *)resmem + resmem->Header.Length;
  900         for (;;) {
  901                 if (ptr >= ptrend)
  902                         break;
  903                 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
  904                 ptr += devscope->Length;
  905                 match = dmar_match_devscope(devscope, ria->dev, ria->dev_busno,
  906                     ria->dev_path, ria->dev_path_len);
  907                 if (match == 1) {
  908                         if (dmar_match_verbose)
  909                                 printf("matched\n");
  910                         entry = dmar_gas_alloc_entry(ria->domain,
  911                             DMAR_PGF_WAITOK);
  912                         entry->start = resmem->BaseAddress;
  913                         /* The RMRR entry end address is inclusive. */
  914                         entry->end = resmem->EndAddress;
  915                         TAILQ_INSERT_TAIL(ria->rmrr_entries, entry,
  916                             unroll_link);
  917                 } else if (dmar_match_verbose) {
  918                         printf("not matched, err %d\n", match);
  919                 }
  920         }
  921 
  922         return (1);
  923 }
  924 
  925 void
  926 dmar_dev_parse_rmrr(struct dmar_domain *domain, device_t dev,
  927     struct dmar_map_entries_tailq *rmrr_entries)
  928 {
  929         struct rmrr_iter_args ria;
  930 
  931         ria.dev_domain = pci_get_domain(dev);
  932         ria.dev_path_len = dmar_dev_depth(dev);
  933         ACPI_DMAR_PCI_PATH dev_path[ria.dev_path_len];
  934         dmar_dev_path(dev, &ria.dev_busno, dev_path, ria.dev_path_len);
  935 
  936         if (dmar_match_verbose) {
  937                 device_printf(dev, "parsing RMRR entries for ");
  938                 dmar_print_path(dev, "PCI", ria.dev_busno, ria.dev_path_len,
  939                     dev_path);
  940         }
  941 
  942         ria.domain = domain;
  943         ria.dev = dev;
  944         ria.dev_path = dev_path;
  945         ria.rmrr_entries = rmrr_entries;
  946         dmar_iterate_tbl(dmar_rmrr_iter, &ria);
  947 }
  948 
  949 struct inst_rmrr_iter_args {
  950         struct dmar_unit *dmar;
  951 };
  952 
  953 static device_t
  954 dmar_path_dev(int segment, int path_len, int busno,
  955     const ACPI_DMAR_PCI_PATH *path)
  956 {
  957         devclass_t pci_class;
  958         device_t bus, pcib, dev;
  959         int i;
  960 
  961         pci_class = devclass_find("pci");
  962         dev = NULL;
  963         for (i = 0; i < path_len; i++, path++) {
  964                 dev = pci_find_dbsf(segment, busno, path->Device,
  965                     path->Function);
  966                 if (dev == NULL)
  967                         break;
  968                 if (i != path_len - 1) {
  969                         bus = device_get_parent(dev);
  970                         pcib = device_get_parent(bus);
  971                         if (device_get_devclass(device_get_parent(pcib)) !=
  972                             pci_class)
  973                                 return (NULL);
  974                 }
  975                 busno = pcib_get_bus(dev);
  976         }
  977         return (dev);
  978 }
  979 
  980 static int
  981 dmar_inst_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
  982 {
  983         const ACPI_DMAR_RESERVED_MEMORY *resmem;
  984         const ACPI_DMAR_DEVICE_SCOPE *devscope;
  985         struct inst_rmrr_iter_args *iria;
  986         const char *ptr, *ptrend;
  987         struct dmar_unit *dev_dmar;
  988         device_t dev;
  989 
  990         if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY)
  991                 return (1);
  992 
  993         iria = arg;
  994         resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh;
  995         if (resmem->Segment != iria->dmar->segment)
  996                 return (1);
  997         if (dmar_match_verbose) {
  998                 printf("dmar%d: RMRR [%jx,%jx]\n", iria->dmar->unit,
  999                     (uintmax_t)resmem->BaseAddress,
 1000                     (uintmax_t)resmem->EndAddress);
 1001         }
 1002 
 1003         ptr = (const char *)resmem + sizeof(*resmem);
 1004         ptrend = (const char *)resmem + resmem->Header.Length;
 1005         for (;;) {
 1006                 if (ptr >= ptrend)
 1007                         break;
 1008                 devscope = (const ACPI_DMAR_DEVICE_SCOPE *)ptr;
 1009                 ptr += devscope->Length;
 1010                 /* XXXKIB bridge */
 1011                 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT)
 1012                         continue;
 1013                 if (dmar_match_verbose) {
 1014                         dmar_print_path(iria->dmar->dev, "RMRR scope",
 1015                             devscope->Bus, (devscope->Length -
 1016                             sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2,
 1017                             (const ACPI_DMAR_PCI_PATH *)(devscope + 1));
 1018                 }
 1019                 dev = dmar_path_dev(resmem->Segment, (devscope->Length -
 1020                     sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2, devscope->Bus,
 1021                     (const ACPI_DMAR_PCI_PATH *)(devscope + 1));
 1022                 if (dev == NULL) {
 1023                         if (dmar_match_verbose)
 1024                                 printf("null dev\n");
 1025                         continue;
 1026                 }
 1027                 dev_dmar = dmar_find(dev);
 1028                 if (dev_dmar != iria->dmar) {
 1029                         if (dmar_match_verbose) {
 1030                                 printf("dmar%d matched, skipping\n",
 1031                                     dev_dmar->unit);
 1032                         }
 1033                         continue;
 1034                 }
 1035                 if (dmar_match_verbose)
 1036                         printf("matched, instantiating RMRR context\n");
 1037                 dmar_instantiate_ctx(iria->dmar, dev, true);
 1038         }
 1039 
 1040         return (1);
 1041 
 1042 }
 1043 
 1044 /*
 1045  * Pre-create all contexts for the DMAR which have RMRR entries.
 1046  */
 1047 int
 1048 dmar_instantiate_rmrr_ctxs(struct dmar_unit *dmar)
 1049 {
 1050         struct inst_rmrr_iter_args iria;
 1051         int error;
 1052 
 1053         if (!dmar_barrier_enter(dmar, DMAR_BARRIER_RMRR))
 1054                 return (0);
 1055 
 1056         error = 0;
 1057         iria.dmar = dmar;
 1058         if (dmar_match_verbose)
 1059                 printf("dmar%d: instantiating RMRR contexts\n", dmar->unit);
 1060         dmar_iterate_tbl(dmar_inst_rmrr_iter, &iria);
 1061         DMAR_LOCK(dmar);
 1062         if (!LIST_EMPTY(&dmar->domains)) {
 1063                 KASSERT((dmar->hw_gcmd & DMAR_GCMD_TE) == 0,
 1064             ("dmar%d: RMRR not handled but translation is already enabled",
 1065                     dmar->unit));
 1066                 error = dmar_enable_translation(dmar);
 1067         }
 1068         dmar_barrier_exit(dmar, DMAR_BARRIER_RMRR);
 1069         return (error);
 1070 }
 1071 
 1072 #ifdef DDB
 1073 #include <ddb/ddb.h>
 1074 #include <ddb/db_lex.h>
 1075 
 1076 static void
 1077 dmar_print_domain_entry(const struct dmar_map_entry *entry)
 1078 {
 1079         struct dmar_map_entry *l, *r;
 1080 
 1081         db_printf(
 1082             "    start %jx end %jx free_after %jx free_down %jx flags %x ",
 1083             entry->start, entry->end, entry->free_after, entry->free_down,
 1084             entry->flags);
 1085         db_printf("left ");
 1086         l = RB_LEFT(entry, rb_entry);
 1087         if (l == NULL)
 1088                 db_printf("NULL ");
 1089         else
 1090                 db_printf("%jx ", l->start);
 1091         db_printf("right ");
 1092         r = RB_RIGHT(entry, rb_entry);
 1093         if (r == NULL)
 1094                 db_printf("NULL");
 1095         else
 1096                 db_printf("%jx", r->start);
 1097         db_printf("\n");
 1098 }
 1099 
 1100 static void
 1101 dmar_print_ctx(struct dmar_ctx *ctx)
 1102 {
 1103 
 1104         db_printf(
 1105             "    @%p pci%d:%d:%d refs %d flags %x loads %lu unloads %lu\n",
 1106             ctx, pci_get_bus(ctx->ctx_tag.owner),
 1107             pci_get_slot(ctx->ctx_tag.owner),
 1108             pci_get_function(ctx->ctx_tag.owner), ctx->refs, ctx->flags,
 1109             ctx->loads, ctx->unloads);
 1110 }
 1111 
 1112 static void
 1113 dmar_print_domain(struct dmar_domain *domain, bool show_mappings)
 1114 {
 1115         struct dmar_map_entry *entry;
 1116         struct dmar_ctx *ctx;
 1117 
 1118         db_printf(
 1119             "  @%p dom %d mgaw %d agaw %d pglvl %d end %jx refs %d\n"
 1120             "   ctx_cnt %d flags %x pgobj %p map_ents %u\n",
 1121             domain, domain->domain, domain->mgaw, domain->agaw, domain->pglvl,
 1122             (uintmax_t)domain->end, domain->refs, domain->ctx_cnt,
 1123             domain->flags, domain->pgtbl_obj, domain->entries_cnt);
 1124         if (!LIST_EMPTY(&domain->contexts)) {
 1125                 db_printf("  Contexts:\n");
 1126                 LIST_FOREACH(ctx, &domain->contexts, link)
 1127                         dmar_print_ctx(ctx);
 1128         }
 1129         if (!show_mappings)
 1130                 return;
 1131         db_printf("    mapped:\n");
 1132         RB_FOREACH(entry, dmar_gas_entries_tree, &domain->rb_root) {
 1133                 dmar_print_domain_entry(entry);
 1134                 if (db_pager_quit)
 1135                         break;
 1136         }
 1137         if (db_pager_quit)
 1138                 return;
 1139         db_printf("    unloading:\n");
 1140         TAILQ_FOREACH(entry, &domain->unload_entries, dmamap_link) {
 1141                 dmar_print_domain_entry(entry);
 1142                 if (db_pager_quit)
 1143                         break;
 1144         }
 1145 }
 1146 
 1147 DB_FUNC(dmar_domain, db_dmar_print_domain, db_show_table, CS_OWN, NULL)
 1148 {
 1149         struct dmar_unit *unit;
 1150         struct dmar_domain *domain;
 1151         struct dmar_ctx *ctx;
 1152         bool show_mappings, valid;
 1153         int pci_domain, bus, device, function, i, t;
 1154         db_expr_t radix;
 1155 
 1156         valid = false;
 1157         radix = db_radix;
 1158         db_radix = 10;
 1159         t = db_read_token();
 1160         if (t == tSLASH) {
 1161                 t = db_read_token();
 1162                 if (t != tIDENT) {
 1163                         db_printf("Bad modifier\n");
 1164                         db_radix = radix;
 1165                         db_skip_to_eol();
 1166                         return;
 1167                 }
 1168                 show_mappings = strchr(db_tok_string, 'm') != NULL;
 1169                 t = db_read_token();
 1170         } else {
 1171                 show_mappings = false;
 1172         }
 1173         if (t == tNUMBER) {
 1174                 pci_domain = db_tok_number;
 1175                 t = db_read_token();
 1176                 if (t == tNUMBER) {
 1177                         bus = db_tok_number;
 1178                         t = db_read_token();
 1179                         if (t == tNUMBER) {
 1180                                 device = db_tok_number;
 1181                                 t = db_read_token();
 1182                                 if (t == tNUMBER) {
 1183                                         function = db_tok_number;
 1184                                         valid = true;
 1185                                 }
 1186                         }
 1187                 }
 1188         }
 1189                         db_radix = radix;
 1190         db_skip_to_eol();
 1191         if (!valid) {
 1192                 db_printf("usage: show dmar_domain [/m] "
 1193                     "<domain> <bus> <device> <func>\n");
 1194                 return;
 1195         }
 1196         for (i = 0; i < dmar_devcnt; i++) {
 1197                 unit = device_get_softc(dmar_devs[i]);
 1198                 LIST_FOREACH(domain, &unit->domains, link) {
 1199                         LIST_FOREACH(ctx, &domain->contexts, link) {
 1200                                 if (pci_domain == unit->segment && 
 1201                                     bus == pci_get_bus(ctx->ctx_tag.owner) &&
 1202                                     device ==
 1203                                     pci_get_slot(ctx->ctx_tag.owner) &&
 1204                                     function ==
 1205                                     pci_get_function(ctx->ctx_tag.owner)) {
 1206                                         dmar_print_domain(domain,
 1207                                             show_mappings);
 1208                                         goto out;
 1209                                 }
 1210                         }
 1211                 }
 1212         }
 1213 out:;
 1214 }
 1215 
 1216 static void
 1217 dmar_print_one(int idx, bool show_domains, bool show_mappings)
 1218 {
 1219         struct dmar_unit *unit;
 1220         struct dmar_domain *domain;
 1221         int i, frir;
 1222 
 1223         unit = device_get_softc(dmar_devs[idx]);
 1224         db_printf("dmar%d at %p, root at 0x%jx, ver 0x%x\n", unit->unit, unit,
 1225             dmar_read8(unit, DMAR_RTADDR_REG), dmar_read4(unit, DMAR_VER_REG));
 1226         db_printf("cap 0x%jx ecap 0x%jx gsts 0x%x fsts 0x%x fectl 0x%x\n",
 1227             (uintmax_t)dmar_read8(unit, DMAR_CAP_REG),
 1228             (uintmax_t)dmar_read8(unit, DMAR_ECAP_REG),
 1229             dmar_read4(unit, DMAR_GSTS_REG),
 1230             dmar_read4(unit, DMAR_FSTS_REG),
 1231             dmar_read4(unit, DMAR_FECTL_REG));
 1232         if (unit->ir_enabled) {
 1233                 db_printf("ir is enabled; IRT @%p phys 0x%jx maxcnt %d\n",
 1234                     unit->irt, (uintmax_t)unit->irt_phys, unit->irte_cnt);
 1235         }
 1236         db_printf("fed 0x%x fea 0x%x feua 0x%x\n",
 1237             dmar_read4(unit, DMAR_FEDATA_REG),
 1238             dmar_read4(unit, DMAR_FEADDR_REG),
 1239             dmar_read4(unit, DMAR_FEUADDR_REG));
 1240         db_printf("primary fault log:\n");
 1241         for (i = 0; i < DMAR_CAP_NFR(unit->hw_cap); i++) {
 1242                 frir = (DMAR_CAP_FRO(unit->hw_cap) + i) * 16;
 1243                 db_printf("  %d at 0x%x: %jx %jx\n", i, frir,
 1244                     (uintmax_t)dmar_read8(unit, frir),
 1245                     (uintmax_t)dmar_read8(unit, frir + 8));
 1246         }
 1247         if (DMAR_HAS_QI(unit)) {
 1248                 db_printf("ied 0x%x iea 0x%x ieua 0x%x\n",
 1249                     dmar_read4(unit, DMAR_IEDATA_REG),
 1250                     dmar_read4(unit, DMAR_IEADDR_REG),
 1251                     dmar_read4(unit, DMAR_IEUADDR_REG));
 1252                 if (unit->qi_enabled) {
 1253                         db_printf("qi is enabled: queue @0x%jx (IQA 0x%jx) "
 1254                             "size 0x%jx\n"
 1255                     "  head 0x%x tail 0x%x avail 0x%x status 0x%x ctrl 0x%x\n"
 1256                     "  hw compl 0x%x@%p/phys@%jx next seq 0x%x gen 0x%x\n",
 1257                             (uintmax_t)unit->inv_queue,
 1258                             (uintmax_t)dmar_read8(unit, DMAR_IQA_REG),
 1259                             (uintmax_t)unit->inv_queue_size,
 1260                             dmar_read4(unit, DMAR_IQH_REG),
 1261                             dmar_read4(unit, DMAR_IQT_REG),
 1262                             unit->inv_queue_avail,
 1263                             dmar_read4(unit, DMAR_ICS_REG),
 1264                             dmar_read4(unit, DMAR_IECTL_REG),
 1265                             unit->inv_waitd_seq_hw,
 1266                             &unit->inv_waitd_seq_hw,
 1267                             (uintmax_t)unit->inv_waitd_seq_hw_phys,
 1268                             unit->inv_waitd_seq,
 1269                             unit->inv_waitd_gen);
 1270                 } else {
 1271                         db_printf("qi is disabled\n");
 1272                 }
 1273         }
 1274         if (show_domains) {
 1275                 db_printf("domains:\n");
 1276                 LIST_FOREACH(domain, &unit->domains, link) {
 1277                         dmar_print_domain(domain, show_mappings);
 1278                         if (db_pager_quit)
 1279                                 break;
 1280                 }
 1281         }
 1282 }
 1283 
 1284 DB_SHOW_COMMAND(dmar, db_dmar_print)
 1285 {
 1286         bool show_domains, show_mappings;
 1287 
 1288         show_domains = strchr(modif, 'd') != NULL;
 1289         show_mappings = strchr(modif, 'm') != NULL;
 1290         if (!have_addr) {
 1291                 db_printf("usage: show dmar [/d] [/m] index\n");
 1292                 return;
 1293         }
 1294         dmar_print_one((int)addr, show_domains, show_mappings);
 1295 }
 1296 
 1297 DB_SHOW_ALL_COMMAND(dmars, db_show_all_dmars)
 1298 {
 1299         int i;
 1300         bool show_domains, show_mappings;
 1301 
 1302         show_domains = strchr(modif, 'd') != NULL;
 1303         show_mappings = strchr(modif, 'm') != NULL;
 1304 
 1305         for (i = 0; i < dmar_devcnt; i++) {
 1306                 dmar_print_one(i, show_domains, show_mappings);
 1307                 if (db_pager_quit)
 1308                         break;
 1309         }
 1310 }
 1311 #endif

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