The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/x86/iommu/intel_drv.c

Version: -  FREEBSD  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-2  -  FREEBSD-11-1  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-4  -  FREEBSD-10-3  -  FREEBSD-10-2  -  FREEBSD-10-1  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-3  -  FREEBSD-9-2  -  FREEBSD-9-1  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-4  -  FREEBSD-8-3  -  FREEBSD-8-2  -  FREEBSD-8-1  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-4  -  FREEBSD-7-3  -  FREEBSD-7-2  -  FREEBSD-7-1  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-4  -  FREEBSD-6-3  -  FREEBSD-6-2  -  FREEBSD-6-1  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-5  -  FREEBSD-5-4  -  FREEBSD-5-3  -  FREEBSD-5-2  -  FREEBSD-5-1  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  linux-2.6  -  linux-2.4.22  -  MK83  -  MK84  -  PLAN9  -  DFBSD  -  NETBSD  -  NETBSD5  -  NETBSD4  -  NETBSD3  -  NETBSD20  -  OPENBSD  -  xnu-517  -  xnu-792  -  xnu-792.6.70  -  xnu-1228  -  xnu-1456.1.26  -  xnu-1699.24.8  -  xnu-2050.18.24  -  OPENSOLARIS  -  minix-3-1-1 
SearchContext: -  none  -  3  -  10 

    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2013-2015 The FreeBSD Foundation
    5  * All rights reserved.
    6  *
    7  * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
    8  * under sponsorship from the FreeBSD Foundation.
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  *
   19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   22  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   29  * SUCH DAMAGE.
   30  */
   31 
   32 #include <sys/cdefs.h>
   33 __FBSDID("$FreeBSD: stable/12/sys/x86/iommu/intel_drv.c 355086 2019-11-25 09:43:36Z kib $");
   34 
   35 #include "opt_acpi.h"
   36 #if defined(__amd64__)
   37 #define DEV_APIC
   38 #else
   39 #include "opt_apic.h"
   40 #endif
   41 #include "opt_ddb.h"
   42 
   43 #include <sys/param.h>
   44 #include <sys/bus.h>
   45 #include <sys/kernel.h>
   46 #include <sys/lock.h>
   47 #include <sys/malloc.h>
   48 #include <sys/memdesc.h>
   49 #include <sys/module.h>
   50 #include <sys/rman.h>
   51 #include <sys/rwlock.h>
   52 #include <sys/smp.h>
   53 #include <sys/taskqueue.h>
   54 #include <sys/tree.h>
   55 #include <sys/vmem.h>
   56 #include <machine/bus.h>
   57 #include <machine/pci_cfgreg.h>
   58 #include <contrib/dev/acpica/include/acpi.h>
   59 #include <contrib/dev/acpica/include/accommon.h>
   60 #include <dev/acpica/acpivar.h>
   61 #include <vm/vm.h>
   62 #include <vm/vm_extern.h>
   63 #include <vm/vm_kern.h>
   64 #include <vm/vm_object.h>
   65 #include <vm/vm_page.h>
   66 #include <vm/vm_pager.h>
   67 #include <vm/vm_map.h>
   68 #include <x86/include/busdma_impl.h>
   69 #include <x86/iommu/intel_reg.h>
   70 #include <x86/iommu/busdma_dmar.h>
   71 #include <dev/pci/pcireg.h>
   72 #include <dev/pci/pcivar.h>
   73 #include <x86/iommu/intel_dmar.h>
   74 
   75 #ifdef DEV_APIC
   76 #include "pcib_if.h"
   77 #include <machine/intr_machdep.h>
   78 #include <x86/apicreg.h>
   79 #include <x86/apicvar.h>
   80 #endif
   81 
   82 #define DMAR_FAULT_IRQ_RID      0
   83 #define DMAR_QI_IRQ_RID         1
   84 #define DMAR_REG_RID            2
   85 
   86 static devclass_t dmar_devclass;
   87 static device_t *dmar_devs;
   88 static int dmar_devcnt;
   89 
   90 typedef int (*dmar_iter_t)(ACPI_DMAR_HEADER *, void *);
   91 
   92 static void
   93 dmar_iterate_tbl(dmar_iter_t iter, void *arg)
   94 {
   95         ACPI_TABLE_DMAR *dmartbl;
   96         ACPI_DMAR_HEADER *dmarh;
   97         char *ptr, *ptrend;
   98         ACPI_STATUS status;
   99 
  100         status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl);
  101         if (ACPI_FAILURE(status))
  102                 return;
  103         ptr = (char *)dmartbl + sizeof(*dmartbl);
  104         ptrend = (char *)dmartbl + dmartbl->Header.Length;
  105         for (;;) {
  106                 if (ptr >= ptrend)
  107                         break;
  108                 dmarh = (ACPI_DMAR_HEADER *)ptr;
  109                 if (dmarh->Length <= 0) {
  110                         printf("dmar_identify: corrupted DMAR table, l %d\n",
  111                             dmarh->Length);
  112                         break;
  113                 }
  114                 ptr += dmarh->Length;
  115                 if (!iter(dmarh, arg))
  116                         break;
  117         }
  118         AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl);
  119 }
  120 
  121 struct find_iter_args {
  122         int i;
  123         ACPI_DMAR_HARDWARE_UNIT *res;
  124 };
  125 
  126 static int
  127 dmar_find_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
  128 {
  129         struct find_iter_args *fia;
  130 
  131         if (dmarh->Type != ACPI_DMAR_TYPE_HARDWARE_UNIT)
  132                 return (1);
  133 
  134         fia = arg;
  135         if (fia->i == 0) {
  136                 fia->res = (ACPI_DMAR_HARDWARE_UNIT *)dmarh;
  137                 return (0);
  138         }
  139         fia->i--;
  140         return (1);
  141 }
  142 
  143 static ACPI_DMAR_HARDWARE_UNIT *
  144 dmar_find_by_index(int idx)
  145 {
  146         struct find_iter_args fia;
  147 
  148         fia.i = idx;
  149         fia.res = NULL;
  150         dmar_iterate_tbl(dmar_find_iter, &fia);
  151         return (fia.res);
  152 }
  153 
  154 static int
  155 dmar_count_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
  156 {
  157 
  158         if (dmarh->Type == ACPI_DMAR_TYPE_HARDWARE_UNIT)
  159                 dmar_devcnt++;
  160         return (1);
  161 }
  162 
  163 static int dmar_enable = 0;
  164 static void
  165 dmar_identify(driver_t *driver, device_t parent)
  166 {
  167         ACPI_TABLE_DMAR *dmartbl;
  168         ACPI_DMAR_HARDWARE_UNIT *dmarh;
  169         ACPI_STATUS status;
  170         int i, error;
  171 
  172         if (acpi_disabled("dmar"))
  173                 return;
  174         TUNABLE_INT_FETCH("hw.dmar.enable", &dmar_enable);
  175         if (!dmar_enable)
  176                 return;
  177 #ifdef INVARIANTS
  178         TUNABLE_INT_FETCH("hw.dmar.check_free", &dmar_check_free);
  179 #endif
  180         status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl);
  181         if (ACPI_FAILURE(status))
  182                 return;
  183         haw = dmartbl->Width + 1;
  184         if ((1ULL << (haw + 1)) > BUS_SPACE_MAXADDR)
  185                 dmar_high = BUS_SPACE_MAXADDR;
  186         else
  187                 dmar_high = 1ULL << (haw + 1);
  188         if (bootverbose) {
  189                 printf("DMAR HAW=%d flags=<%b>\n", dmartbl->Width,
  190                     (unsigned)dmartbl->Flags,
  191                     "\020\001INTR_REMAP\002X2APIC_OPT_OUT");
  192         }
  193         AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl);
  194 
  195         dmar_iterate_tbl(dmar_count_iter, NULL);
  196         if (dmar_devcnt == 0)
  197                 return;
  198         dmar_devs = malloc(sizeof(device_t) * dmar_devcnt, M_DEVBUF,
  199             M_WAITOK | M_ZERO);
  200         for (i = 0; i < dmar_devcnt; i++) {
  201                 dmarh = dmar_find_by_index(i);
  202                 if (dmarh == NULL) {
  203                         printf("dmar_identify: cannot find HWUNIT %d\n", i);
  204                         continue;
  205                 }
  206                 dmar_devs[i] = BUS_ADD_CHILD(parent, 1, "dmar", i);
  207                 if (dmar_devs[i] == NULL) {
  208                         printf("dmar_identify: cannot create instance %d\n", i);
  209                         continue;
  210                 }
  211                 error = bus_set_resource(dmar_devs[i], SYS_RES_MEMORY,
  212                     DMAR_REG_RID, dmarh->Address, PAGE_SIZE);
  213                 if (error != 0) {
  214                         printf(
  215         "dmar%d: unable to alloc register window at 0x%08jx: error %d\n",
  216                             i, (uintmax_t)dmarh->Address, error);
  217                         device_delete_child(parent, dmar_devs[i]);
  218                         dmar_devs[i] = NULL;
  219                 }
  220         }
  221 }
  222 
  223 static int
  224 dmar_probe(device_t dev)
  225 {
  226 
  227         if (acpi_get_handle(dev) != NULL)
  228                 return (ENXIO);
  229         device_set_desc(dev, "DMA remap");
  230         return (BUS_PROBE_NOWILDCARD);
  231 }
  232 
  233 static void
  234 dmar_release_intr(device_t dev, struct dmar_unit *unit, int idx)
  235 {
  236         struct dmar_msi_data *dmd;
  237 
  238         dmd = &unit->intrs[idx];
  239         if (dmd->irq == -1)
  240                 return;
  241         bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle);
  242         bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res);
  243         bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid);
  244         PCIB_RELEASE_MSIX(device_get_parent(device_get_parent(dev)),
  245             dev, dmd->irq);
  246         dmd->irq = -1;
  247 }
  248 
  249 static void
  250 dmar_release_resources(device_t dev, struct dmar_unit *unit)
  251 {
  252         int i;
  253 
  254         dmar_fini_busdma(unit);
  255         dmar_fini_irt(unit);
  256         dmar_fini_qi(unit);
  257         dmar_fini_fault_log(unit);
  258         for (i = 0; i < DMAR_INTR_TOTAL; i++)
  259                 dmar_release_intr(dev, unit, i);
  260         if (unit->regs != NULL) {
  261                 bus_deactivate_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
  262                     unit->regs);
  263                 bus_release_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
  264                     unit->regs);
  265                 unit->regs = NULL;
  266         }
  267         if (unit->domids != NULL) {
  268                 delete_unrhdr(unit->domids);
  269                 unit->domids = NULL;
  270         }
  271         if (unit->ctx_obj != NULL) {
  272                 vm_object_deallocate(unit->ctx_obj);
  273                 unit->ctx_obj = NULL;
  274         }
  275 }
  276 
  277 static int
  278 dmar_alloc_irq(device_t dev, struct dmar_unit *unit, int idx)
  279 {
  280         device_t pcib;
  281         struct dmar_msi_data *dmd;
  282         uint64_t msi_addr;
  283         uint32_t msi_data;
  284         int error;
  285 
  286         dmd = &unit->intrs[idx];
  287         pcib = device_get_parent(device_get_parent(dev)); /* Really not pcib */
  288         error = PCIB_ALLOC_MSIX(pcib, dev, &dmd->irq);
  289         if (error != 0) {
  290                 device_printf(dev, "cannot allocate %s interrupt, %d\n",
  291                     dmd->name, error);
  292                 goto err1;
  293         }
  294         error = bus_set_resource(dev, SYS_RES_IRQ, dmd->irq_rid,
  295             dmd->irq, 1);
  296         if (error != 0) {
  297                 device_printf(dev, "cannot set %s interrupt resource, %d\n",
  298                     dmd->name, error);
  299                 goto err2;
  300         }
  301         dmd->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
  302             &dmd->irq_rid, RF_ACTIVE);
  303         if (dmd->irq_res == NULL) {
  304                 device_printf(dev,
  305                     "cannot allocate resource for %s interrupt\n", dmd->name);
  306                 error = ENXIO;
  307                 goto err3;
  308         }
  309         error = bus_setup_intr(dev, dmd->irq_res, INTR_TYPE_MISC,
  310             dmd->handler, NULL, unit, &dmd->intr_handle);
  311         if (error != 0) {
  312                 device_printf(dev, "cannot setup %s interrupt, %d\n",
  313                     dmd->name, error);
  314                 goto err4;
  315         }
  316         bus_describe_intr(dev, dmd->irq_res, dmd->intr_handle, "%s", dmd->name);
  317         error = PCIB_MAP_MSI(pcib, dev, dmd->irq, &msi_addr, &msi_data);
  318         if (error != 0) {
  319                 device_printf(dev, "cannot map %s interrupt, %d\n",
  320                     dmd->name, error);
  321                 goto err5;
  322         }
  323         dmar_write4(unit, dmd->msi_data_reg, msi_data);
  324         dmar_write4(unit, dmd->msi_addr_reg, msi_addr);
  325         /* Only for xAPIC mode */
  326         dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32);
  327         return (0);
  328 
  329 err5:
  330         bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle);
  331 err4:
  332         bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res);
  333 err3:
  334         bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid);
  335 err2:
  336         PCIB_RELEASE_MSIX(pcib, dev, dmd->irq);
  337         dmd->irq = -1;
  338 err1:
  339         return (error);
  340 }
  341 
  342 #ifdef DEV_APIC
  343 static int
  344 dmar_remap_intr(device_t dev, device_t child, u_int irq)
  345 {
  346         struct dmar_unit *unit;
  347         struct dmar_msi_data *dmd;
  348         uint64_t msi_addr;
  349         uint32_t msi_data;
  350         int i, error;
  351 
  352         unit = device_get_softc(dev);
  353         for (i = 0; i < DMAR_INTR_TOTAL; i++) {
  354                 dmd = &unit->intrs[i];
  355                 if (irq == dmd->irq) {
  356                         error = PCIB_MAP_MSI(device_get_parent(
  357                             device_get_parent(dev)),
  358                             dev, irq, &msi_addr, &msi_data);
  359                         if (error != 0)
  360                                 return (error);
  361                         DMAR_LOCK(unit);
  362                         (dmd->disable_intr)(unit);
  363                         dmar_write4(unit, dmd->msi_data_reg, msi_data);
  364                         dmar_write4(unit, dmd->msi_addr_reg, msi_addr);
  365                         dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32);
  366                         (dmd->enable_intr)(unit);
  367                         DMAR_UNLOCK(unit);
  368                         return (0);
  369                 }
  370         }
  371         return (ENOENT);
  372 }
  373 #endif
  374 
  375 static void
  376 dmar_print_caps(device_t dev, struct dmar_unit *unit,
  377     ACPI_DMAR_HARDWARE_UNIT *dmaru)
  378 {
  379         uint32_t caphi, ecaphi;
  380 
  381         device_printf(dev, "regs@0x%08jx, ver=%d.%d, seg=%d, flags=<%b>\n",
  382             (uintmax_t)dmaru->Address, DMAR_MAJOR_VER(unit->hw_ver),
  383             DMAR_MINOR_VER(unit->hw_ver), dmaru->Segment,
  384             dmaru->Flags, "\020\001INCLUDE_ALL_PCI");
  385         caphi = unit->hw_cap >> 32;
  386         device_printf(dev, "cap=%b,", (u_int)unit->hw_cap,
  387             "\020\004AFL\005WBF\006PLMR\007PHMR\010CM\027ZLR\030ISOCH");
  388         printf("%b, ", caphi, "\020\010PSI\027DWD\030DRD\031FL1GP\034PSI");
  389         printf("ndoms=%d, sagaw=%d, mgaw=%d, fro=%d, nfr=%d, superp=%d",
  390             DMAR_CAP_ND(unit->hw_cap), DMAR_CAP_SAGAW(unit->hw_cap),
  391             DMAR_CAP_MGAW(unit->hw_cap), DMAR_CAP_FRO(unit->hw_cap),
  392             DMAR_CAP_NFR(unit->hw_cap), DMAR_CAP_SPS(unit->hw_cap));
  393         if ((unit->hw_cap & DMAR_CAP_PSI) != 0)
  394                 printf(", mamv=%d", DMAR_CAP_MAMV(unit->hw_cap));
  395         printf("\n");
  396         ecaphi = unit->hw_ecap >> 32;
  397         device_printf(dev, "ecap=%b,", (u_int)unit->hw_ecap,
  398             "\020\001C\002QI\003DI\004IR\005EIM\007PT\010SC\031ECS\032MTS"
  399             "\033NEST\034DIS\035PASID\036PRS\037ERS\040SRS");
  400         printf("%b, ", ecaphi, "\020\002NWFS\003EAFS");
  401         printf("mhmw=%d, iro=%d\n", DMAR_ECAP_MHMV(unit->hw_ecap),
  402             DMAR_ECAP_IRO(unit->hw_ecap));
  403 }
  404 
  405 static int
  406 dmar_attach(device_t dev)
  407 {
  408         struct dmar_unit *unit;
  409         ACPI_DMAR_HARDWARE_UNIT *dmaru;
  410         uint64_t timeout;
  411         int i, error;
  412 
  413         unit = device_get_softc(dev);
  414         unit->dev = dev;
  415         unit->unit = device_get_unit(dev);
  416         dmaru = dmar_find_by_index(unit->unit);
  417         if (dmaru == NULL)
  418                 return (EINVAL);
  419         unit->segment = dmaru->Segment;
  420         unit->base = dmaru->Address;
  421         unit->reg_rid = DMAR_REG_RID;
  422         unit->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
  423             &unit->reg_rid, RF_ACTIVE);
  424         if (unit->regs == NULL) {
  425                 device_printf(dev, "cannot allocate register window\n");
  426                 return (ENOMEM);
  427         }
  428         unit->hw_ver = dmar_read4(unit, DMAR_VER_REG);
  429         unit->hw_cap = dmar_read8(unit, DMAR_CAP_REG);
  430         unit->hw_ecap = dmar_read8(unit, DMAR_ECAP_REG);
  431         if (bootverbose)
  432                 dmar_print_caps(dev, unit, dmaru);
  433         dmar_quirks_post_ident(unit);
  434 
  435         timeout = dmar_get_timeout();
  436         TUNABLE_UINT64_FETCH("hw.dmar.timeout", &timeout);
  437         dmar_update_timeout(timeout);
  438 
  439         for (i = 0; i < DMAR_INTR_TOTAL; i++)
  440                 unit->intrs[i].irq = -1;
  441 
  442         unit->intrs[DMAR_INTR_FAULT].name = "fault";
  443         unit->intrs[DMAR_INTR_FAULT].irq_rid = DMAR_FAULT_IRQ_RID;
  444         unit->intrs[DMAR_INTR_FAULT].handler = dmar_fault_intr;
  445         unit->intrs[DMAR_INTR_FAULT].msi_data_reg = DMAR_FEDATA_REG;
  446         unit->intrs[DMAR_INTR_FAULT].msi_addr_reg = DMAR_FEADDR_REG;
  447         unit->intrs[DMAR_INTR_FAULT].msi_uaddr_reg = DMAR_FEUADDR_REG;
  448         unit->intrs[DMAR_INTR_FAULT].enable_intr = dmar_enable_fault_intr;
  449         unit->intrs[DMAR_INTR_FAULT].disable_intr = dmar_disable_fault_intr;
  450         error = dmar_alloc_irq(dev, unit, DMAR_INTR_FAULT);
  451         if (error != 0) {
  452                 dmar_release_resources(dev, unit);
  453                 return (error);
  454         }
  455         if (DMAR_HAS_QI(unit)) {
  456                 unit->intrs[DMAR_INTR_QI].name = "qi";
  457                 unit->intrs[DMAR_INTR_QI].irq_rid = DMAR_QI_IRQ_RID;
  458                 unit->intrs[DMAR_INTR_QI].handler = dmar_qi_intr;
  459                 unit->intrs[DMAR_INTR_QI].msi_data_reg = DMAR_IEDATA_REG;
  460                 unit->intrs[DMAR_INTR_QI].msi_addr_reg = DMAR_IEADDR_REG;
  461                 unit->intrs[DMAR_INTR_QI].msi_uaddr_reg = DMAR_IEUADDR_REG;
  462                 unit->intrs[DMAR_INTR_QI].enable_intr = dmar_enable_qi_intr;
  463                 unit->intrs[DMAR_INTR_QI].disable_intr = dmar_disable_qi_intr;
  464                 error = dmar_alloc_irq(dev, unit, DMAR_INTR_QI);
  465                 if (error != 0) {
  466                         dmar_release_resources(dev, unit);
  467                         return (error);
  468                 }
  469         }
  470 
  471         mtx_init(&unit->lock, "dmarhw", NULL, MTX_DEF);
  472         unit->domids = new_unrhdr(0, dmar_nd2mask(DMAR_CAP_ND(unit->hw_cap)),
  473             &unit->lock);
  474         LIST_INIT(&unit->domains);
  475 
  476         /*
  477          * 9.2 "Context Entry":
  478          * When Caching Mode (CM) field is reported as Set, the
  479          * domain-id value of zero is architecturally reserved.
  480          * Software must not use domain-id value of zero
  481          * when CM is Set.
  482          */
  483         if ((unit->hw_cap & DMAR_CAP_CM) != 0)
  484                 alloc_unr_specific(unit->domids, 0);
  485 
  486         unit->ctx_obj = vm_pager_allocate(OBJT_PHYS, NULL, IDX_TO_OFF(1 +
  487             DMAR_CTX_CNT), 0, 0, NULL);
  488 
  489         /*
  490          * Allocate and load the root entry table pointer.  Enable the
  491          * address translation after the required invalidations are
  492          * done.
  493          */
  494         dmar_pgalloc(unit->ctx_obj, 0, DMAR_PGF_WAITOK | DMAR_PGF_ZERO);
  495         DMAR_LOCK(unit);
  496         error = dmar_load_root_entry_ptr(unit);
  497         if (error != 0) {
  498                 DMAR_UNLOCK(unit);
  499                 dmar_release_resources(dev, unit);
  500                 return (error);
  501         }
  502         error = dmar_inv_ctx_glob(unit);
  503         if (error != 0) {
  504                 DMAR_UNLOCK(unit);
  505                 dmar_release_resources(dev, unit);
  506                 return (error);
  507         }
  508         if ((unit->hw_ecap & DMAR_ECAP_DI) != 0) {
  509                 error = dmar_inv_iotlb_glob(unit);
  510                 if (error != 0) {
  511                         DMAR_UNLOCK(unit);
  512                         dmar_release_resources(dev, unit);
  513                         return (error);
  514                 }
  515         }
  516 
  517         DMAR_UNLOCK(unit);
  518         error = dmar_init_fault_log(unit);
  519         if (error != 0) {
  520                 dmar_release_resources(dev, unit);
  521                 return (error);
  522         }
  523         error = dmar_init_qi(unit);
  524         if (error != 0) {
  525                 dmar_release_resources(dev, unit);
  526                 return (error);
  527         }
  528         error = dmar_init_irt(unit);
  529         if (error != 0) {
  530                 dmar_release_resources(dev, unit);
  531                 return (error);
  532         }
  533         error = dmar_init_busdma(unit);
  534         if (error != 0) {
  535                 dmar_release_resources(dev, unit);
  536                 return (error);
  537         }
  538 
  539 #ifdef NOTYET
  540         DMAR_LOCK(unit);
  541         error = dmar_enable_translation(unit);
  542         if (error != 0) {
  543                 DMAR_UNLOCK(unit);
  544                 dmar_release_resources(dev, unit);
  545                 return (error);
  546         }
  547         DMAR_UNLOCK(unit);
  548 #endif
  549 
  550         return (0);
  551 }
  552 
  553 static int
  554 dmar_detach(device_t dev)
  555 {
  556 
  557         return (EBUSY);
  558 }
  559 
  560 static int
  561 dmar_suspend(device_t dev)
  562 {
  563 
  564         return (0);
  565 }
  566 
  567 static int
  568 dmar_resume(device_t dev)
  569 {
  570 
  571         /* XXXKIB */
  572         return (0);
  573 }
  574 
  575 static device_method_t dmar_methods[] = {
  576         DEVMETHOD(device_identify, dmar_identify),
  577         DEVMETHOD(device_probe, dmar_probe),
  578         DEVMETHOD(device_attach, dmar_attach),
  579         DEVMETHOD(device_detach, dmar_detach),
  580         DEVMETHOD(device_suspend, dmar_suspend),
  581         DEVMETHOD(device_resume, dmar_resume),
  582 #ifdef DEV_APIC
  583         DEVMETHOD(bus_remap_intr, dmar_remap_intr),
  584 #endif
  585         DEVMETHOD_END
  586 };
  587 
  588 static driver_t dmar_driver = {
  589         "dmar",
  590         dmar_methods,
  591         sizeof(struct dmar_unit),
  592 };
  593 
  594 DRIVER_MODULE(dmar, acpi, dmar_driver, dmar_devclass, 0, 0);
  595 MODULE_DEPEND(dmar, acpi, 1, 1, 1);
  596 
  597 void
  598 dmar_set_buswide_ctx(struct dmar_unit *unit, u_int busno)
  599 {
  600 
  601         MPASS(busno <= PCI_BUSMAX);
  602         DMAR_LOCK(unit);
  603         unit->buswide_ctxs[busno / NBBY / sizeof(uint32_t)] |=
  604             1 << (busno % (NBBY * sizeof(uint32_t)));
  605         DMAR_UNLOCK(unit);
  606 }
  607 
  608 bool
  609 dmar_is_buswide_ctx(struct dmar_unit *unit, u_int busno)
  610 {
  611 
  612         MPASS(busno <= PCI_BUSMAX);
  613         return ((unit->buswide_ctxs[busno / NBBY / sizeof(uint32_t)] &
  614             (1U << (busno % (NBBY * sizeof(uint32_t))))) != 0);
  615 }
  616 
  617 static void
  618 dmar_print_path(int busno, int depth, const ACPI_DMAR_PCI_PATH *path)
  619 {
  620         int i;
  621 
  622         printf("[%d, ", busno);
  623         for (i = 0; i < depth; i++) {
  624                 if (i != 0)
  625                         printf(", ");
  626                 printf("(%d, %d)", path[i].Device, path[i].Function);
  627         }
  628         printf("]");
  629 }
  630 
  631 int
  632 dmar_dev_depth(device_t child)
  633 {
  634         devclass_t pci_class;
  635         device_t bus, pcib;
  636         int depth;
  637 
  638         pci_class = devclass_find("pci");
  639         for (depth = 1; ; depth++) {
  640                 bus = device_get_parent(child);
  641                 pcib = device_get_parent(bus);
  642                 if (device_get_devclass(device_get_parent(pcib)) !=
  643                     pci_class)
  644                         return (depth);
  645                 child = pcib;
  646         }
  647 }
  648 
  649 void
  650 dmar_dev_path(device_t child, int *busno, void *path1, int depth)
  651 {
  652         devclass_t pci_class;
  653         device_t bus, pcib;
  654         ACPI_DMAR_PCI_PATH *path;
  655 
  656         pci_class = devclass_find("pci");
  657         path = path1;
  658         for (depth--; depth != -1; depth--) {
  659                 path[depth].Device = pci_get_slot(child);
  660                 path[depth].Function = pci_get_function(child);
  661                 bus = device_get_parent(child);
  662                 pcib = device_get_parent(bus);
  663                 if (device_get_devclass(device_get_parent(pcib)) !=
  664                     pci_class) {
  665                         /* reached a host bridge */
  666                         *busno = pcib_get_bus(bus);
  667                         return;
  668                 }
  669                 child = pcib;
  670         }
  671         panic("wrong depth");
  672 }
  673 
  674 static int
  675 dmar_match_pathes(int busno1, const ACPI_DMAR_PCI_PATH *path1, int depth1,
  676     int busno2, const ACPI_DMAR_PCI_PATH *path2, int depth2,
  677     enum AcpiDmarScopeType scope_type)
  678 {
  679         int i, depth;
  680 
  681         if (busno1 != busno2)
  682                 return (0);
  683         if (scope_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && depth1 != depth2)
  684                 return (0);
  685         depth = depth1;
  686         if (depth2 < depth)
  687                 depth = depth2;
  688         for (i = 0; i < depth; i++) {
  689                 if (path1[i].Device != path2[i].Device ||
  690                     path1[i].Function != path2[i].Function)
  691                         return (0);
  692         }
  693         return (1);
  694 }
  695 
  696 static int
  697 dmar_match_devscope(ACPI_DMAR_DEVICE_SCOPE *devscope, int dev_busno,
  698     const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len)
  699 {
  700         ACPI_DMAR_PCI_PATH *path;
  701         int path_len;
  702 
  703         if (devscope->Length < sizeof(*devscope)) {
  704                 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n",
  705                     devscope->Length);
  706                 return (-1);
  707         }
  708         if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
  709             devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_BRIDGE)
  710                 return (0);
  711         path_len = devscope->Length - sizeof(*devscope);
  712         if (path_len % 2 != 0) {
  713                 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n",
  714                     devscope->Length);
  715                 return (-1);
  716         }
  717         path_len /= 2;
  718         path = (ACPI_DMAR_PCI_PATH *)(devscope + 1);
  719         if (path_len == 0) {
  720                 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n",
  721                     devscope->Length);
  722                 return (-1);
  723         }
  724 
  725         return (dmar_match_pathes(devscope->Bus, path, path_len, dev_busno,
  726             dev_path, dev_path_len, devscope->EntryType));
  727 }
  728 
  729 static bool
  730 dmar_match_by_path(struct dmar_unit *unit, int dev_domain, int dev_busno,
  731     const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len, const char **banner)
  732 {
  733         ACPI_DMAR_HARDWARE_UNIT *dmarh;
  734         ACPI_DMAR_DEVICE_SCOPE *devscope;
  735         char *ptr, *ptrend;
  736         int match;
  737 
  738         dmarh = dmar_find_by_index(unit->unit);
  739         if (dmarh == NULL)
  740                 return (false);
  741         if (dmarh->Segment != dev_domain)
  742                 return (false);
  743         if ((dmarh->Flags & ACPI_DMAR_INCLUDE_ALL) != 0) {
  744                 if (banner != NULL)
  745                         *banner = "INCLUDE_ALL";
  746                 return (true);
  747         }
  748         ptr = (char *)dmarh + sizeof(*dmarh);
  749         ptrend = (char *)dmarh + dmarh->Header.Length;
  750         while (ptr < ptrend) {
  751                 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
  752                 ptr += devscope->Length;
  753                 match = dmar_match_devscope(devscope, dev_busno, dev_path,
  754                     dev_path_len);
  755                 if (match == -1)
  756                         return (false);
  757                 if (match == 1) {
  758                         if (banner != NULL)
  759                                 *banner = "specific match";
  760                         return (true);
  761                 }
  762         }
  763         return (false);
  764 }
  765 
  766 static struct dmar_unit *
  767 dmar_find_by_scope(int dev_domain, int dev_busno,
  768     const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len)
  769 {
  770         struct dmar_unit *unit;
  771         int i;
  772 
  773         for (i = 0; i < dmar_devcnt; i++) {
  774                 if (dmar_devs[i] == NULL)
  775                         continue;
  776                 unit = device_get_softc(dmar_devs[i]);
  777                 if (dmar_match_by_path(unit, dev_domain, dev_busno, dev_path,
  778                     dev_path_len, NULL))
  779                         return (unit);
  780         }
  781         return (NULL);
  782 }
  783 
  784 struct dmar_unit *
  785 dmar_find(device_t dev, bool verbose)
  786 {
  787         device_t dmar_dev;
  788         struct dmar_unit *unit;
  789         const char *banner;
  790         int i, dev_domain, dev_busno, dev_path_len;
  791 
  792         /*
  793          * This function can only handle PCI(e) devices.
  794          */
  795         if (device_get_devclass(device_get_parent(dev)) !=
  796             devclass_find("pci"))
  797                 return (NULL);
  798 
  799         dmar_dev = NULL;
  800         dev_domain = pci_get_domain(dev);
  801         dev_path_len = dmar_dev_depth(dev);
  802         ACPI_DMAR_PCI_PATH dev_path[dev_path_len];
  803         dmar_dev_path(dev, &dev_busno, dev_path, dev_path_len);
  804         banner = "";
  805 
  806         for (i = 0; i < dmar_devcnt; i++) {
  807                 if (dmar_devs[i] == NULL)
  808                         continue;
  809                 unit = device_get_softc(dmar_devs[i]);
  810                 if (dmar_match_by_path(unit, dev_domain, dev_busno,
  811                     dev_path, dev_path_len, &banner))
  812                         break;
  813         }
  814         if (i == dmar_devcnt)
  815                 return (NULL);
  816 
  817         if (verbose) {
  818                 device_printf(dev, "pci%d:%d:%d:%d matched dmar%d by %s",
  819                     dev_domain, pci_get_bus(dev), pci_get_slot(dev),
  820                     pci_get_function(dev), unit->unit, banner);
  821                 printf(" scope path ");
  822                 dmar_print_path(dev_busno, dev_path_len, dev_path);
  823                 printf("\n");
  824         }
  825         return (unit);
  826 }
  827 
  828 static struct dmar_unit *
  829 dmar_find_nonpci(u_int id, u_int entry_type, uint16_t *rid)
  830 {
  831         device_t dmar_dev;
  832         struct dmar_unit *unit;
  833         ACPI_DMAR_HARDWARE_UNIT *dmarh;
  834         ACPI_DMAR_DEVICE_SCOPE *devscope;
  835         ACPI_DMAR_PCI_PATH *path;
  836         char *ptr, *ptrend;
  837 #ifdef DEV_APIC
  838         int error;
  839 #endif
  840         int i;
  841 
  842         for (i = 0; i < dmar_devcnt; i++) {
  843                 dmar_dev = dmar_devs[i];
  844                 if (dmar_dev == NULL)
  845                         continue;
  846                 unit = (struct dmar_unit *)device_get_softc(dmar_dev);
  847                 dmarh = dmar_find_by_index(i);
  848                 if (dmarh == NULL)
  849                         continue;
  850                 ptr = (char *)dmarh + sizeof(*dmarh);
  851                 ptrend = (char *)dmarh + dmarh->Header.Length;
  852                 for (;;) {
  853                         if (ptr >= ptrend)
  854                                 break;
  855                         devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
  856                         ptr += devscope->Length;
  857                         if (devscope->EntryType != entry_type)
  858                                 continue;
  859                         if (devscope->EnumerationId != id)
  860                                 continue;
  861 #ifdef DEV_APIC
  862                         if (entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) {
  863                                 error = ioapic_get_rid(id, rid);
  864                                 /*
  865                                  * If our IOAPIC has PCI bindings then
  866                                  * use the PCI device rid.
  867                                  */
  868                                 if (error == 0)
  869                                         return (unit);
  870                         }
  871 #endif
  872                         if (devscope->Length - sizeof(ACPI_DMAR_DEVICE_SCOPE)
  873                             == 2) {
  874                                 if (rid != NULL) {
  875                                         path = (ACPI_DMAR_PCI_PATH *)
  876                                             (devscope + 1);
  877                                         *rid = PCI_RID(devscope->Bus,
  878                                             path->Device, path->Function);
  879                                 }
  880                                 return (unit);
  881                         }
  882                         printf(
  883                            "dmar_find_nonpci: id %d type %d path length != 2\n",
  884                             id, entry_type);
  885                         break;
  886                 }
  887         }
  888         return (NULL);
  889 }
  890 
  891 
  892 struct dmar_unit *
  893 dmar_find_hpet(device_t dev, uint16_t *rid)
  894 {
  895 
  896         return (dmar_find_nonpci(hpet_get_uid(dev), ACPI_DMAR_SCOPE_TYPE_HPET,
  897             rid));
  898 }
  899 
  900 struct dmar_unit *
  901 dmar_find_ioapic(u_int apic_id, uint16_t *rid)
  902 {
  903 
  904         return (dmar_find_nonpci(apic_id, ACPI_DMAR_SCOPE_TYPE_IOAPIC, rid));
  905 }
  906 
  907 struct rmrr_iter_args {
  908         struct dmar_domain *domain;
  909         int dev_domain;
  910         int dev_busno;
  911         const ACPI_DMAR_PCI_PATH *dev_path;
  912         int dev_path_len;
  913         struct dmar_map_entries_tailq *rmrr_entries;
  914 };
  915 
  916 static int
  917 dmar_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
  918 {
  919         struct rmrr_iter_args *ria;
  920         ACPI_DMAR_RESERVED_MEMORY *resmem;
  921         ACPI_DMAR_DEVICE_SCOPE *devscope;
  922         struct dmar_map_entry *entry;
  923         char *ptr, *ptrend;
  924         int match;
  925 
  926         if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY)
  927                 return (1);
  928 
  929         ria = arg;
  930         resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh;
  931         if (resmem->Segment != ria->dev_domain)
  932                 return (1);
  933 
  934         ptr = (char *)resmem + sizeof(*resmem);
  935         ptrend = (char *)resmem + resmem->Header.Length;
  936         for (;;) {
  937                 if (ptr >= ptrend)
  938                         break;
  939                 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
  940                 ptr += devscope->Length;
  941                 match = dmar_match_devscope(devscope, ria->dev_busno,
  942                     ria->dev_path, ria->dev_path_len);
  943                 if (match == 1) {
  944                         entry = dmar_gas_alloc_entry(ria->domain,
  945                             DMAR_PGF_WAITOK);
  946                         entry->start = resmem->BaseAddress;
  947                         /* The RMRR entry end address is inclusive. */
  948                         entry->end = resmem->EndAddress;
  949                         TAILQ_INSERT_TAIL(ria->rmrr_entries, entry,
  950                             unroll_link);
  951                 }
  952         }
  953 
  954         return (1);
  955 }
  956 
  957 void
  958 dmar_dev_parse_rmrr(struct dmar_domain *domain, int dev_domain, int dev_busno,
  959     const void *dev_path, int dev_path_len,
  960     struct dmar_map_entries_tailq *rmrr_entries)
  961 {
  962         struct rmrr_iter_args ria;
  963 
  964         ria.domain = domain;
  965         ria.dev_domain = dev_domain;
  966         ria.dev_busno = dev_busno;
  967         ria.dev_path = (const ACPI_DMAR_PCI_PATH *)dev_path;
  968         ria.dev_path_len = dev_path_len;
  969         ria.rmrr_entries = rmrr_entries;
  970         dmar_iterate_tbl(dmar_rmrr_iter, &ria);
  971 }
  972 
  973 struct inst_rmrr_iter_args {
  974         struct dmar_unit *dmar;
  975 };
  976 
  977 static device_t
  978 dmar_path_dev(int segment, int path_len, int busno,
  979     const ACPI_DMAR_PCI_PATH *path, uint16_t *rid)
  980 {
  981         device_t dev;
  982         int i;
  983 
  984         dev = NULL;
  985         for (i = 0; i < path_len; i++) {
  986                 dev = pci_find_dbsf(segment, busno, path->Device,
  987                     path->Function);
  988                 if (i != path_len - 1) {
  989                         busno = pci_cfgregread(busno, path->Device,
  990                             path->Function, PCIR_SECBUS_1, 1);
  991                         path++;
  992                 }
  993         }
  994         *rid = PCI_RID(busno, path->Device, path->Function);
  995         return (dev);
  996 }
  997 
  998 static int
  999 dmar_inst_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
 1000 {
 1001         const ACPI_DMAR_RESERVED_MEMORY *resmem;
 1002         const ACPI_DMAR_DEVICE_SCOPE *devscope;
 1003         struct inst_rmrr_iter_args *iria;
 1004         const char *ptr, *ptrend;
 1005         device_t dev;
 1006         struct dmar_unit *unit;
 1007         int dev_path_len;
 1008         uint16_t rid;
 1009 
 1010         iria = arg;
 1011 
 1012         if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY)
 1013                 return (1);
 1014 
 1015         resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh;
 1016         if (resmem->Segment != iria->dmar->segment)
 1017                 return (1);
 1018 
 1019         ptr = (const char *)resmem + sizeof(*resmem);
 1020         ptrend = (const char *)resmem + resmem->Header.Length;
 1021         for (;;) {
 1022                 if (ptr >= ptrend)
 1023                         break;
 1024                 devscope = (const ACPI_DMAR_DEVICE_SCOPE *)ptr;
 1025                 ptr += devscope->Length;
 1026                 /* XXXKIB bridge */
 1027                 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT)
 1028                         continue;
 1029                 rid = 0;
 1030                 dev_path_len = (devscope->Length -
 1031                     sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2;
 1032                 dev = dmar_path_dev(resmem->Segment, dev_path_len,
 1033                     devscope->Bus,
 1034                     (const ACPI_DMAR_PCI_PATH *)(devscope + 1), &rid);
 1035                 if (dev == NULL) {
 1036                         if (bootverbose) {
 1037                                 printf("dmar%d no dev found for RMRR "
 1038                                     "[%#jx, %#jx] rid %#x scope path ",
 1039                                      iria->dmar->unit,
 1040                                      (uintmax_t)resmem->BaseAddress,
 1041                                      (uintmax_t)resmem->EndAddress,
 1042                                      rid);
 1043                                 dmar_print_path(devscope->Bus, dev_path_len,
 1044                                     (const ACPI_DMAR_PCI_PATH *)(devscope + 1));
 1045                                 printf("\n");
 1046                         }
 1047                         unit = dmar_find_by_scope(resmem->Segment,
 1048                             devscope->Bus,
 1049                             (const ACPI_DMAR_PCI_PATH *)(devscope + 1),
 1050                             dev_path_len);
 1051                         if (iria->dmar != unit)
 1052                                 continue;
 1053                         dmar_get_ctx_for_devpath(iria->dmar, rid,
 1054                             resmem->Segment, devscope->Bus, 
 1055                             (const ACPI_DMAR_PCI_PATH *)(devscope + 1),
 1056                             dev_path_len, false, true);
 1057                 } else {
 1058                         unit = dmar_find(dev, false);
 1059                         if (iria->dmar != unit)
 1060                                 continue;
 1061                         dmar_instantiate_ctx(iria->dmar, dev, true);
 1062                 }
 1063         }
 1064 
 1065         return (1);
 1066 
 1067 }
 1068 
 1069 /*
 1070  * Pre-create all contexts for the DMAR which have RMRR entries.
 1071  */
 1072 int
 1073 dmar_instantiate_rmrr_ctxs(struct dmar_unit *dmar)
 1074 {
 1075         struct inst_rmrr_iter_args iria;
 1076         int error;
 1077 
 1078         if (!dmar_barrier_enter(dmar, DMAR_BARRIER_RMRR))
 1079                 return (0);
 1080 
 1081         error = 0;
 1082         iria.dmar = dmar;
 1083         dmar_iterate_tbl(dmar_inst_rmrr_iter, &iria);
 1084         DMAR_LOCK(dmar);
 1085         if (!LIST_EMPTY(&dmar->domains)) {
 1086                 KASSERT((dmar->hw_gcmd & DMAR_GCMD_TE) == 0,
 1087             ("dmar%d: RMRR not handled but translation is already enabled",
 1088                     dmar->unit));
 1089                 error = dmar_enable_translation(dmar);
 1090                 if (bootverbose) {
 1091                         if (error == 0) {
 1092                                 printf("dmar%d: enabled translation\n",
 1093                                     dmar->unit);
 1094                         } else {
 1095                                 printf("dmar%d: enabling translation failed, "
 1096                                     "error %d\n", dmar->unit, error);
 1097                         }
 1098                 }
 1099         }
 1100         dmar_barrier_exit(dmar, DMAR_BARRIER_RMRR);
 1101         return (error);
 1102 }
 1103 
 1104 #ifdef DDB
 1105 #include <ddb/ddb.h>
 1106 #include <ddb/db_lex.h>
 1107 
 1108 static void
 1109 dmar_print_domain_entry(const struct dmar_map_entry *entry)
 1110 {
 1111         struct dmar_map_entry *l, *r;
 1112 
 1113         db_printf(
 1114             "    start %jx end %jx free_after %jx free_down %jx flags %x ",
 1115             entry->start, entry->end, entry->free_after, entry->free_down,
 1116             entry->flags);
 1117         db_printf("left ");
 1118         l = RB_LEFT(entry, rb_entry);
 1119         if (l == NULL)
 1120                 db_printf("NULL ");
 1121         else
 1122                 db_printf("%jx ", l->start);
 1123         db_printf("right ");
 1124         r = RB_RIGHT(entry, rb_entry);
 1125         if (r == NULL)
 1126                 db_printf("NULL");
 1127         else
 1128                 db_printf("%jx", r->start);
 1129         db_printf("\n");
 1130 }
 1131 
 1132 static void
 1133 dmar_print_ctx(struct dmar_ctx *ctx)
 1134 {
 1135 
 1136         db_printf(
 1137             "    @%p pci%d:%d:%d refs %d flags %x loads %lu unloads %lu\n",
 1138             ctx, pci_get_bus(ctx->ctx_tag.owner),
 1139             pci_get_slot(ctx->ctx_tag.owner),
 1140             pci_get_function(ctx->ctx_tag.owner), ctx->refs, ctx->flags,
 1141             ctx->loads, ctx->unloads);
 1142 }
 1143 
 1144 static void
 1145 dmar_print_domain(struct dmar_domain *domain, bool show_mappings)
 1146 {
 1147         struct dmar_map_entry *entry;
 1148         struct dmar_ctx *ctx;
 1149 
 1150         db_printf(
 1151             "  @%p dom %d mgaw %d agaw %d pglvl %d end %jx refs %d\n"
 1152             "   ctx_cnt %d flags %x pgobj %p map_ents %u\n",
 1153             domain, domain->domain, domain->mgaw, domain->agaw, domain->pglvl,
 1154             (uintmax_t)domain->end, domain->refs, domain->ctx_cnt,
 1155             domain->flags, domain->pgtbl_obj, domain->entries_cnt);
 1156         if (!LIST_EMPTY(&domain->contexts)) {
 1157                 db_printf("  Contexts:\n");
 1158                 LIST_FOREACH(ctx, &domain->contexts, link)
 1159                         dmar_print_ctx(ctx);
 1160         }
 1161         if (!show_mappings)
 1162                 return;
 1163         db_printf("    mapped:\n");
 1164         RB_FOREACH(entry, dmar_gas_entries_tree, &domain->rb_root) {
 1165                 dmar_print_domain_entry(entry);
 1166                 if (db_pager_quit)
 1167                         break;
 1168         }
 1169         if (db_pager_quit)
 1170                 return;
 1171         db_printf("    unloading:\n");
 1172         TAILQ_FOREACH(entry, &domain->unload_entries, dmamap_link) {
 1173                 dmar_print_domain_entry(entry);
 1174                 if (db_pager_quit)
 1175                         break;
 1176         }
 1177 }
 1178 
 1179 DB_FUNC(dmar_domain, db_dmar_print_domain, db_show_table, CS_OWN, NULL)
 1180 {
 1181         struct dmar_unit *unit;
 1182         struct dmar_domain *domain;
 1183         struct dmar_ctx *ctx;
 1184         bool show_mappings, valid;
 1185         int pci_domain, bus, device, function, i, t;
 1186         db_expr_t radix;
 1187 
 1188         valid = false;
 1189         radix = db_radix;
 1190         db_radix = 10;
 1191         t = db_read_token();
 1192         if (t == tSLASH) {
 1193                 t = db_read_token();
 1194                 if (t != tIDENT) {
 1195                         db_printf("Bad modifier\n");
 1196                         db_radix = radix;
 1197                         db_skip_to_eol();
 1198                         return;
 1199                 }
 1200                 show_mappings = strchr(db_tok_string, 'm') != NULL;
 1201                 t = db_read_token();
 1202         } else {
 1203                 show_mappings = false;
 1204         }
 1205         if (t == tNUMBER) {
 1206                 pci_domain = db_tok_number;
 1207                 t = db_read_token();
 1208                 if (t == tNUMBER) {
 1209                         bus = db_tok_number;
 1210                         t = db_read_token();
 1211                         if (t == tNUMBER) {
 1212                                 device = db_tok_number;
 1213                                 t = db_read_token();
 1214                                 if (t == tNUMBER) {
 1215                                         function = db_tok_number;
 1216                                         valid = true;
 1217                                 }
 1218                         }
 1219                 }
 1220         }
 1221                         db_radix = radix;
 1222         db_skip_to_eol();
 1223         if (!valid) {
 1224                 db_printf("usage: show dmar_domain [/m] "
 1225                     "<domain> <bus> <device> <func>\n");
 1226                 return;
 1227         }
 1228         for (i = 0; i < dmar_devcnt; i++) {
 1229                 unit = device_get_softc(dmar_devs[i]);
 1230                 LIST_FOREACH(domain, &unit->domains, link) {
 1231                         LIST_FOREACH(ctx, &domain->contexts, link) {
 1232                                 if (pci_domain == unit->segment && 
 1233                                     bus == pci_get_bus(ctx->ctx_tag.owner) &&
 1234                                     device ==
 1235                                     pci_get_slot(ctx->ctx_tag.owner) &&
 1236                                     function ==
 1237                                     pci_get_function(ctx->ctx_tag.owner)) {
 1238                                         dmar_print_domain(domain,
 1239                                             show_mappings);
 1240                                         goto out;
 1241                                 }
 1242                         }
 1243                 }
 1244         }
 1245 out:;
 1246 }
 1247 
 1248 static void
 1249 dmar_print_one(int idx, bool show_domains, bool show_mappings)
 1250 {
 1251         struct dmar_unit *unit;
 1252         struct dmar_domain *domain;
 1253         int i, frir;
 1254 
 1255         unit = device_get_softc(dmar_devs[idx]);
 1256         db_printf("dmar%d at %p, root at 0x%jx, ver 0x%x\n", unit->unit, unit,
 1257             dmar_read8(unit, DMAR_RTADDR_REG), dmar_read4(unit, DMAR_VER_REG));
 1258         db_printf("cap 0x%jx ecap 0x%jx gsts 0x%x fsts 0x%x fectl 0x%x\n",
 1259             (uintmax_t)dmar_read8(unit, DMAR_CAP_REG),
 1260             (uintmax_t)dmar_read8(unit, DMAR_ECAP_REG),
 1261             dmar_read4(unit, DMAR_GSTS_REG),
 1262             dmar_read4(unit, DMAR_FSTS_REG),
 1263             dmar_read4(unit, DMAR_FECTL_REG));
 1264         if (unit->ir_enabled) {
 1265                 db_printf("ir is enabled; IRT @%p phys 0x%jx maxcnt %d\n",
 1266                     unit->irt, (uintmax_t)unit->irt_phys, unit->irte_cnt);
 1267         }
 1268         db_printf("fed 0x%x fea 0x%x feua 0x%x\n",
 1269             dmar_read4(unit, DMAR_FEDATA_REG),
 1270             dmar_read4(unit, DMAR_FEADDR_REG),
 1271             dmar_read4(unit, DMAR_FEUADDR_REG));
 1272         db_printf("primary fault log:\n");
 1273         for (i = 0; i < DMAR_CAP_NFR(unit->hw_cap); i++) {
 1274                 frir = (DMAR_CAP_FRO(unit->hw_cap) + i) * 16;
 1275                 db_printf("  %d at 0x%x: %jx %jx\n", i, frir,
 1276                     (uintmax_t)dmar_read8(unit, frir),
 1277                     (uintmax_t)dmar_read8(unit, frir + 8));
 1278         }
 1279         if (DMAR_HAS_QI(unit)) {
 1280                 db_printf("ied 0x%x iea 0x%x ieua 0x%x\n",
 1281                     dmar_read4(unit, DMAR_IEDATA_REG),
 1282                     dmar_read4(unit, DMAR_IEADDR_REG),
 1283                     dmar_read4(unit, DMAR_IEUADDR_REG));
 1284                 if (unit->qi_enabled) {
 1285                         db_printf("qi is enabled: queue @0x%jx (IQA 0x%jx) "
 1286                             "size 0x%jx\n"
 1287                     "  head 0x%x tail 0x%x avail 0x%x status 0x%x ctrl 0x%x\n"
 1288                     "  hw compl 0x%x@%p/phys@%jx next seq 0x%x gen 0x%x\n",
 1289                             (uintmax_t)unit->inv_queue,
 1290                             (uintmax_t)dmar_read8(unit, DMAR_IQA_REG),
 1291                             (uintmax_t)unit->inv_queue_size,
 1292                             dmar_read4(unit, DMAR_IQH_REG),
 1293                             dmar_read4(unit, DMAR_IQT_REG),
 1294                             unit->inv_queue_avail,
 1295                             dmar_read4(unit, DMAR_ICS_REG),
 1296                             dmar_read4(unit, DMAR_IECTL_REG),
 1297                             unit->inv_waitd_seq_hw,
 1298                             &unit->inv_waitd_seq_hw,
 1299                             (uintmax_t)unit->inv_waitd_seq_hw_phys,
 1300                             unit->inv_waitd_seq,
 1301                             unit->inv_waitd_gen);
 1302                 } else {
 1303                         db_printf("qi is disabled\n");
 1304                 }
 1305         }
 1306         if (show_domains) {
 1307                 db_printf("domains:\n");
 1308                 LIST_FOREACH(domain, &unit->domains, link) {
 1309                         dmar_print_domain(domain, show_mappings);
 1310                         if (db_pager_quit)
 1311                                 break;
 1312                 }
 1313         }
 1314 }
 1315 
 1316 DB_SHOW_COMMAND(dmar, db_dmar_print)
 1317 {
 1318         bool show_domains, show_mappings;
 1319 
 1320         show_domains = strchr(modif, 'd') != NULL;
 1321         show_mappings = strchr(modif, 'm') != NULL;
 1322         if (!have_addr) {
 1323                 db_printf("usage: show dmar [/d] [/m] index\n");
 1324                 return;
 1325         }
 1326         dmar_print_one((int)addr, show_domains, show_mappings);
 1327 }
 1328 
 1329 DB_SHOW_ALL_COMMAND(dmars, db_show_all_dmars)
 1330 {
 1331         int i;
 1332         bool show_domains, show_mappings;
 1333 
 1334         show_domains = strchr(modif, 'd') != NULL;
 1335         show_mappings = strchr(modif, 'm') != NULL;
 1336 
 1337         for (i = 0; i < dmar_devcnt; i++) {
 1338                 dmar_print_one(i, show_domains, show_mappings);
 1339                 if (db_pager_quit)
 1340                         break;
 1341         }
 1342 }
 1343 #endif

Cache object: 277b7000a730d75d2c51b5bdd880eda9


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.