The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/x86/iommu/intel_drv.c

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2013-2015 The FreeBSD Foundation
    5  * All rights reserved.
    6  *
    7  * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
    8  * under sponsorship from the FreeBSD Foundation.
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  *
   19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   22  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   29  * SUCH DAMAGE.
   30  */
   31 
   32 #include <sys/cdefs.h>
   33 __FBSDID("$FreeBSD$");
   34 
   35 #include "opt_acpi.h"
   36 #if defined(__amd64__)
   37 #define DEV_APIC
   38 #else
   39 #include "opt_apic.h"
   40 #endif
   41 #include "opt_ddb.h"
   42 
   43 #include <sys/param.h>
   44 #include <sys/bus.h>
   45 #include <sys/kernel.h>
   46 #include <sys/lock.h>
   47 #include <sys/malloc.h>
   48 #include <sys/memdesc.h>
   49 #include <sys/module.h>
   50 #include <sys/mutex.h>
   51 #include <sys/rman.h>
   52 #include <sys/rwlock.h>
   53 #include <sys/smp.h>
   54 #include <sys/taskqueue.h>
   55 #include <sys/tree.h>
   56 #include <sys/vmem.h>
   57 #include <vm/vm.h>
   58 #include <vm/vm_extern.h>
   59 #include <vm/vm_kern.h>
   60 #include <vm/vm_object.h>
   61 #include <vm/vm_page.h>
   62 #include <vm/vm_pager.h>
   63 #include <vm/vm_map.h>
   64 #include <contrib/dev/acpica/include/acpi.h>
   65 #include <contrib/dev/acpica/include/accommon.h>
   66 #include <dev/acpica/acpivar.h>
   67 #include <dev/pci/pcireg.h>
   68 #include <dev/pci/pcivar.h>
   69 #include <machine/bus.h>
   70 #include <machine/pci_cfgreg.h>
   71 #include <x86/include/busdma_impl.h>
   72 #include <dev/iommu/busdma_iommu.h>
   73 #include <x86/iommu/intel_reg.h>
   74 #include <x86/iommu/intel_dmar.h>
   75 
   76 #ifdef DEV_APIC
   77 #include "pcib_if.h"
   78 #include <machine/intr_machdep.h>
   79 #include <x86/apicreg.h>
   80 #include <x86/apicvar.h>
   81 #endif
   82 
   83 #define DMAR_FAULT_IRQ_RID      0
   84 #define DMAR_QI_IRQ_RID         1
   85 #define DMAR_REG_RID            2
   86 
   87 static devclass_t dmar_devclass;
   88 static device_t *dmar_devs;
   89 static int dmar_devcnt;
   90 
   91 typedef int (*dmar_iter_t)(ACPI_DMAR_HEADER *, void *);
   92 
   93 static void
   94 dmar_iterate_tbl(dmar_iter_t iter, void *arg)
   95 {
   96         ACPI_TABLE_DMAR *dmartbl;
   97         ACPI_DMAR_HEADER *dmarh;
   98         char *ptr, *ptrend;
   99         ACPI_STATUS status;
  100 
  101         status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl);
  102         if (ACPI_FAILURE(status))
  103                 return;
  104         ptr = (char *)dmartbl + sizeof(*dmartbl);
  105         ptrend = (char *)dmartbl + dmartbl->Header.Length;
  106         for (;;) {
  107                 if (ptr >= ptrend)
  108                         break;
  109                 dmarh = (ACPI_DMAR_HEADER *)ptr;
  110                 if (dmarh->Length <= 0) {
  111                         printf("dmar_identify: corrupted DMAR table, l %d\n",
  112                             dmarh->Length);
  113                         break;
  114                 }
  115                 ptr += dmarh->Length;
  116                 if (!iter(dmarh, arg))
  117                         break;
  118         }
  119         AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl);
  120 }
  121 
  122 struct find_iter_args {
  123         int i;
  124         ACPI_DMAR_HARDWARE_UNIT *res;
  125 };
  126 
  127 static int
  128 dmar_find_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
  129 {
  130         struct find_iter_args *fia;
  131 
  132         if (dmarh->Type != ACPI_DMAR_TYPE_HARDWARE_UNIT)
  133                 return (1);
  134 
  135         fia = arg;
  136         if (fia->i == 0) {
  137                 fia->res = (ACPI_DMAR_HARDWARE_UNIT *)dmarh;
  138                 return (0);
  139         }
  140         fia->i--;
  141         return (1);
  142 }
  143 
  144 static ACPI_DMAR_HARDWARE_UNIT *
  145 dmar_find_by_index(int idx)
  146 {
  147         struct find_iter_args fia;
  148 
  149         fia.i = idx;
  150         fia.res = NULL;
  151         dmar_iterate_tbl(dmar_find_iter, &fia);
  152         return (fia.res);
  153 }
  154 
  155 static int
  156 dmar_count_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
  157 {
  158 
  159         if (dmarh->Type == ACPI_DMAR_TYPE_HARDWARE_UNIT)
  160                 dmar_devcnt++;
  161         return (1);
  162 }
  163 
  164 static int dmar_enable = 0;
  165 static void
  166 dmar_identify(driver_t *driver, device_t parent)
  167 {
  168         ACPI_TABLE_DMAR *dmartbl;
  169         ACPI_DMAR_HARDWARE_UNIT *dmarh;
  170         ACPI_STATUS status;
  171         int i, error;
  172 
  173         if (acpi_disabled("dmar"))
  174                 return;
  175         TUNABLE_INT_FETCH("hw.dmar.enable", &dmar_enable);
  176         if (!dmar_enable)
  177                 return;
  178         status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl);
  179         if (ACPI_FAILURE(status))
  180                 return;
  181         haw = dmartbl->Width + 1;
  182         if ((1ULL << (haw + 1)) > BUS_SPACE_MAXADDR)
  183                 dmar_high = BUS_SPACE_MAXADDR;
  184         else
  185                 dmar_high = 1ULL << (haw + 1);
  186         if (bootverbose) {
  187                 printf("DMAR HAW=%d flags=<%b>\n", dmartbl->Width,
  188                     (unsigned)dmartbl->Flags,
  189                     "\020\001INTR_REMAP\002X2APIC_OPT_OUT");
  190         }
  191         AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl);
  192 
  193         dmar_iterate_tbl(dmar_count_iter, NULL);
  194         if (dmar_devcnt == 0)
  195                 return;
  196         dmar_devs = malloc(sizeof(device_t) * dmar_devcnt, M_DEVBUF,
  197             M_WAITOK | M_ZERO);
  198         for (i = 0; i < dmar_devcnt; i++) {
  199                 dmarh = dmar_find_by_index(i);
  200                 if (dmarh == NULL) {
  201                         printf("dmar_identify: cannot find HWUNIT %d\n", i);
  202                         continue;
  203                 }
  204                 dmar_devs[i] = BUS_ADD_CHILD(parent, 1, "dmar", i);
  205                 if (dmar_devs[i] == NULL) {
  206                         printf("dmar_identify: cannot create instance %d\n", i);
  207                         continue;
  208                 }
  209                 error = bus_set_resource(dmar_devs[i], SYS_RES_MEMORY,
  210                     DMAR_REG_RID, dmarh->Address, PAGE_SIZE);
  211                 if (error != 0) {
  212                         printf(
  213         "dmar%d: unable to alloc register window at 0x%08jx: error %d\n",
  214                             i, (uintmax_t)dmarh->Address, error);
  215                         device_delete_child(parent, dmar_devs[i]);
  216                         dmar_devs[i] = NULL;
  217                 }
  218         }
  219 }
  220 
  221 static int
  222 dmar_probe(device_t dev)
  223 {
  224 
  225         if (acpi_get_handle(dev) != NULL)
  226                 return (ENXIO);
  227         device_set_desc(dev, "DMA remap");
  228         return (BUS_PROBE_NOWILDCARD);
  229 }
  230 
  231 static void
  232 dmar_release_intr(device_t dev, struct dmar_unit *unit, int idx)
  233 {
  234         struct dmar_msi_data *dmd;
  235 
  236         dmd = &unit->intrs[idx];
  237         if (dmd->irq == -1)
  238                 return;
  239         bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle);
  240         bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res);
  241         bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid);
  242         PCIB_RELEASE_MSIX(device_get_parent(device_get_parent(dev)),
  243             dev, dmd->irq);
  244         dmd->irq = -1;
  245 }
  246 
  247 static void
  248 dmar_release_resources(device_t dev, struct dmar_unit *unit)
  249 {
  250         int i;
  251 
  252         iommu_fini_busdma(&unit->iommu);
  253         dmar_fini_irt(unit);
  254         dmar_fini_qi(unit);
  255         dmar_fini_fault_log(unit);
  256         for (i = 0; i < DMAR_INTR_TOTAL; i++)
  257                 dmar_release_intr(dev, unit, i);
  258         if (unit->regs != NULL) {
  259                 bus_deactivate_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
  260                     unit->regs);
  261                 bus_release_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
  262                     unit->regs);
  263                 unit->regs = NULL;
  264         }
  265         if (unit->domids != NULL) {
  266                 delete_unrhdr(unit->domids);
  267                 unit->domids = NULL;
  268         }
  269         if (unit->ctx_obj != NULL) {
  270                 vm_object_deallocate(unit->ctx_obj);
  271                 unit->ctx_obj = NULL;
  272         }
  273 }
  274 
  275 static int
  276 dmar_alloc_irq(device_t dev, struct dmar_unit *unit, int idx)
  277 {
  278         device_t pcib;
  279         struct dmar_msi_data *dmd;
  280         uint64_t msi_addr;
  281         uint32_t msi_data;
  282         int error;
  283 
  284         dmd = &unit->intrs[idx];
  285         pcib = device_get_parent(device_get_parent(dev)); /* Really not pcib */
  286         error = PCIB_ALLOC_MSIX(pcib, dev, &dmd->irq);
  287         if (error != 0) {
  288                 device_printf(dev, "cannot allocate %s interrupt, %d\n",
  289                     dmd->name, error);
  290                 goto err1;
  291         }
  292         error = bus_set_resource(dev, SYS_RES_IRQ, dmd->irq_rid,
  293             dmd->irq, 1);
  294         if (error != 0) {
  295                 device_printf(dev, "cannot set %s interrupt resource, %d\n",
  296                     dmd->name, error);
  297                 goto err2;
  298         }
  299         dmd->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
  300             &dmd->irq_rid, RF_ACTIVE);
  301         if (dmd->irq_res == NULL) {
  302                 device_printf(dev,
  303                     "cannot allocate resource for %s interrupt\n", dmd->name);
  304                 error = ENXIO;
  305                 goto err3;
  306         }
  307         error = bus_setup_intr(dev, dmd->irq_res, INTR_TYPE_MISC,
  308             dmd->handler, NULL, unit, &dmd->intr_handle);
  309         if (error != 0) {
  310                 device_printf(dev, "cannot setup %s interrupt, %d\n",
  311                     dmd->name, error);
  312                 goto err4;
  313         }
  314         bus_describe_intr(dev, dmd->irq_res, dmd->intr_handle, "%s", dmd->name);
  315         error = PCIB_MAP_MSI(pcib, dev, dmd->irq, &msi_addr, &msi_data);
  316         if (error != 0) {
  317                 device_printf(dev, "cannot map %s interrupt, %d\n",
  318                     dmd->name, error);
  319                 goto err5;
  320         }
  321         dmar_write4(unit, dmd->msi_data_reg, msi_data);
  322         dmar_write4(unit, dmd->msi_addr_reg, msi_addr);
  323         /* Only for xAPIC mode */
  324         dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32);
  325         return (0);
  326 
  327 err5:
  328         bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle);
  329 err4:
  330         bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res);
  331 err3:
  332         bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid);
  333 err2:
  334         PCIB_RELEASE_MSIX(pcib, dev, dmd->irq);
  335         dmd->irq = -1;
  336 err1:
  337         return (error);
  338 }
  339 
  340 #ifdef DEV_APIC
  341 static int
  342 dmar_remap_intr(device_t dev, device_t child, u_int irq)
  343 {
  344         struct dmar_unit *unit;
  345         struct dmar_msi_data *dmd;
  346         uint64_t msi_addr;
  347         uint32_t msi_data;
  348         int i, error;
  349 
  350         unit = device_get_softc(dev);
  351         for (i = 0; i < DMAR_INTR_TOTAL; i++) {
  352                 dmd = &unit->intrs[i];
  353                 if (irq == dmd->irq) {
  354                         error = PCIB_MAP_MSI(device_get_parent(
  355                             device_get_parent(dev)),
  356                             dev, irq, &msi_addr, &msi_data);
  357                         if (error != 0)
  358                                 return (error);
  359                         DMAR_LOCK(unit);
  360                         (dmd->disable_intr)(unit);
  361                         dmar_write4(unit, dmd->msi_data_reg, msi_data);
  362                         dmar_write4(unit, dmd->msi_addr_reg, msi_addr);
  363                         dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32);
  364                         (dmd->enable_intr)(unit);
  365                         DMAR_UNLOCK(unit);
  366                         return (0);
  367                 }
  368         }
  369         return (ENOENT);
  370 }
  371 #endif
  372 
  373 static void
  374 dmar_print_caps(device_t dev, struct dmar_unit *unit,
  375     ACPI_DMAR_HARDWARE_UNIT *dmaru)
  376 {
  377         uint32_t caphi, ecaphi;
  378 
  379         device_printf(dev, "regs@0x%08jx, ver=%d.%d, seg=%d, flags=<%b>\n",
  380             (uintmax_t)dmaru->Address, DMAR_MAJOR_VER(unit->hw_ver),
  381             DMAR_MINOR_VER(unit->hw_ver), dmaru->Segment,
  382             dmaru->Flags, "\020\001INCLUDE_ALL_PCI");
  383         caphi = unit->hw_cap >> 32;
  384         device_printf(dev, "cap=%b,", (u_int)unit->hw_cap,
  385             "\020\004AFL\005WBF\006PLMR\007PHMR\010CM\027ZLR\030ISOCH");
  386         printf("%b, ", caphi, "\020\010PSI\027DWD\030DRD\031FL1GP\034PSI");
  387         printf("ndoms=%d, sagaw=%d, mgaw=%d, fro=%d, nfr=%d, superp=%d",
  388             DMAR_CAP_ND(unit->hw_cap), DMAR_CAP_SAGAW(unit->hw_cap),
  389             DMAR_CAP_MGAW(unit->hw_cap), DMAR_CAP_FRO(unit->hw_cap),
  390             DMAR_CAP_NFR(unit->hw_cap), DMAR_CAP_SPS(unit->hw_cap));
  391         if ((unit->hw_cap & DMAR_CAP_PSI) != 0)
  392                 printf(", mamv=%d", DMAR_CAP_MAMV(unit->hw_cap));
  393         printf("\n");
  394         ecaphi = unit->hw_ecap >> 32;
  395         device_printf(dev, "ecap=%b,", (u_int)unit->hw_ecap,
  396             "\020\001C\002QI\003DI\004IR\005EIM\007PT\010SC\031ECS\032MTS"
  397             "\033NEST\034DIS\035PASID\036PRS\037ERS\040SRS");
  398         printf("%b, ", ecaphi, "\020\002NWFS\003EAFS");
  399         printf("mhmw=%d, iro=%d\n", DMAR_ECAP_MHMV(unit->hw_ecap),
  400             DMAR_ECAP_IRO(unit->hw_ecap));
  401 }
  402 
  403 static int
  404 dmar_attach(device_t dev)
  405 {
  406         struct dmar_unit *unit;
  407         ACPI_DMAR_HARDWARE_UNIT *dmaru;
  408         uint64_t timeout;
  409         int i, error;
  410 
  411         unit = device_get_softc(dev);
  412         unit->dev = dev;
  413         unit->iommu.unit = device_get_unit(dev);
  414         unit->iommu.dev = dev;
  415         dmaru = dmar_find_by_index(unit->iommu.unit);
  416         if (dmaru == NULL)
  417                 return (EINVAL);
  418         unit->segment = dmaru->Segment;
  419         unit->base = dmaru->Address;
  420         unit->reg_rid = DMAR_REG_RID;
  421         unit->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
  422             &unit->reg_rid, RF_ACTIVE);
  423         if (unit->regs == NULL) {
  424                 device_printf(dev, "cannot allocate register window\n");
  425                 return (ENOMEM);
  426         }
  427         unit->hw_ver = dmar_read4(unit, DMAR_VER_REG);
  428         unit->hw_cap = dmar_read8(unit, DMAR_CAP_REG);
  429         unit->hw_ecap = dmar_read8(unit, DMAR_ECAP_REG);
  430         if (bootverbose)
  431                 dmar_print_caps(dev, unit, dmaru);
  432         dmar_quirks_post_ident(unit);
  433 
  434         timeout = dmar_get_timeout();
  435         TUNABLE_UINT64_FETCH("hw.dmar.timeout", &timeout);
  436         dmar_update_timeout(timeout);
  437 
  438         for (i = 0; i < DMAR_INTR_TOTAL; i++)
  439                 unit->intrs[i].irq = -1;
  440 
  441         unit->intrs[DMAR_INTR_FAULT].name = "fault";
  442         unit->intrs[DMAR_INTR_FAULT].irq_rid = DMAR_FAULT_IRQ_RID;
  443         unit->intrs[DMAR_INTR_FAULT].handler = dmar_fault_intr;
  444         unit->intrs[DMAR_INTR_FAULT].msi_data_reg = DMAR_FEDATA_REG;
  445         unit->intrs[DMAR_INTR_FAULT].msi_addr_reg = DMAR_FEADDR_REG;
  446         unit->intrs[DMAR_INTR_FAULT].msi_uaddr_reg = DMAR_FEUADDR_REG;
  447         unit->intrs[DMAR_INTR_FAULT].enable_intr = dmar_enable_fault_intr;
  448         unit->intrs[DMAR_INTR_FAULT].disable_intr = dmar_disable_fault_intr;
  449         error = dmar_alloc_irq(dev, unit, DMAR_INTR_FAULT);
  450         if (error != 0) {
  451                 dmar_release_resources(dev, unit);
  452                 return (error);
  453         }
  454         if (DMAR_HAS_QI(unit)) {
  455                 unit->intrs[DMAR_INTR_QI].name = "qi";
  456                 unit->intrs[DMAR_INTR_QI].irq_rid = DMAR_QI_IRQ_RID;
  457                 unit->intrs[DMAR_INTR_QI].handler = dmar_qi_intr;
  458                 unit->intrs[DMAR_INTR_QI].msi_data_reg = DMAR_IEDATA_REG;
  459                 unit->intrs[DMAR_INTR_QI].msi_addr_reg = DMAR_IEADDR_REG;
  460                 unit->intrs[DMAR_INTR_QI].msi_uaddr_reg = DMAR_IEUADDR_REG;
  461                 unit->intrs[DMAR_INTR_QI].enable_intr = dmar_enable_qi_intr;
  462                 unit->intrs[DMAR_INTR_QI].disable_intr = dmar_disable_qi_intr;
  463                 error = dmar_alloc_irq(dev, unit, DMAR_INTR_QI);
  464                 if (error != 0) {
  465                         dmar_release_resources(dev, unit);
  466                         return (error);
  467                 }
  468         }
  469 
  470         mtx_init(&unit->iommu.lock, "dmarhw", NULL, MTX_DEF);
  471         unit->domids = new_unrhdr(0, dmar_nd2mask(DMAR_CAP_ND(unit->hw_cap)),
  472             &unit->iommu.lock);
  473         LIST_INIT(&unit->domains);
  474 
  475         /*
  476          * 9.2 "Context Entry":
  477          * When Caching Mode (CM) field is reported as Set, the
  478          * domain-id value of zero is architecturally reserved.
  479          * Software must not use domain-id value of zero
  480          * when CM is Set.
  481          */
  482         if ((unit->hw_cap & DMAR_CAP_CM) != 0)
  483                 alloc_unr_specific(unit->domids, 0);
  484 
  485         unit->ctx_obj = vm_pager_allocate(OBJT_PHYS, NULL, IDX_TO_OFF(1 +
  486             DMAR_CTX_CNT), 0, 0, NULL);
  487 
  488         /*
  489          * Allocate and load the root entry table pointer.  Enable the
  490          * address translation after the required invalidations are
  491          * done.
  492          */
  493         dmar_pgalloc(unit->ctx_obj, 0, IOMMU_PGF_WAITOK | IOMMU_PGF_ZERO);
  494         DMAR_LOCK(unit);
  495         error = dmar_load_root_entry_ptr(unit);
  496         if (error != 0) {
  497                 DMAR_UNLOCK(unit);
  498                 dmar_release_resources(dev, unit);
  499                 return (error);
  500         }
  501         error = dmar_inv_ctx_glob(unit);
  502         if (error != 0) {
  503                 DMAR_UNLOCK(unit);
  504                 dmar_release_resources(dev, unit);
  505                 return (error);
  506         }
  507         if ((unit->hw_ecap & DMAR_ECAP_DI) != 0) {
  508                 error = dmar_inv_iotlb_glob(unit);
  509                 if (error != 0) {
  510                         DMAR_UNLOCK(unit);
  511                         dmar_release_resources(dev, unit);
  512                         return (error);
  513                 }
  514         }
  515 
  516         DMAR_UNLOCK(unit);
  517         error = dmar_init_fault_log(unit);
  518         if (error != 0) {
  519                 dmar_release_resources(dev, unit);
  520                 return (error);
  521         }
  522         error = dmar_init_qi(unit);
  523         if (error != 0) {
  524                 dmar_release_resources(dev, unit);
  525                 return (error);
  526         }
  527         error = dmar_init_irt(unit);
  528         if (error != 0) {
  529                 dmar_release_resources(dev, unit);
  530                 return (error);
  531         }
  532         error = iommu_init_busdma(&unit->iommu);
  533         if (error != 0) {
  534                 dmar_release_resources(dev, unit);
  535                 return (error);
  536         }
  537 
  538 #ifdef NOTYET
  539         DMAR_LOCK(unit);
  540         error = dmar_enable_translation(unit);
  541         if (error != 0) {
  542                 DMAR_UNLOCK(unit);
  543                 dmar_release_resources(dev, unit);
  544                 return (error);
  545         }
  546         DMAR_UNLOCK(unit);
  547 #endif
  548 
  549         return (0);
  550 }
  551 
  552 static int
  553 dmar_detach(device_t dev)
  554 {
  555 
  556         return (EBUSY);
  557 }
  558 
  559 static int
  560 dmar_suspend(device_t dev)
  561 {
  562 
  563         return (0);
  564 }
  565 
  566 static int
  567 dmar_resume(device_t dev)
  568 {
  569 
  570         /* XXXKIB */
  571         return (0);
  572 }
  573 
  574 static device_method_t dmar_methods[] = {
  575         DEVMETHOD(device_identify, dmar_identify),
  576         DEVMETHOD(device_probe, dmar_probe),
  577         DEVMETHOD(device_attach, dmar_attach),
  578         DEVMETHOD(device_detach, dmar_detach),
  579         DEVMETHOD(device_suspend, dmar_suspend),
  580         DEVMETHOD(device_resume, dmar_resume),
  581 #ifdef DEV_APIC
  582         DEVMETHOD(bus_remap_intr, dmar_remap_intr),
  583 #endif
  584         DEVMETHOD_END
  585 };
  586 
  587 static driver_t dmar_driver = {
  588         "dmar",
  589         dmar_methods,
  590         sizeof(struct dmar_unit),
  591 };
  592 
  593 DRIVER_MODULE(dmar, acpi, dmar_driver, dmar_devclass, 0, 0);
  594 MODULE_DEPEND(dmar, acpi, 1, 1, 1);
  595 
  596 static void
  597 dmar_print_path(int busno, int depth, const ACPI_DMAR_PCI_PATH *path)
  598 {
  599         int i;
  600 
  601         printf("[%d, ", busno);
  602         for (i = 0; i < depth; i++) {
  603                 if (i != 0)
  604                         printf(", ");
  605                 printf("(%d, %d)", path[i].Device, path[i].Function);
  606         }
  607         printf("]");
  608 }
  609 
  610 int
  611 dmar_dev_depth(device_t child)
  612 {
  613         devclass_t pci_class;
  614         device_t bus, pcib;
  615         int depth;
  616 
  617         pci_class = devclass_find("pci");
  618         for (depth = 1; ; depth++) {
  619                 bus = device_get_parent(child);
  620                 pcib = device_get_parent(bus);
  621                 if (device_get_devclass(device_get_parent(pcib)) !=
  622                     pci_class)
  623                         return (depth);
  624                 child = pcib;
  625         }
  626 }
  627 
  628 void
  629 dmar_dev_path(device_t child, int *busno, void *path1, int depth)
  630 {
  631         devclass_t pci_class;
  632         device_t bus, pcib;
  633         ACPI_DMAR_PCI_PATH *path;
  634 
  635         pci_class = devclass_find("pci");
  636         path = path1;
  637         for (depth--; depth != -1; depth--) {
  638                 path[depth].Device = pci_get_slot(child);
  639                 path[depth].Function = pci_get_function(child);
  640                 bus = device_get_parent(child);
  641                 pcib = device_get_parent(bus);
  642                 if (device_get_devclass(device_get_parent(pcib)) !=
  643                     pci_class) {
  644                         /* reached a host bridge */
  645                         *busno = pcib_get_bus(bus);
  646                         return;
  647                 }
  648                 child = pcib;
  649         }
  650         panic("wrong depth");
  651 }
  652 
  653 static int
  654 dmar_match_pathes(int busno1, const ACPI_DMAR_PCI_PATH *path1, int depth1,
  655     int busno2, const ACPI_DMAR_PCI_PATH *path2, int depth2,
  656     enum AcpiDmarScopeType scope_type)
  657 {
  658         int i, depth;
  659 
  660         if (busno1 != busno2)
  661                 return (0);
  662         if (scope_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && depth1 != depth2)
  663                 return (0);
  664         depth = depth1;
  665         if (depth2 < depth)
  666                 depth = depth2;
  667         for (i = 0; i < depth; i++) {
  668                 if (path1[i].Device != path2[i].Device ||
  669                     path1[i].Function != path2[i].Function)
  670                         return (0);
  671         }
  672         return (1);
  673 }
  674 
  675 static int
  676 dmar_match_devscope(ACPI_DMAR_DEVICE_SCOPE *devscope, int dev_busno,
  677     const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len)
  678 {
  679         ACPI_DMAR_PCI_PATH *path;
  680         int path_len;
  681 
  682         if (devscope->Length < sizeof(*devscope)) {
  683                 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n",
  684                     devscope->Length);
  685                 return (-1);
  686         }
  687         if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
  688             devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_BRIDGE)
  689                 return (0);
  690         path_len = devscope->Length - sizeof(*devscope);
  691         if (path_len % 2 != 0) {
  692                 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n",
  693                     devscope->Length);
  694                 return (-1);
  695         }
  696         path_len /= 2;
  697         path = (ACPI_DMAR_PCI_PATH *)(devscope + 1);
  698         if (path_len == 0) {
  699                 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n",
  700                     devscope->Length);
  701                 return (-1);
  702         }
  703 
  704         return (dmar_match_pathes(devscope->Bus, path, path_len, dev_busno,
  705             dev_path, dev_path_len, devscope->EntryType));
  706 }
  707 
  708 static bool
  709 dmar_match_by_path(struct dmar_unit *unit, int dev_domain, int dev_busno,
  710     const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len, const char **banner)
  711 {
  712         ACPI_DMAR_HARDWARE_UNIT *dmarh;
  713         ACPI_DMAR_DEVICE_SCOPE *devscope;
  714         char *ptr, *ptrend;
  715         int match;
  716 
  717         dmarh = dmar_find_by_index(unit->iommu.unit);
  718         if (dmarh == NULL)
  719                 return (false);
  720         if (dmarh->Segment != dev_domain)
  721                 return (false);
  722         if ((dmarh->Flags & ACPI_DMAR_INCLUDE_ALL) != 0) {
  723                 if (banner != NULL)
  724                         *banner = "INCLUDE_ALL";
  725                 return (true);
  726         }
  727         ptr = (char *)dmarh + sizeof(*dmarh);
  728         ptrend = (char *)dmarh + dmarh->Header.Length;
  729         while (ptr < ptrend) {
  730                 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
  731                 ptr += devscope->Length;
  732                 match = dmar_match_devscope(devscope, dev_busno, dev_path,
  733                     dev_path_len);
  734                 if (match == -1)
  735                         return (false);
  736                 if (match == 1) {
  737                         if (banner != NULL)
  738                                 *banner = "specific match";
  739                         return (true);
  740                 }
  741         }
  742         return (false);
  743 }
  744 
  745 static struct dmar_unit *
  746 dmar_find_by_scope(int dev_domain, int dev_busno,
  747     const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len)
  748 {
  749         struct dmar_unit *unit;
  750         int i;
  751 
  752         for (i = 0; i < dmar_devcnt; i++) {
  753                 if (dmar_devs[i] == NULL)
  754                         continue;
  755                 unit = device_get_softc(dmar_devs[i]);
  756                 if (dmar_match_by_path(unit, dev_domain, dev_busno, dev_path,
  757                     dev_path_len, NULL))
  758                         return (unit);
  759         }
  760         return (NULL);
  761 }
  762 
  763 struct dmar_unit *
  764 dmar_find(device_t dev, bool verbose)
  765 {
  766         struct dmar_unit *unit;
  767         const char *banner;
  768         int i, dev_domain, dev_busno, dev_path_len;
  769 
  770         /*
  771          * This function can only handle PCI(e) devices.
  772          */
  773         if (device_get_devclass(device_get_parent(dev)) !=
  774             devclass_find("pci"))
  775                 return (NULL);
  776 
  777         dev_domain = pci_get_domain(dev);
  778         dev_path_len = dmar_dev_depth(dev);
  779         ACPI_DMAR_PCI_PATH dev_path[dev_path_len];
  780         dmar_dev_path(dev, &dev_busno, dev_path, dev_path_len);
  781         banner = "";
  782 
  783         for (i = 0; i < dmar_devcnt; i++) {
  784                 if (dmar_devs[i] == NULL)
  785                         continue;
  786                 unit = device_get_softc(dmar_devs[i]);
  787                 if (dmar_match_by_path(unit, dev_domain, dev_busno,
  788                     dev_path, dev_path_len, &banner))
  789                         break;
  790         }
  791         if (i == dmar_devcnt)
  792                 return (NULL);
  793 
  794         if (verbose) {
  795                 device_printf(dev, "pci%d:%d:%d:%d matched dmar%d by %s",
  796                     dev_domain, pci_get_bus(dev), pci_get_slot(dev),
  797                     pci_get_function(dev), unit->iommu.unit, banner);
  798                 printf(" scope path ");
  799                 dmar_print_path(dev_busno, dev_path_len, dev_path);
  800                 printf("\n");
  801         }
  802         return (unit);
  803 }
  804 
  805 static struct dmar_unit *
  806 dmar_find_nonpci(u_int id, u_int entry_type, uint16_t *rid)
  807 {
  808         device_t dmar_dev;
  809         struct dmar_unit *unit;
  810         ACPI_DMAR_HARDWARE_UNIT *dmarh;
  811         ACPI_DMAR_DEVICE_SCOPE *devscope;
  812         ACPI_DMAR_PCI_PATH *path;
  813         char *ptr, *ptrend;
  814 #ifdef DEV_APIC
  815         int error;
  816 #endif
  817         int i;
  818 
  819         for (i = 0; i < dmar_devcnt; i++) {
  820                 dmar_dev = dmar_devs[i];
  821                 if (dmar_dev == NULL)
  822                         continue;
  823                 unit = (struct dmar_unit *)device_get_softc(dmar_dev);
  824                 dmarh = dmar_find_by_index(i);
  825                 if (dmarh == NULL)
  826                         continue;
  827                 ptr = (char *)dmarh + sizeof(*dmarh);
  828                 ptrend = (char *)dmarh + dmarh->Header.Length;
  829                 for (;;) {
  830                         if (ptr >= ptrend)
  831                                 break;
  832                         devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
  833                         ptr += devscope->Length;
  834                         if (devscope->EntryType != entry_type)
  835                                 continue;
  836                         if (devscope->EnumerationId != id)
  837                                 continue;
  838 #ifdef DEV_APIC
  839                         if (entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) {
  840                                 error = ioapic_get_rid(id, rid);
  841                                 /*
  842                                  * If our IOAPIC has PCI bindings then
  843                                  * use the PCI device rid.
  844                                  */
  845                                 if (error == 0)
  846                                         return (unit);
  847                         }
  848 #endif
  849                         if (devscope->Length - sizeof(ACPI_DMAR_DEVICE_SCOPE)
  850                             == 2) {
  851                                 if (rid != NULL) {
  852                                         path = (ACPI_DMAR_PCI_PATH *)
  853                                             (devscope + 1);
  854                                         *rid = PCI_RID(devscope->Bus,
  855                                             path->Device, path->Function);
  856                                 }
  857                                 return (unit);
  858                         }
  859                         printf(
  860                            "dmar_find_nonpci: id %d type %d path length != 2\n",
  861                             id, entry_type);
  862                         break;
  863                 }
  864         }
  865         return (NULL);
  866 }
  867 
  868 struct dmar_unit *
  869 dmar_find_hpet(device_t dev, uint16_t *rid)
  870 {
  871 
  872         return (dmar_find_nonpci(hpet_get_uid(dev), ACPI_DMAR_SCOPE_TYPE_HPET,
  873             rid));
  874 }
  875 
  876 struct dmar_unit *
  877 dmar_find_ioapic(u_int apic_id, uint16_t *rid)
  878 {
  879 
  880         return (dmar_find_nonpci(apic_id, ACPI_DMAR_SCOPE_TYPE_IOAPIC, rid));
  881 }
  882 
  883 struct rmrr_iter_args {
  884         struct dmar_domain *domain;
  885         int dev_domain;
  886         int dev_busno;
  887         const ACPI_DMAR_PCI_PATH *dev_path;
  888         int dev_path_len;
  889         struct iommu_map_entries_tailq *rmrr_entries;
  890 };
  891 
  892 static int
  893 dmar_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
  894 {
  895         struct rmrr_iter_args *ria;
  896         ACPI_DMAR_RESERVED_MEMORY *resmem;
  897         ACPI_DMAR_DEVICE_SCOPE *devscope;
  898         struct iommu_map_entry *entry;
  899         char *ptr, *ptrend;
  900         int match;
  901 
  902         if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY)
  903                 return (1);
  904 
  905         ria = arg;
  906         resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh;
  907         if (resmem->Segment != ria->dev_domain)
  908                 return (1);
  909 
  910         ptr = (char *)resmem + sizeof(*resmem);
  911         ptrend = (char *)resmem + resmem->Header.Length;
  912         for (;;) {
  913                 if (ptr >= ptrend)
  914                         break;
  915                 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
  916                 ptr += devscope->Length;
  917                 match = dmar_match_devscope(devscope, ria->dev_busno,
  918                     ria->dev_path, ria->dev_path_len);
  919                 if (match == 1) {
  920                         entry = iommu_gas_alloc_entry(DOM2IODOM(ria->domain),
  921                             IOMMU_PGF_WAITOK);
  922                         entry->start = resmem->BaseAddress;
  923                         /* The RMRR entry end address is inclusive. */
  924                         entry->end = resmem->EndAddress;
  925                         TAILQ_INSERT_TAIL(ria->rmrr_entries, entry,
  926                             unroll_link);
  927                 }
  928         }
  929 
  930         return (1);
  931 }
  932 
  933 void
  934 dmar_dev_parse_rmrr(struct dmar_domain *domain, int dev_domain, int dev_busno,
  935     const void *dev_path, int dev_path_len,
  936     struct iommu_map_entries_tailq *rmrr_entries)
  937 {
  938         struct rmrr_iter_args ria;
  939 
  940         ria.domain = domain;
  941         ria.dev_domain = dev_domain;
  942         ria.dev_busno = dev_busno;
  943         ria.dev_path = (const ACPI_DMAR_PCI_PATH *)dev_path;
  944         ria.dev_path_len = dev_path_len;
  945         ria.rmrr_entries = rmrr_entries;
  946         dmar_iterate_tbl(dmar_rmrr_iter, &ria);
  947 }
  948 
  949 struct inst_rmrr_iter_args {
  950         struct dmar_unit *dmar;
  951 };
  952 
  953 static device_t
  954 dmar_path_dev(int segment, int path_len, int busno,
  955     const ACPI_DMAR_PCI_PATH *path, uint16_t *rid)
  956 {
  957         device_t dev;
  958         int i;
  959 
  960         dev = NULL;
  961         for (i = 0; i < path_len; i++) {
  962                 dev = pci_find_dbsf(segment, busno, path->Device,
  963                     path->Function);
  964                 if (i != path_len - 1) {
  965                         busno = pci_cfgregread(busno, path->Device,
  966                             path->Function, PCIR_SECBUS_1, 1);
  967                         path++;
  968                 }
  969         }
  970         *rid = PCI_RID(busno, path->Device, path->Function);
  971         return (dev);
  972 }
  973 
  974 static int
  975 dmar_inst_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
  976 {
  977         const ACPI_DMAR_RESERVED_MEMORY *resmem;
  978         const ACPI_DMAR_DEVICE_SCOPE *devscope;
  979         struct inst_rmrr_iter_args *iria;
  980         const char *ptr, *ptrend;
  981         device_t dev;
  982         struct dmar_unit *unit;
  983         int dev_path_len;
  984         uint16_t rid;
  985 
  986         iria = arg;
  987 
  988         if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY)
  989                 return (1);
  990 
  991         resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh;
  992         if (resmem->Segment != iria->dmar->segment)
  993                 return (1);
  994 
  995         ptr = (const char *)resmem + sizeof(*resmem);
  996         ptrend = (const char *)resmem + resmem->Header.Length;
  997         for (;;) {
  998                 if (ptr >= ptrend)
  999                         break;
 1000                 devscope = (const ACPI_DMAR_DEVICE_SCOPE *)ptr;
 1001                 ptr += devscope->Length;
 1002                 /* XXXKIB bridge */
 1003                 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT)
 1004                         continue;
 1005                 rid = 0;
 1006                 dev_path_len = (devscope->Length -
 1007                     sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2;
 1008                 dev = dmar_path_dev(resmem->Segment, dev_path_len,
 1009                     devscope->Bus,
 1010                     (const ACPI_DMAR_PCI_PATH *)(devscope + 1), &rid);
 1011                 if (dev == NULL) {
 1012                         if (bootverbose) {
 1013                                 printf("dmar%d no dev found for RMRR "
 1014                                     "[%#jx, %#jx] rid %#x scope path ",
 1015                                      iria->dmar->iommu.unit,
 1016                                      (uintmax_t)resmem->BaseAddress,
 1017                                      (uintmax_t)resmem->EndAddress,
 1018                                      rid);
 1019                                 dmar_print_path(devscope->Bus, dev_path_len,
 1020                                     (const ACPI_DMAR_PCI_PATH *)(devscope + 1));
 1021                                 printf("\n");
 1022                         }
 1023                         unit = dmar_find_by_scope(resmem->Segment,
 1024                             devscope->Bus,
 1025                             (const ACPI_DMAR_PCI_PATH *)(devscope + 1),
 1026                             dev_path_len);
 1027                         if (iria->dmar != unit)
 1028                                 continue;
 1029                         dmar_get_ctx_for_devpath(iria->dmar, rid,
 1030                             resmem->Segment, devscope->Bus, 
 1031                             (const ACPI_DMAR_PCI_PATH *)(devscope + 1),
 1032                             dev_path_len, false, true);
 1033                 } else {
 1034                         unit = dmar_find(dev, false);
 1035                         if (iria->dmar != unit)
 1036                                 continue;
 1037                         iommu_instantiate_ctx(&(iria)->dmar->iommu,
 1038                             dev, true);
 1039                 }
 1040         }
 1041 
 1042         return (1);
 1043 
 1044 }
 1045 
 1046 /*
 1047  * Pre-create all contexts for the DMAR which have RMRR entries.
 1048  */
 1049 int
 1050 dmar_instantiate_rmrr_ctxs(struct iommu_unit *unit)
 1051 {
 1052         struct dmar_unit *dmar;
 1053         struct inst_rmrr_iter_args iria;
 1054         int error;
 1055 
 1056         dmar = IOMMU2DMAR(unit);
 1057 
 1058         if (!dmar_barrier_enter(dmar, DMAR_BARRIER_RMRR))
 1059                 return (0);
 1060 
 1061         error = 0;
 1062         iria.dmar = dmar;
 1063         dmar_iterate_tbl(dmar_inst_rmrr_iter, &iria);
 1064         DMAR_LOCK(dmar);
 1065         if (!LIST_EMPTY(&dmar->domains)) {
 1066                 KASSERT((dmar->hw_gcmd & DMAR_GCMD_TE) == 0,
 1067             ("dmar%d: RMRR not handled but translation is already enabled",
 1068                     dmar->iommu.unit));
 1069                 error = dmar_enable_translation(dmar);
 1070                 if (bootverbose) {
 1071                         if (error == 0) {
 1072                                 printf("dmar%d: enabled translation\n",
 1073                                     dmar->iommu.unit);
 1074                         } else {
 1075                                 printf("dmar%d: enabling translation failed, "
 1076                                     "error %d\n", dmar->iommu.unit, error);
 1077                         }
 1078                 }
 1079         }
 1080         dmar_barrier_exit(dmar, DMAR_BARRIER_RMRR);
 1081         return (error);
 1082 }
 1083 
 1084 #ifdef DDB
 1085 #include <ddb/ddb.h>
 1086 #include <ddb/db_lex.h>
 1087 
 1088 static void
 1089 dmar_print_domain_entry(const struct iommu_map_entry *entry)
 1090 {
 1091         struct iommu_map_entry *l, *r;
 1092 
 1093         db_printf(
 1094             "    start %jx end %jx first %jx last %jx free_down %jx flags %x ",
 1095             entry->start, entry->end, entry->first, entry->last,
 1096             entry->free_down, entry->flags);
 1097         db_printf("left ");
 1098         l = RB_LEFT(entry, rb_entry);
 1099         if (l == NULL)
 1100                 db_printf("NULL ");
 1101         else
 1102                 db_printf("%jx ", l->start);
 1103         db_printf("right ");
 1104         r = RB_RIGHT(entry, rb_entry);
 1105         if (r == NULL)
 1106                 db_printf("NULL");
 1107         else
 1108                 db_printf("%jx", r->start);
 1109         db_printf("\n");
 1110 }
 1111 
 1112 static void
 1113 dmar_print_ctx(struct dmar_ctx *ctx)
 1114 {
 1115 
 1116         db_printf(
 1117             "    @%p pci%d:%d:%d refs %d flags %x loads %lu unloads %lu\n",
 1118             ctx, pci_get_bus(ctx->context.tag->owner),
 1119             pci_get_slot(ctx->context.tag->owner),
 1120             pci_get_function(ctx->context.tag->owner), ctx->refs,
 1121             ctx->context.flags, ctx->context.loads, ctx->context.unloads);
 1122 }
 1123 
 1124 static void
 1125 dmar_print_domain(struct dmar_domain *domain, bool show_mappings)
 1126 {
 1127         struct iommu_domain *iodom;
 1128         struct iommu_map_entry *entry;
 1129         struct dmar_ctx *ctx;
 1130 
 1131         iodom = DOM2IODOM(domain);
 1132 
 1133         db_printf(
 1134             "  @%p dom %d mgaw %d agaw %d pglvl %d end %jx refs %d\n"
 1135             "   ctx_cnt %d flags %x pgobj %p map_ents %u\n",
 1136             domain, domain->domain, domain->mgaw, domain->agaw, domain->pglvl,
 1137             (uintmax_t)domain->iodom.end, domain->refs, domain->ctx_cnt,
 1138             domain->iodom.flags, domain->pgtbl_obj, domain->iodom.entries_cnt);
 1139         if (!LIST_EMPTY(&domain->contexts)) {
 1140                 db_printf("  Contexts:\n");
 1141                 LIST_FOREACH(ctx, &domain->contexts, link)
 1142                         dmar_print_ctx(ctx);
 1143         }
 1144         if (!show_mappings)
 1145                 return;
 1146         db_printf("    mapped:\n");
 1147         RB_FOREACH(entry, iommu_gas_entries_tree, &iodom->rb_root) {
 1148                 dmar_print_domain_entry(entry);
 1149                 if (db_pager_quit)
 1150                         break;
 1151         }
 1152         if (db_pager_quit)
 1153                 return;
 1154         db_printf("    unloading:\n");
 1155         TAILQ_FOREACH(entry, &domain->iodom.unload_entries, dmamap_link) {
 1156                 dmar_print_domain_entry(entry);
 1157                 if (db_pager_quit)
 1158                         break;
 1159         }
 1160 }
 1161 
 1162 DB_FUNC(dmar_domain, db_dmar_print_domain, db_show_table, CS_OWN, NULL)
 1163 {
 1164         struct dmar_unit *unit;
 1165         struct dmar_domain *domain;
 1166         struct dmar_ctx *ctx;
 1167         bool show_mappings, valid;
 1168         int pci_domain, bus, device, function, i, t;
 1169         db_expr_t radix;
 1170 
 1171         valid = false;
 1172         radix = db_radix;
 1173         db_radix = 10;
 1174         t = db_read_token();
 1175         if (t == tSLASH) {
 1176                 t = db_read_token();
 1177                 if (t != tIDENT) {
 1178                         db_printf("Bad modifier\n");
 1179                         db_radix = radix;
 1180                         db_skip_to_eol();
 1181                         return;
 1182                 }
 1183                 show_mappings = strchr(db_tok_string, 'm') != NULL;
 1184                 t = db_read_token();
 1185         } else {
 1186                 show_mappings = false;
 1187         }
 1188         if (t == tNUMBER) {
 1189                 pci_domain = db_tok_number;
 1190                 t = db_read_token();
 1191                 if (t == tNUMBER) {
 1192                         bus = db_tok_number;
 1193                         t = db_read_token();
 1194                         if (t == tNUMBER) {
 1195                                 device = db_tok_number;
 1196                                 t = db_read_token();
 1197                                 if (t == tNUMBER) {
 1198                                         function = db_tok_number;
 1199                                         valid = true;
 1200                                 }
 1201                         }
 1202                 }
 1203         }
 1204                         db_radix = radix;
 1205         db_skip_to_eol();
 1206         if (!valid) {
 1207                 db_printf("usage: show dmar_domain [/m] "
 1208                     "<domain> <bus> <device> <func>\n");
 1209                 return;
 1210         }
 1211         for (i = 0; i < dmar_devcnt; i++) {
 1212                 unit = device_get_softc(dmar_devs[i]);
 1213                 LIST_FOREACH(domain, &unit->domains, link) {
 1214                         LIST_FOREACH(ctx, &domain->contexts, link) {
 1215                                 if (pci_domain == unit->segment && 
 1216                                     bus == pci_get_bus(ctx->context.tag->owner) &&
 1217                                     device ==
 1218                                     pci_get_slot(ctx->context.tag->owner) &&
 1219                                     function ==
 1220                                     pci_get_function(ctx->context.tag->owner)) {
 1221                                         dmar_print_domain(domain,
 1222                                             show_mappings);
 1223                                         goto out;
 1224                                 }
 1225                         }
 1226                 }
 1227         }
 1228 out:;
 1229 }
 1230 
 1231 static void
 1232 dmar_print_one(int idx, bool show_domains, bool show_mappings)
 1233 {
 1234         struct dmar_unit *unit;
 1235         struct dmar_domain *domain;
 1236         int i, frir;
 1237 
 1238         unit = device_get_softc(dmar_devs[idx]);
 1239         db_printf("dmar%d at %p, root at 0x%jx, ver 0x%x\n", unit->iommu.unit,
 1240             unit, dmar_read8(unit, DMAR_RTADDR_REG),
 1241             dmar_read4(unit, DMAR_VER_REG));
 1242         db_printf("cap 0x%jx ecap 0x%jx gsts 0x%x fsts 0x%x fectl 0x%x\n",
 1243             (uintmax_t)dmar_read8(unit, DMAR_CAP_REG),
 1244             (uintmax_t)dmar_read8(unit, DMAR_ECAP_REG),
 1245             dmar_read4(unit, DMAR_GSTS_REG),
 1246             dmar_read4(unit, DMAR_FSTS_REG),
 1247             dmar_read4(unit, DMAR_FECTL_REG));
 1248         if (unit->ir_enabled) {
 1249                 db_printf("ir is enabled; IRT @%p phys 0x%jx maxcnt %d\n",
 1250                     unit->irt, (uintmax_t)unit->irt_phys, unit->irte_cnt);
 1251         }
 1252         db_printf("fed 0x%x fea 0x%x feua 0x%x\n",
 1253             dmar_read4(unit, DMAR_FEDATA_REG),
 1254             dmar_read4(unit, DMAR_FEADDR_REG),
 1255             dmar_read4(unit, DMAR_FEUADDR_REG));
 1256         db_printf("primary fault log:\n");
 1257         for (i = 0; i < DMAR_CAP_NFR(unit->hw_cap); i++) {
 1258                 frir = (DMAR_CAP_FRO(unit->hw_cap) + i) * 16;
 1259                 db_printf("  %d at 0x%x: %jx %jx\n", i, frir,
 1260                     (uintmax_t)dmar_read8(unit, frir),
 1261                     (uintmax_t)dmar_read8(unit, frir + 8));
 1262         }
 1263         if (DMAR_HAS_QI(unit)) {
 1264                 db_printf("ied 0x%x iea 0x%x ieua 0x%x\n",
 1265                     dmar_read4(unit, DMAR_IEDATA_REG),
 1266                     dmar_read4(unit, DMAR_IEADDR_REG),
 1267                     dmar_read4(unit, DMAR_IEUADDR_REG));
 1268                 if (unit->qi_enabled) {
 1269                         db_printf("qi is enabled: queue @0x%jx (IQA 0x%jx) "
 1270                             "size 0x%jx\n"
 1271                     "  head 0x%x tail 0x%x avail 0x%x status 0x%x ctrl 0x%x\n"
 1272                     "  hw compl 0x%x@%p/phys@%jx next seq 0x%x gen 0x%x\n",
 1273                             (uintmax_t)unit->inv_queue,
 1274                             (uintmax_t)dmar_read8(unit, DMAR_IQA_REG),
 1275                             (uintmax_t)unit->inv_queue_size,
 1276                             dmar_read4(unit, DMAR_IQH_REG),
 1277                             dmar_read4(unit, DMAR_IQT_REG),
 1278                             unit->inv_queue_avail,
 1279                             dmar_read4(unit, DMAR_ICS_REG),
 1280                             dmar_read4(unit, DMAR_IECTL_REG),
 1281                             unit->inv_waitd_seq_hw,
 1282                             &unit->inv_waitd_seq_hw,
 1283                             (uintmax_t)unit->inv_waitd_seq_hw_phys,
 1284                             unit->inv_waitd_seq,
 1285                             unit->inv_waitd_gen);
 1286                 } else {
 1287                         db_printf("qi is disabled\n");
 1288                 }
 1289         }
 1290         if (show_domains) {
 1291                 db_printf("domains:\n");
 1292                 LIST_FOREACH(domain, &unit->domains, link) {
 1293                         dmar_print_domain(domain, show_mappings);
 1294                         if (db_pager_quit)
 1295                                 break;
 1296                 }
 1297         }
 1298 }
 1299 
 1300 DB_SHOW_COMMAND(dmar, db_dmar_print)
 1301 {
 1302         bool show_domains, show_mappings;
 1303 
 1304         show_domains = strchr(modif, 'd') != NULL;
 1305         show_mappings = strchr(modif, 'm') != NULL;
 1306         if (!have_addr) {
 1307                 db_printf("usage: show dmar [/d] [/m] index\n");
 1308                 return;
 1309         }
 1310         dmar_print_one((int)addr, show_domains, show_mappings);
 1311 }
 1312 
 1313 DB_SHOW_ALL_COMMAND(dmars, db_show_all_dmars)
 1314 {
 1315         int i;
 1316         bool show_domains, show_mappings;
 1317 
 1318         show_domains = strchr(modif, 'd') != NULL;
 1319         show_mappings = strchr(modif, 'm') != NULL;
 1320 
 1321         for (i = 0; i < dmar_devcnt; i++) {
 1322                 dmar_print_one(i, show_domains, show_mappings);
 1323                 if (db_pager_quit)
 1324                         break;
 1325         }
 1326 }
 1327 #endif
 1328 
 1329 struct iommu_unit *
 1330 iommu_find(device_t dev, bool verbose)
 1331 {
 1332         struct dmar_unit *dmar;
 1333 
 1334         dmar = dmar_find(dev, verbose);
 1335 
 1336         return (&dmar->iommu);
 1337 }

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