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sys/x86/iommu/intel_idpgtbl.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013 The FreeBSD Foundation 5 * 6 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 7 * under sponsorship from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/bus.h> 38 #include <sys/interrupt.h> 39 #include <sys/kernel.h> 40 #include <sys/ktr.h> 41 #include <sys/lock.h> 42 #include <sys/memdesc.h> 43 #include <sys/mutex.h> 44 #include <sys/proc.h> 45 #include <sys/rwlock.h> 46 #include <sys/rman.h> 47 #include <sys/sf_buf.h> 48 #include <sys/sysctl.h> 49 #include <sys/taskqueue.h> 50 #include <sys/tree.h> 51 #include <sys/uio.h> 52 #include <sys/vmem.h> 53 #include <vm/vm.h> 54 #include <vm/vm_extern.h> 55 #include <vm/vm_kern.h> 56 #include <vm/vm_object.h> 57 #include <vm/vm_page.h> 58 #include <vm/vm_pager.h> 59 #include <vm/vm_map.h> 60 #include <dev/pci/pcireg.h> 61 #include <machine/atomic.h> 62 #include <machine/bus.h> 63 #include <machine/cpu.h> 64 #include <machine/md_var.h> 65 #include <machine/specialreg.h> 66 #include <x86/include/busdma_impl.h> 67 #include <dev/iommu/busdma_iommu.h> 68 #include <x86/iommu/intel_reg.h> 69 #include <x86/iommu/intel_dmar.h> 70 71 static int domain_unmap_buf_locked(struct dmar_domain *domain, 72 iommu_gaddr_t base, iommu_gaddr_t size, int flags); 73 74 /* 75 * The cache of the identity mapping page tables for the DMARs. Using 76 * the cache saves significant amount of memory for page tables by 77 * reusing the page tables, since usually DMARs are identical and have 78 * the same capabilities. Still, cache records the information needed 79 * to match DMAR capabilities and page table format, to correctly 80 * handle different DMARs. 81 */ 82 83 struct idpgtbl { 84 iommu_gaddr_t maxaddr; /* Page table covers the guest address 85 range [0..maxaddr) */ 86 int pglvl; /* Total page table levels ignoring 87 superpages */ 88 int leaf; /* The last materialized page table 89 level, it is non-zero if superpages 90 are supported */ 91 vm_object_t pgtbl_obj; /* The page table pages */ 92 LIST_ENTRY(idpgtbl) link; 93 }; 94 95 static struct sx idpgtbl_lock; 96 SX_SYSINIT(idpgtbl, &idpgtbl_lock, "idpgtbl"); 97 static LIST_HEAD(, idpgtbl) idpgtbls = LIST_HEAD_INITIALIZER(idpgtbls); 98 static MALLOC_DEFINE(M_DMAR_IDPGTBL, "dmar_idpgtbl", 99 "Intel DMAR Identity mappings cache elements"); 100 101 /* 102 * Build the next level of the page tables for the identity mapping. 103 * - lvl is the level to build; 104 * - idx is the index of the page table page in the pgtbl_obj, which is 105 * being allocated filled now; 106 * - addr is the starting address in the bus address space which is 107 * mapped by the page table page. 108 */ 109 static void 110 domain_idmap_nextlvl(struct idpgtbl *tbl, int lvl, vm_pindex_t idx, 111 iommu_gaddr_t addr) 112 { 113 vm_page_t m1; 114 dmar_pte_t *pte; 115 struct sf_buf *sf; 116 iommu_gaddr_t f, pg_sz; 117 vm_pindex_t base; 118 int i; 119 120 VM_OBJECT_ASSERT_LOCKED(tbl->pgtbl_obj); 121 if (addr >= tbl->maxaddr) 122 return; 123 (void)dmar_pgalloc(tbl->pgtbl_obj, idx, IOMMU_PGF_OBJL | 124 IOMMU_PGF_WAITOK | IOMMU_PGF_ZERO); 125 base = idx * DMAR_NPTEPG + 1; /* Index of the first child page of idx */ 126 pg_sz = pglvl_page_size(tbl->pglvl, lvl); 127 if (lvl != tbl->leaf) { 128 for (i = 0, f = addr; i < DMAR_NPTEPG; i++, f += pg_sz) 129 domain_idmap_nextlvl(tbl, lvl + 1, base + i, f); 130 } 131 VM_OBJECT_WUNLOCK(tbl->pgtbl_obj); 132 pte = dmar_map_pgtbl(tbl->pgtbl_obj, idx, IOMMU_PGF_WAITOK, &sf); 133 if (lvl == tbl->leaf) { 134 for (i = 0, f = addr; i < DMAR_NPTEPG; i++, f += pg_sz) { 135 if (f >= tbl->maxaddr) 136 break; 137 pte[i].pte = (DMAR_PTE_ADDR_MASK & f) | 138 DMAR_PTE_R | DMAR_PTE_W; 139 } 140 } else { 141 for (i = 0, f = addr; i < DMAR_NPTEPG; i++, f += pg_sz) { 142 if (f >= tbl->maxaddr) 143 break; 144 m1 = dmar_pgalloc(tbl->pgtbl_obj, base + i, 145 IOMMU_PGF_NOALLOC); 146 KASSERT(m1 != NULL, ("lost page table page")); 147 pte[i].pte = (DMAR_PTE_ADDR_MASK & 148 VM_PAGE_TO_PHYS(m1)) | DMAR_PTE_R | DMAR_PTE_W; 149 } 150 } 151 /* domain_get_idmap_pgtbl flushes CPU cache if needed. */ 152 dmar_unmap_pgtbl(sf); 153 VM_OBJECT_WLOCK(tbl->pgtbl_obj); 154 } 155 156 /* 157 * Find a ready and compatible identity-mapping page table in the 158 * cache. If not found, populate the identity-mapping page table for 159 * the context, up to the maxaddr. The maxaddr byte is allowed to be 160 * not mapped, which is aligned with the definition of Maxmem as the 161 * highest usable physical address + 1. If superpages are used, the 162 * maxaddr is typically mapped. 163 */ 164 vm_object_t 165 domain_get_idmap_pgtbl(struct dmar_domain *domain, iommu_gaddr_t maxaddr) 166 { 167 struct dmar_unit *unit; 168 struct idpgtbl *tbl; 169 vm_object_t res; 170 vm_page_t m; 171 int leaf, i; 172 173 leaf = 0; /* silence gcc */ 174 175 /* 176 * First, determine where to stop the paging structures. 177 */ 178 for (i = 0; i < domain->pglvl; i++) { 179 if (i == domain->pglvl - 1 || domain_is_sp_lvl(domain, i)) { 180 leaf = i; 181 break; 182 } 183 } 184 185 /* 186 * Search the cache for a compatible page table. Qualified 187 * page table must map up to maxaddr, its level must be 188 * supported by the DMAR and leaf should be equal to the 189 * calculated value. The later restriction could be lifted 190 * but I believe it is currently impossible to have any 191 * deviations for existing hardware. 192 */ 193 sx_slock(&idpgtbl_lock); 194 LIST_FOREACH(tbl, &idpgtbls, link) { 195 if (tbl->maxaddr >= maxaddr && 196 dmar_pglvl_supported(domain->dmar, tbl->pglvl) && 197 tbl->leaf == leaf) { 198 res = tbl->pgtbl_obj; 199 vm_object_reference(res); 200 sx_sunlock(&idpgtbl_lock); 201 domain->pglvl = tbl->pglvl; /* XXXKIB ? */ 202 goto end; 203 } 204 } 205 206 /* 207 * Not found in cache, relock the cache into exclusive mode to 208 * be able to add element, and recheck cache again after the 209 * relock. 210 */ 211 sx_sunlock(&idpgtbl_lock); 212 sx_xlock(&idpgtbl_lock); 213 LIST_FOREACH(tbl, &idpgtbls, link) { 214 if (tbl->maxaddr >= maxaddr && 215 dmar_pglvl_supported(domain->dmar, tbl->pglvl) && 216 tbl->leaf == leaf) { 217 res = tbl->pgtbl_obj; 218 vm_object_reference(res); 219 sx_xunlock(&idpgtbl_lock); 220 domain->pglvl = tbl->pglvl; /* XXXKIB ? */ 221 return (res); 222 } 223 } 224 225 /* 226 * Still not found, create new page table. 227 */ 228 tbl = malloc(sizeof(*tbl), M_DMAR_IDPGTBL, M_WAITOK); 229 tbl->pglvl = domain->pglvl; 230 tbl->leaf = leaf; 231 tbl->maxaddr = maxaddr; 232 tbl->pgtbl_obj = vm_pager_allocate(OBJT_PHYS, NULL, 233 IDX_TO_OFF(pglvl_max_pages(tbl->pglvl)), 0, 0, NULL); 234 VM_OBJECT_WLOCK(tbl->pgtbl_obj); 235 domain_idmap_nextlvl(tbl, 0, 0, 0); 236 VM_OBJECT_WUNLOCK(tbl->pgtbl_obj); 237 LIST_INSERT_HEAD(&idpgtbls, tbl, link); 238 res = tbl->pgtbl_obj; 239 vm_object_reference(res); 240 sx_xunlock(&idpgtbl_lock); 241 242 end: 243 /* 244 * Table was found or created. 245 * 246 * If DMAR does not snoop paging structures accesses, flush 247 * CPU cache to memory. Note that dmar_unmap_pgtbl() coherent 248 * argument was possibly invalid at the time of the identity 249 * page table creation, since DMAR which was passed at the 250 * time of creation could be coherent, while current DMAR is 251 * not. 252 * 253 * If DMAR cannot look into the chipset write buffer, flush it 254 * as well. 255 */ 256 unit = domain->dmar; 257 if (!DMAR_IS_COHERENT(unit)) { 258 VM_OBJECT_WLOCK(res); 259 for (m = vm_page_lookup(res, 0); m != NULL; 260 m = vm_page_next(m)) 261 pmap_invalidate_cache_pages(&m, 1); 262 VM_OBJECT_WUNLOCK(res); 263 } 264 if ((unit->hw_cap & DMAR_CAP_RWBF) != 0) { 265 DMAR_LOCK(unit); 266 dmar_flush_write_bufs(unit); 267 DMAR_UNLOCK(unit); 268 } 269 270 return (res); 271 } 272 273 /* 274 * Return a reference to the identity mapping page table to the cache. 275 */ 276 void 277 put_idmap_pgtbl(vm_object_t obj) 278 { 279 struct idpgtbl *tbl, *tbl1; 280 vm_object_t rmobj; 281 282 sx_slock(&idpgtbl_lock); 283 KASSERT(obj->ref_count >= 2, ("lost cache reference")); 284 vm_object_deallocate(obj); 285 286 /* 287 * Cache always owns one last reference on the page table object. 288 * If there is an additional reference, object must stay. 289 */ 290 if (obj->ref_count > 1) { 291 sx_sunlock(&idpgtbl_lock); 292 return; 293 } 294 295 /* 296 * Cache reference is the last, remove cache element and free 297 * page table object, returning the page table pages to the 298 * system. 299 */ 300 sx_sunlock(&idpgtbl_lock); 301 sx_xlock(&idpgtbl_lock); 302 LIST_FOREACH_SAFE(tbl, &idpgtbls, link, tbl1) { 303 rmobj = tbl->pgtbl_obj; 304 if (rmobj->ref_count == 1) { 305 LIST_REMOVE(tbl, link); 306 atomic_subtract_int(&dmar_tbl_pagecnt, 307 rmobj->resident_page_count); 308 vm_object_deallocate(rmobj); 309 free(tbl, M_DMAR_IDPGTBL); 310 } 311 } 312 sx_xunlock(&idpgtbl_lock); 313 } 314 315 /* 316 * The core routines to map and unmap host pages at the given guest 317 * address. Support superpages. 318 */ 319 320 /* 321 * Index of the pte for the guest address base in the page table at 322 * the level lvl. 323 */ 324 static int 325 domain_pgtbl_pte_off(struct dmar_domain *domain, iommu_gaddr_t base, int lvl) 326 { 327 328 base >>= DMAR_PAGE_SHIFT + (domain->pglvl - lvl - 1) * 329 DMAR_NPTEPGSHIFT; 330 return (base & DMAR_PTEMASK); 331 } 332 333 /* 334 * Returns the page index of the page table page in the page table 335 * object, which maps the given address base at the page table level 336 * lvl. 337 */ 338 static vm_pindex_t 339 domain_pgtbl_get_pindex(struct dmar_domain *domain, iommu_gaddr_t base, int lvl) 340 { 341 vm_pindex_t idx, pidx; 342 int i; 343 344 KASSERT(lvl >= 0 && lvl < domain->pglvl, 345 ("wrong lvl %p %d", domain, lvl)); 346 347 for (pidx = idx = 0, i = 0; i < lvl; i++, pidx = idx) { 348 idx = domain_pgtbl_pte_off(domain, base, i) + 349 pidx * DMAR_NPTEPG + 1; 350 } 351 return (idx); 352 } 353 354 static dmar_pte_t * 355 domain_pgtbl_map_pte(struct dmar_domain *domain, iommu_gaddr_t base, int lvl, 356 int flags, vm_pindex_t *idxp, struct sf_buf **sf) 357 { 358 vm_page_t m; 359 struct sf_buf *sfp; 360 dmar_pte_t *pte, *ptep; 361 vm_pindex_t idx, idx1; 362 363 DMAR_DOMAIN_ASSERT_PGLOCKED(domain); 364 KASSERT((flags & IOMMU_PGF_OBJL) != 0, ("lost PGF_OBJL")); 365 366 idx = domain_pgtbl_get_pindex(domain, base, lvl); 367 if (*sf != NULL && idx == *idxp) { 368 pte = (dmar_pte_t *)sf_buf_kva(*sf); 369 } else { 370 if (*sf != NULL) 371 dmar_unmap_pgtbl(*sf); 372 *idxp = idx; 373 retry: 374 pte = dmar_map_pgtbl(domain->pgtbl_obj, idx, flags, sf); 375 if (pte == NULL) { 376 KASSERT(lvl > 0, 377 ("lost root page table page %p", domain)); 378 /* 379 * Page table page does not exist, allocate 380 * it and create a pte in the preceeding page level 381 * to reference the allocated page table page. 382 */ 383 m = dmar_pgalloc(domain->pgtbl_obj, idx, flags | 384 IOMMU_PGF_ZERO); 385 if (m == NULL) 386 return (NULL); 387 388 /* 389 * Prevent potential free while pgtbl_obj is 390 * unlocked in the recursive call to 391 * domain_pgtbl_map_pte(), if other thread did 392 * pte write and clean while the lock is 393 * dropped. 394 */ 395 m->ref_count++; 396 397 sfp = NULL; 398 ptep = domain_pgtbl_map_pte(domain, base, lvl - 1, 399 flags, &idx1, &sfp); 400 if (ptep == NULL) { 401 KASSERT(m->pindex != 0, 402 ("loosing root page %p", domain)); 403 m->ref_count--; 404 dmar_pgfree(domain->pgtbl_obj, m->pindex, 405 flags); 406 return (NULL); 407 } 408 dmar_pte_store(&ptep->pte, DMAR_PTE_R | DMAR_PTE_W | 409 VM_PAGE_TO_PHYS(m)); 410 dmar_flush_pte_to_ram(domain->dmar, ptep); 411 sf_buf_page(sfp)->ref_count += 1; 412 m->ref_count--; 413 dmar_unmap_pgtbl(sfp); 414 /* Only executed once. */ 415 goto retry; 416 } 417 } 418 pte += domain_pgtbl_pte_off(domain, base, lvl); 419 return (pte); 420 } 421 422 static int 423 domain_map_buf_locked(struct dmar_domain *domain, iommu_gaddr_t base, 424 iommu_gaddr_t size, vm_page_t *ma, uint64_t pflags, int flags) 425 { 426 dmar_pte_t *pte; 427 struct sf_buf *sf; 428 iommu_gaddr_t pg_sz, base1; 429 vm_pindex_t pi, c, idx, run_sz; 430 int lvl; 431 bool superpage; 432 433 DMAR_DOMAIN_ASSERT_PGLOCKED(domain); 434 435 base1 = base; 436 flags |= IOMMU_PGF_OBJL; 437 TD_PREP_PINNED_ASSERT; 438 439 for (sf = NULL, pi = 0; size > 0; base += pg_sz, size -= pg_sz, 440 pi += run_sz) { 441 for (lvl = 0, c = 0, superpage = false;; lvl++) { 442 pg_sz = domain_page_size(domain, lvl); 443 run_sz = pg_sz >> DMAR_PAGE_SHIFT; 444 if (lvl == domain->pglvl - 1) 445 break; 446 /* 447 * Check if the current base suitable for the 448 * superpage mapping. First, verify the level. 449 */ 450 if (!domain_is_sp_lvl(domain, lvl)) 451 continue; 452 /* 453 * Next, look at the size of the mapping and 454 * alignment of both guest and host addresses. 455 */ 456 if (size < pg_sz || (base & (pg_sz - 1)) != 0 || 457 (VM_PAGE_TO_PHYS(ma[pi]) & (pg_sz - 1)) != 0) 458 continue; 459 /* All passed, check host pages contiguouty. */ 460 if (c == 0) { 461 for (c = 1; c < run_sz; c++) { 462 if (VM_PAGE_TO_PHYS(ma[pi + c]) != 463 VM_PAGE_TO_PHYS(ma[pi + c - 1]) + 464 PAGE_SIZE) 465 break; 466 } 467 } 468 if (c >= run_sz) { 469 superpage = true; 470 break; 471 } 472 } 473 KASSERT(size >= pg_sz, 474 ("mapping loop overflow %p %jx %jx %jx", domain, 475 (uintmax_t)base, (uintmax_t)size, (uintmax_t)pg_sz)); 476 KASSERT(pg_sz > 0, ("pg_sz 0 lvl %d", lvl)); 477 pte = domain_pgtbl_map_pte(domain, base, lvl, flags, &idx, &sf); 478 if (pte == NULL) { 479 KASSERT((flags & IOMMU_PGF_WAITOK) == 0, 480 ("failed waitable pte alloc %p", domain)); 481 if (sf != NULL) 482 dmar_unmap_pgtbl(sf); 483 domain_unmap_buf_locked(domain, base1, base - base1, 484 flags); 485 TD_PINNED_ASSERT; 486 return (ENOMEM); 487 } 488 dmar_pte_store(&pte->pte, VM_PAGE_TO_PHYS(ma[pi]) | pflags | 489 (superpage ? DMAR_PTE_SP : 0)); 490 dmar_flush_pte_to_ram(domain->dmar, pte); 491 sf_buf_page(sf)->ref_count += 1; 492 } 493 if (sf != NULL) 494 dmar_unmap_pgtbl(sf); 495 TD_PINNED_ASSERT; 496 return (0); 497 } 498 499 static int 500 domain_map_buf(struct iommu_domain *iodom, iommu_gaddr_t base, 501 iommu_gaddr_t size, vm_page_t *ma, uint64_t eflags, int flags) 502 { 503 struct dmar_domain *domain; 504 struct dmar_unit *unit; 505 uint64_t pflags; 506 int error; 507 508 pflags = ((eflags & IOMMU_MAP_ENTRY_READ) != 0 ? DMAR_PTE_R : 0) | 509 ((eflags & IOMMU_MAP_ENTRY_WRITE) != 0 ? DMAR_PTE_W : 0) | 510 ((eflags & IOMMU_MAP_ENTRY_SNOOP) != 0 ? DMAR_PTE_SNP : 0) | 511 ((eflags & IOMMU_MAP_ENTRY_TM) != 0 ? DMAR_PTE_TM : 0); 512 513 domain = IODOM2DOM(iodom); 514 unit = domain->dmar; 515 516 KASSERT((domain->iodom.flags & IOMMU_DOMAIN_IDMAP) == 0, 517 ("modifying idmap pagetable domain %p", domain)); 518 KASSERT((base & DMAR_PAGE_MASK) == 0, 519 ("non-aligned base %p %jx %jx", domain, (uintmax_t)base, 520 (uintmax_t)size)); 521 KASSERT((size & DMAR_PAGE_MASK) == 0, 522 ("non-aligned size %p %jx %jx", domain, (uintmax_t)base, 523 (uintmax_t)size)); 524 KASSERT(size > 0, ("zero size %p %jx %jx", domain, (uintmax_t)base, 525 (uintmax_t)size)); 526 KASSERT(base < (1ULL << domain->agaw), 527 ("base too high %p %jx %jx agaw %d", domain, (uintmax_t)base, 528 (uintmax_t)size, domain->agaw)); 529 KASSERT(base + size < (1ULL << domain->agaw), 530 ("end too high %p %jx %jx agaw %d", domain, (uintmax_t)base, 531 (uintmax_t)size, domain->agaw)); 532 KASSERT(base + size > base, 533 ("size overflow %p %jx %jx", domain, (uintmax_t)base, 534 (uintmax_t)size)); 535 KASSERT((pflags & (DMAR_PTE_R | DMAR_PTE_W)) != 0, 536 ("neither read nor write %jx", (uintmax_t)pflags)); 537 KASSERT((pflags & ~(DMAR_PTE_R | DMAR_PTE_W | DMAR_PTE_SNP | 538 DMAR_PTE_TM)) == 0, 539 ("invalid pte flags %jx", (uintmax_t)pflags)); 540 KASSERT((pflags & DMAR_PTE_SNP) == 0 || 541 (unit->hw_ecap & DMAR_ECAP_SC) != 0, 542 ("PTE_SNP for dmar without snoop control %p %jx", 543 domain, (uintmax_t)pflags)); 544 KASSERT((pflags & DMAR_PTE_TM) == 0 || 545 (unit->hw_ecap & DMAR_ECAP_DI) != 0, 546 ("PTE_TM for dmar without DIOTLB %p %jx", 547 domain, (uintmax_t)pflags)); 548 KASSERT((flags & ~IOMMU_PGF_WAITOK) == 0, ("invalid flags %x", flags)); 549 550 DMAR_DOMAIN_PGLOCK(domain); 551 error = domain_map_buf_locked(domain, base, size, ma, pflags, flags); 552 DMAR_DOMAIN_PGUNLOCK(domain); 553 if (error != 0) 554 return (error); 555 556 if ((unit->hw_cap & DMAR_CAP_CM) != 0) 557 domain_flush_iotlb_sync(domain, base, size); 558 else if ((unit->hw_cap & DMAR_CAP_RWBF) != 0) { 559 /* See 11.1 Write Buffer Flushing. */ 560 DMAR_LOCK(unit); 561 dmar_flush_write_bufs(unit); 562 DMAR_UNLOCK(unit); 563 } 564 return (0); 565 } 566 567 static void domain_unmap_clear_pte(struct dmar_domain *domain, 568 iommu_gaddr_t base, int lvl, int flags, dmar_pte_t *pte, 569 struct sf_buf **sf, bool free_fs); 570 571 static void 572 domain_free_pgtbl_pde(struct dmar_domain *domain, iommu_gaddr_t base, 573 int lvl, int flags) 574 { 575 struct sf_buf *sf; 576 dmar_pte_t *pde; 577 vm_pindex_t idx; 578 579 sf = NULL; 580 pde = domain_pgtbl_map_pte(domain, base, lvl, flags, &idx, &sf); 581 domain_unmap_clear_pte(domain, base, lvl, flags, pde, &sf, true); 582 } 583 584 static void 585 domain_unmap_clear_pte(struct dmar_domain *domain, iommu_gaddr_t base, int lvl, 586 int flags, dmar_pte_t *pte, struct sf_buf **sf, bool free_sf) 587 { 588 vm_page_t m; 589 590 dmar_pte_clear(&pte->pte); 591 dmar_flush_pte_to_ram(domain->dmar, pte); 592 m = sf_buf_page(*sf); 593 if (free_sf) { 594 dmar_unmap_pgtbl(*sf); 595 *sf = NULL; 596 } 597 m->ref_count--; 598 if (m->ref_count != 0) 599 return; 600 KASSERT(lvl != 0, 601 ("lost reference (lvl) on root pg domain %p base %jx lvl %d", 602 domain, (uintmax_t)base, lvl)); 603 KASSERT(m->pindex != 0, 604 ("lost reference (idx) on root pg domain %p base %jx lvl %d", 605 domain, (uintmax_t)base, lvl)); 606 dmar_pgfree(domain->pgtbl_obj, m->pindex, flags); 607 domain_free_pgtbl_pde(domain, base, lvl - 1, flags); 608 } 609 610 /* 611 * Assumes that the unmap is never partial. 612 */ 613 static int 614 domain_unmap_buf_locked(struct dmar_domain *domain, iommu_gaddr_t base, 615 iommu_gaddr_t size, int flags) 616 { 617 dmar_pte_t *pte; 618 struct sf_buf *sf; 619 vm_pindex_t idx; 620 iommu_gaddr_t pg_sz; 621 int lvl; 622 623 DMAR_DOMAIN_ASSERT_PGLOCKED(domain); 624 if (size == 0) 625 return (0); 626 627 KASSERT((domain->iodom.flags & IOMMU_DOMAIN_IDMAP) == 0, 628 ("modifying idmap pagetable domain %p", domain)); 629 KASSERT((base & DMAR_PAGE_MASK) == 0, 630 ("non-aligned base %p %jx %jx", domain, (uintmax_t)base, 631 (uintmax_t)size)); 632 KASSERT((size & DMAR_PAGE_MASK) == 0, 633 ("non-aligned size %p %jx %jx", domain, (uintmax_t)base, 634 (uintmax_t)size)); 635 KASSERT(base < (1ULL << domain->agaw), 636 ("base too high %p %jx %jx agaw %d", domain, (uintmax_t)base, 637 (uintmax_t)size, domain->agaw)); 638 KASSERT(base + size < (1ULL << domain->agaw), 639 ("end too high %p %jx %jx agaw %d", domain, (uintmax_t)base, 640 (uintmax_t)size, domain->agaw)); 641 KASSERT(base + size > base, 642 ("size overflow %p %jx %jx", domain, (uintmax_t)base, 643 (uintmax_t)size)); 644 KASSERT((flags & ~IOMMU_PGF_WAITOK) == 0, ("invalid flags %x", flags)); 645 646 pg_sz = 0; /* silence gcc */ 647 flags |= IOMMU_PGF_OBJL; 648 TD_PREP_PINNED_ASSERT; 649 650 for (sf = NULL; size > 0; base += pg_sz, size -= pg_sz) { 651 for (lvl = 0; lvl < domain->pglvl; lvl++) { 652 if (lvl != domain->pglvl - 1 && 653 !domain_is_sp_lvl(domain, lvl)) 654 continue; 655 pg_sz = domain_page_size(domain, lvl); 656 if (pg_sz > size) 657 continue; 658 pte = domain_pgtbl_map_pte(domain, base, lvl, flags, 659 &idx, &sf); 660 KASSERT(pte != NULL, 661 ("sleeping or page missed %p %jx %d 0x%x", 662 domain, (uintmax_t)base, lvl, flags)); 663 if ((pte->pte & DMAR_PTE_SP) != 0 || 664 lvl == domain->pglvl - 1) { 665 domain_unmap_clear_pte(domain, base, lvl, 666 flags, pte, &sf, false); 667 break; 668 } 669 } 670 KASSERT(size >= pg_sz, 671 ("unmapping loop overflow %p %jx %jx %jx", domain, 672 (uintmax_t)base, (uintmax_t)size, (uintmax_t)pg_sz)); 673 } 674 if (sf != NULL) 675 dmar_unmap_pgtbl(sf); 676 /* 677 * See 11.1 Write Buffer Flushing for an explanation why RWBF 678 * can be ignored there. 679 */ 680 681 TD_PINNED_ASSERT; 682 return (0); 683 } 684 685 static int 686 domain_unmap_buf(struct iommu_domain *iodom, iommu_gaddr_t base, 687 iommu_gaddr_t size, int flags) 688 { 689 struct dmar_domain *domain; 690 int error; 691 692 domain = IODOM2DOM(iodom); 693 694 DMAR_DOMAIN_PGLOCK(domain); 695 error = domain_unmap_buf_locked(domain, base, size, flags); 696 DMAR_DOMAIN_PGUNLOCK(domain); 697 return (error); 698 } 699 700 int 701 domain_alloc_pgtbl(struct dmar_domain *domain) 702 { 703 vm_page_t m; 704 705 KASSERT(domain->pgtbl_obj == NULL, 706 ("already initialized %p", domain)); 707 708 domain->pgtbl_obj = vm_pager_allocate(OBJT_PHYS, NULL, 709 IDX_TO_OFF(pglvl_max_pages(domain->pglvl)), 0, 0, NULL); 710 DMAR_DOMAIN_PGLOCK(domain); 711 m = dmar_pgalloc(domain->pgtbl_obj, 0, IOMMU_PGF_WAITOK | 712 IOMMU_PGF_ZERO | IOMMU_PGF_OBJL); 713 /* No implicit free of the top level page table page. */ 714 m->ref_count = 1; 715 DMAR_DOMAIN_PGUNLOCK(domain); 716 DMAR_LOCK(domain->dmar); 717 domain->iodom.flags |= IOMMU_DOMAIN_PGTBL_INITED; 718 DMAR_UNLOCK(domain->dmar); 719 return (0); 720 } 721 722 void 723 domain_free_pgtbl(struct dmar_domain *domain) 724 { 725 vm_object_t obj; 726 vm_page_t m; 727 728 obj = domain->pgtbl_obj; 729 if (obj == NULL) { 730 KASSERT((domain->dmar->hw_ecap & DMAR_ECAP_PT) != 0 && 731 (domain->iodom.flags & IOMMU_DOMAIN_IDMAP) != 0, 732 ("lost pagetable object domain %p", domain)); 733 return; 734 } 735 DMAR_DOMAIN_ASSERT_PGLOCKED(domain); 736 domain->pgtbl_obj = NULL; 737 738 if ((domain->iodom.flags & IOMMU_DOMAIN_IDMAP) != 0) { 739 put_idmap_pgtbl(obj); 740 domain->iodom.flags &= ~IOMMU_DOMAIN_IDMAP; 741 return; 742 } 743 744 /* Obliterate ref_counts */ 745 VM_OBJECT_ASSERT_WLOCKED(obj); 746 for (m = vm_page_lookup(obj, 0); m != NULL; m = vm_page_next(m)) 747 m->ref_count = 0; 748 VM_OBJECT_WUNLOCK(obj); 749 vm_object_deallocate(obj); 750 } 751 752 static inline uint64_t 753 domain_wait_iotlb_flush(struct dmar_unit *unit, uint64_t wt, int iro) 754 { 755 uint64_t iotlbr; 756 757 dmar_write8(unit, iro + DMAR_IOTLB_REG_OFF, DMAR_IOTLB_IVT | 758 DMAR_IOTLB_DR | DMAR_IOTLB_DW | wt); 759 for (;;) { 760 iotlbr = dmar_read8(unit, iro + DMAR_IOTLB_REG_OFF); 761 if ((iotlbr & DMAR_IOTLB_IVT) == 0) 762 break; 763 cpu_spinwait(); 764 } 765 return (iotlbr); 766 } 767 768 void 769 domain_flush_iotlb_sync(struct dmar_domain *domain, iommu_gaddr_t base, 770 iommu_gaddr_t size) 771 { 772 struct dmar_unit *unit; 773 iommu_gaddr_t isize; 774 uint64_t iotlbr; 775 int am, iro; 776 777 unit = domain->dmar; 778 KASSERT(!unit->qi_enabled, ("dmar%d: sync iotlb flush call", 779 unit->iommu.unit)); 780 iro = DMAR_ECAP_IRO(unit->hw_ecap) * 16; 781 DMAR_LOCK(unit); 782 if ((unit->hw_cap & DMAR_CAP_PSI) == 0 || size > 2 * 1024 * 1024) { 783 iotlbr = domain_wait_iotlb_flush(unit, DMAR_IOTLB_IIRG_DOM | 784 DMAR_IOTLB_DID(domain->domain), iro); 785 KASSERT((iotlbr & DMAR_IOTLB_IAIG_MASK) != 786 DMAR_IOTLB_IAIG_INVLD, 787 ("dmar%d: invalidation failed %jx", unit->iommu.unit, 788 (uintmax_t)iotlbr)); 789 } else { 790 for (; size > 0; base += isize, size -= isize) { 791 am = calc_am(unit, base, size, &isize); 792 dmar_write8(unit, iro, base | am); 793 iotlbr = domain_wait_iotlb_flush(unit, 794 DMAR_IOTLB_IIRG_PAGE | 795 DMAR_IOTLB_DID(domain->domain), iro); 796 KASSERT((iotlbr & DMAR_IOTLB_IAIG_MASK) != 797 DMAR_IOTLB_IAIG_INVLD, 798 ("dmar%d: PSI invalidation failed " 799 "iotlbr 0x%jx base 0x%jx size 0x%jx am %d", 800 unit->iommu.unit, (uintmax_t)iotlbr, 801 (uintmax_t)base, (uintmax_t)size, am)); 802 /* 803 * Any non-page granularity covers whole guest 804 * address space for the domain. 805 */ 806 if ((iotlbr & DMAR_IOTLB_IAIG_MASK) != 807 DMAR_IOTLB_IAIG_PAGE) 808 break; 809 } 810 } 811 DMAR_UNLOCK(unit); 812 } 813 814 const struct iommu_domain_map_ops dmar_domain_map_ops = { 815 .map = domain_map_buf, 816 .unmap = domain_unmap_buf, 817 };
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