The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/x86/iommu/intel_reg.h

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2013-2015 The FreeBSD Foundation
    5  * All rights reserved.
    6  *
    7  * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
    8  * under sponsorship from the FreeBSD Foundation.
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  *
   19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   22  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   29  * SUCH DAMAGE.
   30  *
   31  * $FreeBSD: stable/12/sys/x86/iommu/intel_reg.h 326263 2017-11-27 15:11:47Z pfg $
   32  */
   33 
   34 #ifndef __X86_IOMMU_INTEL_REG_H
   35 #define __X86_IOMMU_INTEL_REG_H
   36 
   37 #define DMAR_PAGE_SIZE  PAGE_SIZE
   38 #define DMAR_PAGE_MASK  (DMAR_PAGE_SIZE - 1)
   39 #define DMAR_PAGE_SHIFT PAGE_SHIFT
   40 #define DMAR_NPTEPG     (DMAR_PAGE_SIZE / sizeof(dmar_pte_t))
   41 #define DMAR_NPTEPGSHIFT 9
   42 #define DMAR_PTEMASK    (DMAR_NPTEPG - 1)
   43 
   44 typedef struct dmar_root_entry {
   45         uint64_t r1;
   46         uint64_t r2;
   47 } dmar_root_entry_t;
   48 #define DMAR_ROOT_R1_P          1                  /* Present */
   49 #define DMAR_ROOT_R1_CTP_MASK   0xfffffffffffff000 /* Mask for Context-Entry
   50                                                       Table Pointer */
   51 
   52 #define DMAR_CTX_CNT            (DMAR_PAGE_SIZE / sizeof(dmar_root_entry_t))
   53 
   54 typedef struct dmar_ctx_entry {
   55         uint64_t ctx1;
   56         uint64_t ctx2;
   57 } dmar_ctx_entry_t;
   58 #define DMAR_CTX1_P             1               /* Present */
   59 #define DMAR_CTX1_FPD           2               /* Fault Processing Disable */
   60                                                 /* Translation Type: */
   61 #define DMAR_CTX1_T_UNTR        0               /* only Untranslated */
   62 #define DMAR_CTX1_T_TR          4               /* both Untranslated
   63                                                    and Translated */
   64 #define DMAR_CTX1_T_PASS        8               /* Pass-Through */
   65 #define DMAR_CTX1_ASR_MASK      0xfffffffffffff000 /* Mask for the Address
   66                                                    Space Root */
   67 #define DMAR_CTX2_AW_2LVL       0               /* 2-level page tables */
   68 #define DMAR_CTX2_AW_3LVL       1               /* 3-level page tables */
   69 #define DMAR_CTX2_AW_4LVL       2               /* 4-level page tables */
   70 #define DMAR_CTX2_AW_5LVL       3               /* 5-level page tables */
   71 #define DMAR_CTX2_AW_6LVL       4               /* 6-level page tables */
   72 #define DMAR_CTX2_DID_MASK      0xffff0
   73 #define DMAR_CTX2_DID(x)        ((x) << 8)      /* Domain Identifier */
   74 #define DMAR_CTX2_GET_DID(ctx2) (((ctx2) & DMAR_CTX2_DID_MASK) >> 8)
   75 
   76 typedef struct dmar_pte {
   77         uint64_t pte;
   78 } dmar_pte_t;
   79 #define DMAR_PTE_R              1               /* Read */
   80 #define DMAR_PTE_W              (1 << 1)        /* Write */
   81 #define DMAR_PTE_SP             (1 << 7)        /* Super Page */
   82 #define DMAR_PTE_SNP            (1 << 11)       /* Snoop Behaviour */
   83 #define DMAR_PTE_ADDR_MASK      0xffffffffff000 /* Address Mask */
   84 #define DMAR_PTE_TM             (1ULL << 62)    /* Transient Mapping */
   85 
   86 typedef struct dmar_irte {
   87         uint64_t irte1;
   88         uint64_t irte2;
   89 } dmar_irte_t;
   90 /* Source Validation Type */
   91 #define DMAR_IRTE2_SVT_NONE     (0ULL << (82 - 64))
   92 #define DMAR_IRTE2_SVT_RID      (1ULL << (82 - 64))
   93 #define DMAR_IRTE2_SVT_BUS      (2ULL << (82 - 64))
   94 /* Source-id Qualifier */
   95 #define DMAR_IRTE2_SQ_RID       (0ULL << (80 - 64))
   96 #define DMAR_IRTE2_SQ_RID_N2    (1ULL << (80 - 64))
   97 #define DMAR_IRTE2_SQ_RID_N21   (2ULL << (80 - 64))
   98 #define DMAR_IRTE2_SQ_RID_N210  (3ULL << (80 - 64))
   99 /* Source Identifier */
  100 #define DMAR_IRTE2_SID_RID(x)   ((uint64_t)(x))
  101 #define DMAR_IRTE2_SID_BUS(start, end)  ((((uint64_t)(start)) << 8) | (end))
  102 /* Destination Id */
  103 #define DMAR_IRTE1_DST_xAPIC(x) (((uint64_t)(x)) << 40)
  104 #define DMAR_IRTE1_DST_x2APIC(x) (((uint64_t)(x)) << 32)
  105 /* Vector */
  106 #define DMAR_IRTE1_V(x)         (((uint64_t)x) << 16)
  107 #define DMAR_IRTE1_IM_POSTED    (1ULL << 15)    /* Posted */
  108 /* Delivery Mode */
  109 #define DMAR_IRTE1_DLM_FM       (0ULL << 5)
  110 #define DMAR_IRTE1_DLM_LP       (1ULL << 5)
  111 #define DMAR_IRTE1_DLM_SMI      (2ULL << 5)
  112 #define DMAR_IRTE1_DLM_NMI      (4ULL << 5)
  113 #define DMAR_IRTE1_DLM_INIT     (5ULL << 5)
  114 #define DMAR_IRTE1_DLM_ExtINT   (7ULL << 5)
  115 /* Trigger Mode */
  116 #define DMAR_IRTE1_TM_EDGE      (0ULL << 4)
  117 #define DMAR_IRTE1_TM_LEVEL     (1ULL << 4)
  118 /* Redirection Hint */
  119 #define DMAR_IRTE1_RH_DIRECT    (0ULL << 3)
  120 #define DMAR_IRTE1_RH_SELECT    (1ULL << 3)
  121 /* Destination Mode */
  122 #define DMAR_IRTE1_DM_PHYSICAL  (0ULL << 2)
  123 #define DMAR_IRTE1_DM_LOGICAL   (1ULL << 2)
  124 #define DMAR_IRTE1_FPD          (1ULL << 1)     /* Fault Processing Disable */
  125 #define DMAR_IRTE1_P            (1ULL)          /* Present */
  126 
  127 /* Version register */
  128 #define DMAR_VER_REG    0
  129 #define DMAR_MAJOR_VER(x)       (((x) >> 4) & 0xf)
  130 #define DMAR_MINOR_VER(x)       ((x) & 0xf)
  131 
  132 /* Capabilities register */
  133 #define DMAR_CAP_REG    0x8
  134 #define DMAR_CAP_PI     (1ULL << 59)    /* Posted Interrupts */
  135 #define DMAR_CAP_FL1GP  (1ULL << 56)    /* First Level 1GByte Page */
  136 #define DMAR_CAP_DRD    (1ULL << 55)    /* DMA Read Draining */
  137 #define DMAR_CAP_DWD    (1ULL << 54)    /* DMA Write Draining */
  138 #define DMAR_CAP_MAMV(x) ((u_int)(((x) >> 48) & 0x3f))
  139                                         /* Maximum Address Mask */
  140 #define DMAR_CAP_NFR(x) ((u_int)(((x) >> 40) & 0xff) + 1)
  141                                         /* Num of Fault-recording regs */
  142 #define DMAR_CAP_PSI    (1ULL << 39)    /* Page Selective Invalidation */
  143 #define DMAR_CAP_SPS(x) ((u_int)(((x) >> 34) & 0xf)) /* Super-Page Support */
  144 #define DMAR_CAP_SPS_2M 0x1
  145 #define DMAR_CAP_SPS_1G 0x2
  146 #define DMAR_CAP_SPS_512G 0x4
  147 #define DMAR_CAP_SPS_1T 0x8
  148 #define DMAR_CAP_FRO(x) ((u_int)(((x) >> 24) & 0x1ff))
  149                                         /* Fault-recording reg offset */
  150 #define DMAR_CAP_ISOCH  (1 << 23)       /* Isochrony */
  151 #define DMAR_CAP_ZLR    (1 << 22)       /* Zero-length reads */
  152 #define DMAR_CAP_MGAW(x) ((u_int)(((x) >> 16) & 0x3f))
  153                                         /* Max Guest Address Width */
  154 #define DMAR_CAP_SAGAW(x) ((u_int)(((x) >> 8) & 0x1f))
  155                                         /* Adjusted Guest Address Width */
  156 #define DMAR_CAP_SAGAW_2LVL     0x01
  157 #define DMAR_CAP_SAGAW_3LVL     0x02
  158 #define DMAR_CAP_SAGAW_4LVL     0x04
  159 #define DMAR_CAP_SAGAW_5LVL     0x08
  160 #define DMAR_CAP_SAGAW_6LVL     0x10
  161 #define DMAR_CAP_CM     (1 << 7)        /* Caching mode */
  162 #define DMAR_CAP_PHMR   (1 << 6)        /* Protected High-mem Region */
  163 #define DMAR_CAP_PLMR   (1 << 5)        /* Protected Low-mem Region */
  164 #define DMAR_CAP_RWBF   (1 << 4)        /* Required Write-Buffer Flushing */
  165 #define DMAR_CAP_AFL    (1 << 3)        /* Advanced Fault Logging */
  166 #define DMAR_CAP_ND(x)  ((u_int)((x) & 0x3))    /* Number of domains */
  167 
  168 /* Extended Capabilities register */
  169 #define DMAR_ECAP_REG   0x10
  170 #define DMAR_ECAP_PSS(x) (((x) >> 35) & 0xf) /* PASID Size Supported */
  171 #define DMAR_ECAP_EAFS  (1ULL << 34)    /* Extended Accessed Flag */
  172 #define DMAR_ECAP_NWFS  (1ULL << 33)    /* No Write Flag */
  173 #define DMAR_ECAP_SRS   (1ULL << 31)    /* Supervisor Request */
  174 #define DMAR_ECAP_ERS   (1ULL << 30)    /* Execute Request */
  175 #define DMAR_ECAP_PRS   (1ULL << 29)    /* Page Request */
  176 #define DMAR_ECAP_PASID (1ULL << 28)    /* Process Address Space Id */
  177 #define DMAR_ECAP_DIS   (1ULL << 27)    /* Deferred Invalidate */
  178 #define DMAR_ECAP_NEST  (1ULL << 26)    /* Nested Translation */
  179 #define DMAR_ECAP_MTS   (1ULL << 25)    /* Memory Type */
  180 #define DMAR_ECAP_ECS   (1ULL << 24)    /* Extended Context */
  181 #define DMAR_ECAP_MHMV(x) ((u_int)(((x) >> 20) & 0xf))
  182                                         /* Maximum Handle Mask Value */
  183 #define DMAR_ECAP_IRO(x)  ((u_int)(((x) >> 8) & 0x3ff))
  184                                         /* IOTLB Register Offset */
  185 #define DMAR_ECAP_SC    (1 << 7)        /* Snoop Control */
  186 #define DMAR_ECAP_PT    (1 << 6)        /* Pass Through */
  187 #define DMAR_ECAP_EIM   (1 << 4)        /* Extended Interrupt Mode (x2APIC) */
  188 #define DMAR_ECAP_IR    (1 << 3)        /* Interrupt Remapping */
  189 #define DMAR_ECAP_DI    (1 << 2)        /* Device IOTLB */
  190 #define DMAR_ECAP_QI    (1 << 1)        /* Queued Invalidation */
  191 #define DMAR_ECAP_C     (1 << 0)        /* Coherency */
  192 
  193 /* Global Command register */
  194 #define DMAR_GCMD_REG   0x18
  195 #define DMAR_GCMD_TE    (1U << 31)      /* Translation Enable */
  196 #define DMAR_GCMD_SRTP  (1 << 30)       /* Set Root Table Pointer */
  197 #define DMAR_GCMD_SFL   (1 << 29)       /* Set Fault Log */
  198 #define DMAR_GCMD_EAFL  (1 << 28)       /* Enable Advanced Fault Logging */
  199 #define DMAR_GCMD_WBF   (1 << 27)       /* Write Buffer Flush */
  200 #define DMAR_GCMD_QIE   (1 << 26)       /* Queued Invalidation Enable */
  201 #define DMAR_GCMD_IRE   (1 << 25)       /* Interrupt Remapping Enable */
  202 #define DMAR_GCMD_SIRTP (1 << 24)       /* Set Interrupt Remap Table Pointer */
  203 #define DMAR_GCMD_CFI   (1 << 23)       /* Compatibility Format Interrupt */
  204 
  205 /* Global Status register */
  206 #define DMAR_GSTS_REG   0x1c
  207 #define DMAR_GSTS_TES   (1U << 31)      /* Translation Enable Status */
  208 #define DMAR_GSTS_RTPS  (1 << 30)       /* Root Table Pointer Status */
  209 #define DMAR_GSTS_FLS   (1 << 29)       /* Fault Log Status */
  210 #define DMAR_GSTS_AFLS  (1 << 28)       /* Advanced Fault Logging Status */
  211 #define DMAR_GSTS_WBFS  (1 << 27)       /* Write Buffer Flush Status */
  212 #define DMAR_GSTS_QIES  (1 << 26)       /* Queued Invalidation Enable Status */
  213 #define DMAR_GSTS_IRES  (1 << 25)       /* Interrupt Remapping Enable Status */
  214 #define DMAR_GSTS_IRTPS (1 << 24)       /* Interrupt Remapping Table
  215                                            Pointer Status */
  216 #define DMAR_GSTS_CFIS  (1 << 23)       /* Compatibility Format
  217                                            Interrupt Status */
  218 
  219 /* Root-Entry Table Address register */
  220 #define DMAR_RTADDR_REG 0x20
  221 #define DMAR_RTADDR_RTT (1 << 11)       /* Root Table Type */
  222 #define DMAR_RTADDR_RTA_MASK    0xfffffffffffff000
  223 
  224 /* Context Command register */
  225 #define DMAR_CCMD_REG   0x28
  226 #define DMAR_CCMD_ICC   (1ULL << 63)    /* Invalidate Context-Cache */
  227 #define DMAR_CCMD_ICC32 (1U << 31)
  228 #define DMAR_CCMD_CIRG_MASK     (0x3ULL << 61)  /* Context Invalidation
  229                                                    Request Granularity */
  230 #define DMAR_CCMD_CIRG_GLOB     (0x1ULL << 61)  /* Global */
  231 #define DMAR_CCMD_CIRG_DOM      (0x2ULL << 61)  /* Domain */
  232 #define DMAR_CCMD_CIRG_DEV      (0x3ULL << 61)  /* Device */
  233 #define DMAR_CCMD_CAIG(x)       (((x) >> 59) & 0x3) /* Context Actual
  234                                                     Invalidation Granularity */
  235 #define DMAR_CCMD_CAIG_GLOB     0x1             /* Global */
  236 #define DMAR_CCMD_CAIG_DOM      0x2             /* Domain */
  237 #define DMAR_CCMD_CAIG_DEV      0x3             /* Device */
  238 #define DMAR_CCMD_FM            (0x3UUL << 32)  /* Function Mask */
  239 #define DMAR_CCMD_SID(x)        (((x) & 0xffff) << 16) /* Source-ID */
  240 #define DMAR_CCMD_DID(x)        ((x) & 0xffff)  /* Domain-ID */
  241 
  242 /* Invalidate Address register */
  243 #define DMAR_IVA_REG_OFF        0
  244 #define DMAR_IVA_IH             (1 << 6)        /* Invalidation Hint */
  245 #define DMAR_IVA_AM(x)          ((x) & 0x1f)    /* Address Mask */
  246 #define DMAR_IVA_ADDR(x)        ((x) & ~0xfffULL) /* Address */
  247 
  248 /* IOTLB Invalidate register */
  249 #define DMAR_IOTLB_REG_OFF      0x8
  250 #define DMAR_IOTLB_IVT          (1ULL << 63)    /* Invalidate IOTLB */
  251 #define DMAR_IOTLB_IVT32        (1U << 31)
  252 #define DMAR_IOTLB_IIRG_MASK    (0x3ULL << 60)  /* Invalidation Request
  253                                                    Granularity */
  254 #define DMAR_IOTLB_IIRG_GLB     (0x1ULL << 60)  /* Global */
  255 #define DMAR_IOTLB_IIRG_DOM     (0x2ULL << 60)  /* Domain-selective */
  256 #define DMAR_IOTLB_IIRG_PAGE    (0x3ULL << 60)  /* Page-selective */
  257 #define DMAR_IOTLB_IAIG_MASK    (0x3ULL << 57)  /* Actual Invalidation
  258                                                    Granularity */
  259 #define DMAR_IOTLB_IAIG_INVLD   0               /* Hw detected error */
  260 #define DMAR_IOTLB_IAIG_GLB     (0x1ULL << 57)  /* Global */
  261 #define DMAR_IOTLB_IAIG_DOM     (0x2ULL << 57)  /* Domain-selective */
  262 #define DMAR_IOTLB_IAIG_PAGE    (0x3ULL << 57)  /* Page-selective */
  263 #define DMAR_IOTLB_DR           (0x1ULL << 49)  /* Drain Reads */
  264 #define DMAR_IOTLB_DW           (0x1ULL << 48)  /* Drain Writes */
  265 #define DMAR_IOTLB_DID(x)       (((uint64_t)(x) & 0xffff) << 32) /* Domain Id */
  266 
  267 /* Fault Status register */
  268 #define DMAR_FSTS_REG           0x34
  269 #define DMAR_FSTS_FRI(x)        (((x) >> 8) & 0xff) /* Fault Record Index */
  270 #define DMAR_FSTS_ITE           (1 << 6)        /* Invalidation Time-out */
  271 #define DMAR_FSTS_ICE           (1 << 5)        /* Invalidation Completion */
  272 #define DMAR_FSTS_IQE           (1 << 4)        /* Invalidation Queue */
  273 #define DMAR_FSTS_APF           (1 << 3)        /* Advanced Pending Fault */
  274 #define DMAR_FSTS_AFO           (1 << 2)        /* Advanced Fault Overflow */
  275 #define DMAR_FSTS_PPF           (1 << 1)        /* Primary Pending Fault */
  276 #define DMAR_FSTS_PFO           1               /* Fault Overflow */
  277 
  278 /* Fault Event Control register */
  279 #define DMAR_FECTL_REG          0x38
  280 #define DMAR_FECTL_IM           (1U << 31)      /* Interrupt Mask */
  281 #define DMAR_FECTL_IP           (1 << 30)       /* Interrupt Pending */
  282 
  283 /* Fault Event Data register */
  284 #define DMAR_FEDATA_REG         0x3c
  285 
  286 /* Fault Event Address register */
  287 #define DMAR_FEADDR_REG         0x40
  288 
  289 /* Fault Event Upper Address register */
  290 #define DMAR_FEUADDR_REG        0x44
  291 
  292 /* Advanced Fault Log register */
  293 #define DMAR_AFLOG_REG          0x58
  294 
  295 /* Fault Recording Register, also usable for Advanced Fault Log records */
  296 #define DMAR_FRCD2_F            (1ULL << 63)    /* Fault */
  297 #define DMAR_FRCD2_F32          (1U << 31)
  298 #define DMAR_FRCD2_T(x)         ((int)((x >> 62) & 1))  /* Type */
  299 #define DMAR_FRCD2_T_W          0               /* Write request */
  300 #define DMAR_FRCD2_T_R          1               /* Read or AtomicOp */
  301 #define DMAR_FRCD2_AT(x)        ((int)((x >> 60) & 0x3)) /* Address Type */
  302 #define DMAR_FRCD2_FR(x)        ((int)((x >> 32) & 0xff)) /* Fault Reason */
  303 #define DMAR_FRCD2_SID(x)       ((int)(x & 0xffff))     /* Source Identifier */
  304 #define DMAR_FRCS1_FI_MASK      0xffffffffff000 /* Fault Info, Address Mask */
  305 
  306 /* Protected Memory Enable register */
  307 #define DMAR_PMEN_REG           0x64
  308 #define DMAR_PMEN_EPM           (1U << 31)      /* Enable Protected Memory */
  309 #define DMAR_PMEN_PRS           1               /* Protected Region Status */
  310 
  311 /* Protected Low-Memory Base register */
  312 #define DMAR_PLMBASE_REG        0x68
  313 
  314 /* Protected Low-Memory Limit register */
  315 #define DMAR_PLMLIMIT_REG       0x6c
  316 
  317 /* Protected High-Memory Base register */
  318 #define DMAR_PHMBASE_REG        0x70
  319 
  320 /* Protected High-Memory Limit register */
  321 #define DMAR_PHMLIMIT_REG       0x78
  322 
  323 /* Queued Invalidation Descriptors */
  324 #define DMAR_IQ_DESCR_SZ_SHIFT  4       /* Shift for descriptor count
  325                                            to ring offset */
  326 #define DMAR_IQ_DESCR_SZ        (1 << DMAR_IQ_DESCR_SZ_SHIFT)
  327                                         /* Descriptor size */
  328 
  329 /* Context-cache Invalidate Descriptor */
  330 #define DMAR_IQ_DESCR_CTX_INV   0x1
  331 #define DMAR_IQ_DESCR_CTX_GLOB  (0x1 << 4)      /* Granularity: Global */
  332 #define DMAR_IQ_DESCR_CTX_DOM   (0x2 << 4)      /* Granularity: Domain */
  333 #define DMAR_IQ_DESCR_CTX_DEV   (0x3 << 4)      /* Granularity: Device */
  334 #define DMAR_IQ_DESCR_CTX_DID(x) (((uint32_t)(x)) << 16) /* Domain Id */
  335 #define DMAR_IQ_DESCR_CTX_SRC(x) (((uint64_t)(x)) << 32) /* Source Id */
  336 #define DMAR_IQ_DESCR_CTX_FM(x)  (((uint64_t)(x)) << 48) /* Function Mask */
  337 
  338 /* IOTLB Invalidate Descriptor */
  339 #define DMAR_IQ_DESCR_IOTLB_INV 0x2
  340 #define DMAR_IQ_DESCR_IOTLB_GLOB (0x1 << 4)     /* Granularity: Global */
  341 #define DMAR_IQ_DESCR_IOTLB_DOM  (0x2 << 4)     /* Granularity: Domain */
  342 #define DMAR_IQ_DESCR_IOTLB_PAGE (0x3 << 4)     /* Granularity: Page */
  343 #define DMAR_IQ_DESCR_IOTLB_DW  (1 << 6)        /* Drain Writes */
  344 #define DMAR_IQ_DESCR_IOTLB_DR  (1 << 7)        /* Drain Reads */
  345 #define DMAR_IQ_DESCR_IOTLB_DID(x) (((uint32_t)(x)) << 16) /* Domain Id */
  346 
  347 /* Device-TLB Invalidate Descriptor */
  348 #define DMAR_IQ_DESCR_DTLB_INV  0x3
  349 
  350 /* Invalidate Interrupt Entry Cache */
  351 #define DMAR_IQ_DESCR_IEC_INV   0x4
  352 #define DMAR_IQ_DESCR_IEC_IDX   (1 << 4) /* Index-Selective Invalidation */
  353 #define DMAR_IQ_DESCR_IEC_IIDX(x) (((uint64_t)x) << 32) /* Interrupt Index */
  354 #define DMAR_IQ_DESCR_IEC_IM(x) ((x) << 27)     /* Index Mask */
  355 
  356 /* Invalidation Wait Descriptor */
  357 #define DMAR_IQ_DESCR_WAIT_ID   0x5
  358 #define DMAR_IQ_DESCR_WAIT_IF   (1 << 4)        /* Interrupt Flag */
  359 #define DMAR_IQ_DESCR_WAIT_SW   (1 << 5)        /* Status Write */
  360 #define DMAR_IQ_DESCR_WAIT_FN   (1 << 6)        /* Fence */
  361 #define DMAR_IQ_DESCR_WAIT_SD(x) (((uint64_t)(x)) << 32) /* Status Data */
  362 
  363 /* Extended IOTLB Invalidate Descriptor */
  364 #define DMAR_IQ_DESCR_EIOTLB_INV 0x6
  365 
  366 /* PASID-Cache Invalidate Descriptor */
  367 #define DMAR_IQ_DESCR_PASIDC_INV 0x7
  368 
  369 /* Extended Device-TLB Invalidate Descriptor */
  370 #define DMAR_IQ_DESCR_EDTLB_INV 0x8
  371 
  372 /* Invalidation Queue Head register */
  373 #define DMAR_IQH_REG            0x80
  374 #define DMAR_IQH_MASK           0x7fff0         /* Next cmd index mask */
  375 
  376 /* Invalidation Queue Tail register */
  377 #define DMAR_IQT_REG            0x88
  378 #define DMAR_IQT_MASK           0x7fff0
  379 
  380 /* Invalidation Queue Address register */
  381 #define DMAR_IQA_REG            0x90
  382 #define DMAR_IQA_IQA_MASK       0xfffffffffffff000 /* Invalidation Queue
  383                                                       Base Address mask */
  384 #define DMAR_IQA_QS_MASK        0x7             /* Queue Size in pages */
  385 #define DMAR_IQA_QS_MAX         0x7             /* Max Queue size */
  386 #define DMAR_IQA_QS_DEF         3
  387 
  388  /* Invalidation Completion Status register */
  389 #define DMAR_ICS_REG            0x9c
  390 #define DMAR_ICS_IWC            1               /* Invalidation Wait
  391                                                    Descriptor Complete */
  392 
  393 /* Invalidation Event Control register */
  394 #define DMAR_IECTL_REG          0xa0
  395 #define DMAR_IECTL_IM           (1U << 31)      /* Interrupt Mask */
  396 #define DMAR_IECTL_IP           (1 << 30)       /* Interrupt Pending */
  397 
  398 /* Invalidation Event Data register */
  399 #define DMAR_IEDATA_REG         0xa4
  400 
  401 /* Invalidation Event Address register */
  402 #define DMAR_IEADDR_REG         0xa8
  403 
  404 /* Invalidation Event Upper Address register */
  405 #define DMAR_IEUADDR_REG        0xac
  406 
  407 /* Interrupt Remapping Table Address register */
  408 #define DMAR_IRTA_REG           0xb8
  409 #define DMAR_IRTA_EIME          (1 << 11)       /* Extended Interrupt Mode
  410                                                    Enable */
  411 #define DMAR_IRTA_S_MASK        0xf             /* Size Mask */
  412 
  413 #endif

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