1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2013-2015 The FreeBSD Foundation
5 *
6 * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
7 * under sponsorship from the FreeBSD Foundation.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * $FreeBSD$
31 */
32
33 #ifndef __X86_IOMMU_INTEL_REG_H
34 #define __X86_IOMMU_INTEL_REG_H
35
36 #define DMAR_PAGE_SIZE PAGE_SIZE
37 #define DMAR_PAGE_MASK (DMAR_PAGE_SIZE - 1)
38 #define DMAR_PAGE_SHIFT PAGE_SHIFT
39 #define DMAR_NPTEPG (DMAR_PAGE_SIZE / sizeof(dmar_pte_t))
40 #define DMAR_NPTEPGSHIFT 9
41 #define DMAR_PTEMASK (DMAR_NPTEPG - 1)
42
43 #define IOMMU_PAGE_SIZE DMAR_PAGE_SIZE
44 #define IOMMU_PAGE_MASK DMAR_PAGE_MASK
45
46 typedef struct dmar_root_entry {
47 uint64_t r1;
48 uint64_t r2;
49 } dmar_root_entry_t;
50 #define DMAR_ROOT_R1_P 1 /* Present */
51 #define DMAR_ROOT_R1_CTP_MASK 0xfffffffffffff000 /* Mask for Context-Entry
52 Table Pointer */
53
54 #define DMAR_CTX_CNT (DMAR_PAGE_SIZE / sizeof(dmar_root_entry_t))
55
56 typedef struct dmar_ctx_entry {
57 uint64_t ctx1;
58 uint64_t ctx2;
59 } dmar_ctx_entry_t;
60 #define DMAR_CTX1_P 1 /* Present */
61 #define DMAR_CTX1_FPD 2 /* Fault Processing Disable */
62 /* Translation Type: */
63 #define DMAR_CTX1_T_UNTR 0 /* only Untranslated */
64 #define DMAR_CTX1_T_TR 4 /* both Untranslated
65 and Translated */
66 #define DMAR_CTX1_T_PASS 8 /* Pass-Through */
67 #define DMAR_CTX1_ASR_MASK 0xfffffffffffff000 /* Mask for the Address
68 Space Root */
69 #define DMAR_CTX2_AW_2LVL 0 /* 2-level page tables */
70 #define DMAR_CTX2_AW_3LVL 1 /* 3-level page tables */
71 #define DMAR_CTX2_AW_4LVL 2 /* 4-level page tables */
72 #define DMAR_CTX2_AW_5LVL 3 /* 5-level page tables */
73 #define DMAR_CTX2_AW_6LVL 4 /* 6-level page tables */
74 #define DMAR_CTX2_DID_MASK 0xffff0
75 #define DMAR_CTX2_DID(x) ((x) << 8) /* Domain Identifier */
76 #define DMAR_CTX2_GET_DID(ctx2) (((ctx2) & DMAR_CTX2_DID_MASK) >> 8)
77
78 typedef struct dmar_pte {
79 uint64_t pte;
80 } dmar_pte_t;
81 #define DMAR_PTE_R 1 /* Read */
82 #define DMAR_PTE_W (1 << 1) /* Write */
83 #define DMAR_PTE_SP (1 << 7) /* Super Page */
84 #define DMAR_PTE_SNP (1 << 11) /* Snoop Behaviour */
85 #define DMAR_PTE_ADDR_MASK 0xffffffffff000 /* Address Mask */
86 #define DMAR_PTE_TM (1ULL << 62) /* Transient Mapping */
87
88 typedef struct dmar_irte {
89 uint64_t irte1;
90 uint64_t irte2;
91 } dmar_irte_t;
92 /* Source Validation Type */
93 #define DMAR_IRTE2_SVT_NONE (0ULL << (82 - 64))
94 #define DMAR_IRTE2_SVT_RID (1ULL << (82 - 64))
95 #define DMAR_IRTE2_SVT_BUS (2ULL << (82 - 64))
96 /* Source-id Qualifier */
97 #define DMAR_IRTE2_SQ_RID (0ULL << (80 - 64))
98 #define DMAR_IRTE2_SQ_RID_N2 (1ULL << (80 - 64))
99 #define DMAR_IRTE2_SQ_RID_N21 (2ULL << (80 - 64))
100 #define DMAR_IRTE2_SQ_RID_N210 (3ULL << (80 - 64))
101 /* Source Identifier */
102 #define DMAR_IRTE2_SID_RID(x) ((uint64_t)(x))
103 #define DMAR_IRTE2_SID_BUS(start, end) ((((uint64_t)(start)) << 8) | (end))
104 /* Destination Id */
105 #define DMAR_IRTE1_DST_xAPIC(x) (((uint64_t)(x)) << 40)
106 #define DMAR_IRTE1_DST_x2APIC(x) (((uint64_t)(x)) << 32)
107 /* Vector */
108 #define DMAR_IRTE1_V(x) (((uint64_t)x) << 16)
109 #define DMAR_IRTE1_IM_POSTED (1ULL << 15) /* Posted */
110 /* Delivery Mode */
111 #define DMAR_IRTE1_DLM_FM (0ULL << 5)
112 #define DMAR_IRTE1_DLM_LP (1ULL << 5)
113 #define DMAR_IRTE1_DLM_SMI (2ULL << 5)
114 #define DMAR_IRTE1_DLM_NMI (4ULL << 5)
115 #define DMAR_IRTE1_DLM_INIT (5ULL << 5)
116 #define DMAR_IRTE1_DLM_ExtINT (7ULL << 5)
117 /* Trigger Mode */
118 #define DMAR_IRTE1_TM_EDGE (0ULL << 4)
119 #define DMAR_IRTE1_TM_LEVEL (1ULL << 4)
120 /* Redirection Hint */
121 #define DMAR_IRTE1_RH_DIRECT (0ULL << 3)
122 #define DMAR_IRTE1_RH_SELECT (1ULL << 3)
123 /* Destination Mode */
124 #define DMAR_IRTE1_DM_PHYSICAL (0ULL << 2)
125 #define DMAR_IRTE1_DM_LOGICAL (1ULL << 2)
126 #define DMAR_IRTE1_FPD (1ULL << 1) /* Fault Processing Disable */
127 #define DMAR_IRTE1_P (1ULL) /* Present */
128
129 /* Version register */
130 #define DMAR_VER_REG 0
131 #define DMAR_MAJOR_VER(x) (((x) >> 4) & 0xf)
132 #define DMAR_MINOR_VER(x) ((x) & 0xf)
133
134 /* Capabilities register */
135 #define DMAR_CAP_REG 0x8
136 #define DMAR_CAP_PI (1ULL << 59) /* Posted Interrupts */
137 #define DMAR_CAP_FL1GP (1ULL << 56) /* First Level 1GByte Page */
138 #define DMAR_CAP_DRD (1ULL << 55) /* DMA Read Draining */
139 #define DMAR_CAP_DWD (1ULL << 54) /* DMA Write Draining */
140 #define DMAR_CAP_MAMV(x) ((u_int)(((x) >> 48) & 0x3f))
141 /* Maximum Address Mask */
142 #define DMAR_CAP_NFR(x) ((u_int)(((x) >> 40) & 0xff) + 1)
143 /* Num of Fault-recording regs */
144 #define DMAR_CAP_PSI (1ULL << 39) /* Page Selective Invalidation */
145 #define DMAR_CAP_SPS(x) ((u_int)(((x) >> 34) & 0xf)) /* Super-Page Support */
146 #define DMAR_CAP_SPS_2M 0x1
147 #define DMAR_CAP_SPS_1G 0x2
148 #define DMAR_CAP_SPS_512G 0x4
149 #define DMAR_CAP_SPS_1T 0x8
150 #define DMAR_CAP_FRO(x) ((u_int)(((x) >> 24) & 0x1ff))
151 /* Fault-recording reg offset */
152 #define DMAR_CAP_ISOCH (1 << 23) /* Isochrony */
153 #define DMAR_CAP_ZLR (1 << 22) /* Zero-length reads */
154 #define DMAR_CAP_MGAW(x) ((u_int)(((x) >> 16) & 0x3f))
155 /* Max Guest Address Width */
156 #define DMAR_CAP_SAGAW(x) ((u_int)(((x) >> 8) & 0x1f))
157 /* Adjusted Guest Address Width */
158 #define DMAR_CAP_SAGAW_2LVL 0x01
159 #define DMAR_CAP_SAGAW_3LVL 0x02
160 #define DMAR_CAP_SAGAW_4LVL 0x04
161 #define DMAR_CAP_SAGAW_5LVL 0x08
162 #define DMAR_CAP_SAGAW_6LVL 0x10
163 #define DMAR_CAP_CM (1 << 7) /* Caching mode */
164 #define DMAR_CAP_PHMR (1 << 6) /* Protected High-mem Region */
165 #define DMAR_CAP_PLMR (1 << 5) /* Protected Low-mem Region */
166 #define DMAR_CAP_RWBF (1 << 4) /* Required Write-Buffer Flushing */
167 #define DMAR_CAP_AFL (1 << 3) /* Advanced Fault Logging */
168 #define DMAR_CAP_ND(x) ((u_int)((x) & 0x3)) /* Number of domains */
169
170 /* Extended Capabilities register */
171 #define DMAR_ECAP_REG 0x10
172 #define DMAR_ECAP_PSS(x) (((x) >> 35) & 0xf) /* PASID Size Supported */
173 #define DMAR_ECAP_EAFS (1ULL << 34) /* Extended Accessed Flag */
174 #define DMAR_ECAP_NWFS (1ULL << 33) /* No Write Flag */
175 #define DMAR_ECAP_SRS (1ULL << 31) /* Supervisor Request */
176 #define DMAR_ECAP_ERS (1ULL << 30) /* Execute Request */
177 #define DMAR_ECAP_PRS (1ULL << 29) /* Page Request */
178 #define DMAR_ECAP_PASID (1ULL << 28) /* Process Address Space Id */
179 #define DMAR_ECAP_DIS (1ULL << 27) /* Deferred Invalidate */
180 #define DMAR_ECAP_NEST (1ULL << 26) /* Nested Translation */
181 #define DMAR_ECAP_MTS (1ULL << 25) /* Memory Type */
182 #define DMAR_ECAP_ECS (1ULL << 24) /* Extended Context */
183 #define DMAR_ECAP_MHMV(x) ((u_int)(((x) >> 20) & 0xf))
184 /* Maximum Handle Mask Value */
185 #define DMAR_ECAP_IRO(x) ((u_int)(((x) >> 8) & 0x3ff))
186 /* IOTLB Register Offset */
187 #define DMAR_ECAP_SC (1 << 7) /* Snoop Control */
188 #define DMAR_ECAP_PT (1 << 6) /* Pass Through */
189 #define DMAR_ECAP_EIM (1 << 4) /* Extended Interrupt Mode (x2APIC) */
190 #define DMAR_ECAP_IR (1 << 3) /* Interrupt Remapping */
191 #define DMAR_ECAP_DI (1 << 2) /* Device IOTLB */
192 #define DMAR_ECAP_QI (1 << 1) /* Queued Invalidation */
193 #define DMAR_ECAP_C (1 << 0) /* Coherency */
194
195 /* Global Command register */
196 #define DMAR_GCMD_REG 0x18
197 #define DMAR_GCMD_TE (1U << 31) /* Translation Enable */
198 #define DMAR_GCMD_SRTP (1 << 30) /* Set Root Table Pointer */
199 #define DMAR_GCMD_SFL (1 << 29) /* Set Fault Log */
200 #define DMAR_GCMD_EAFL (1 << 28) /* Enable Advanced Fault Logging */
201 #define DMAR_GCMD_WBF (1 << 27) /* Write Buffer Flush */
202 #define DMAR_GCMD_QIE (1 << 26) /* Queued Invalidation Enable */
203 #define DMAR_GCMD_IRE (1 << 25) /* Interrupt Remapping Enable */
204 #define DMAR_GCMD_SIRTP (1 << 24) /* Set Interrupt Remap Table Pointer */
205 #define DMAR_GCMD_CFI (1 << 23) /* Compatibility Format Interrupt */
206
207 /* Global Status register */
208 #define DMAR_GSTS_REG 0x1c
209 #define DMAR_GSTS_TES (1U << 31) /* Translation Enable Status */
210 #define DMAR_GSTS_RTPS (1 << 30) /* Root Table Pointer Status */
211 #define DMAR_GSTS_FLS (1 << 29) /* Fault Log Status */
212 #define DMAR_GSTS_AFLS (1 << 28) /* Advanced Fault Logging Status */
213 #define DMAR_GSTS_WBFS (1 << 27) /* Write Buffer Flush Status */
214 #define DMAR_GSTS_QIES (1 << 26) /* Queued Invalidation Enable Status */
215 #define DMAR_GSTS_IRES (1 << 25) /* Interrupt Remapping Enable Status */
216 #define DMAR_GSTS_IRTPS (1 << 24) /* Interrupt Remapping Table
217 Pointer Status */
218 #define DMAR_GSTS_CFIS (1 << 23) /* Compatibility Format
219 Interrupt Status */
220
221 /* Root-Entry Table Address register */
222 #define DMAR_RTADDR_REG 0x20
223 #define DMAR_RTADDR_RTT (1 << 11) /* Root Table Type */
224 #define DMAR_RTADDR_RTA_MASK 0xfffffffffffff000
225
226 /* Context Command register */
227 #define DMAR_CCMD_REG 0x28
228 #define DMAR_CCMD_ICC (1ULL << 63) /* Invalidate Context-Cache */
229 #define DMAR_CCMD_ICC32 (1U << 31)
230 #define DMAR_CCMD_CIRG_MASK (0x3ULL << 61) /* Context Invalidation
231 Request Granularity */
232 #define DMAR_CCMD_CIRG_GLOB (0x1ULL << 61) /* Global */
233 #define DMAR_CCMD_CIRG_DOM (0x2ULL << 61) /* Domain */
234 #define DMAR_CCMD_CIRG_DEV (0x3ULL << 61) /* Device */
235 #define DMAR_CCMD_CAIG(x) (((x) >> 59) & 0x3) /* Context Actual
236 Invalidation Granularity */
237 #define DMAR_CCMD_CAIG_GLOB 0x1 /* Global */
238 #define DMAR_CCMD_CAIG_DOM 0x2 /* Domain */
239 #define DMAR_CCMD_CAIG_DEV 0x3 /* Device */
240 #define DMAR_CCMD_FM (0x3UUL << 32) /* Function Mask */
241 #define DMAR_CCMD_SID(x) (((x) & 0xffff) << 16) /* Source-ID */
242 #define DMAR_CCMD_DID(x) ((x) & 0xffff) /* Domain-ID */
243
244 /* Invalidate Address register */
245 #define DMAR_IVA_REG_OFF 0
246 #define DMAR_IVA_IH (1 << 6) /* Invalidation Hint */
247 #define DMAR_IVA_AM(x) ((x) & 0x1f) /* Address Mask */
248 #define DMAR_IVA_ADDR(x) ((x) & ~0xfffULL) /* Address */
249
250 /* IOTLB Invalidate register */
251 #define DMAR_IOTLB_REG_OFF 0x8
252 #define DMAR_IOTLB_IVT (1ULL << 63) /* Invalidate IOTLB */
253 #define DMAR_IOTLB_IVT32 (1U << 31)
254 #define DMAR_IOTLB_IIRG_MASK (0x3ULL << 60) /* Invalidation Request
255 Granularity */
256 #define DMAR_IOTLB_IIRG_GLB (0x1ULL << 60) /* Global */
257 #define DMAR_IOTLB_IIRG_DOM (0x2ULL << 60) /* Domain-selective */
258 #define DMAR_IOTLB_IIRG_PAGE (0x3ULL << 60) /* Page-selective */
259 #define DMAR_IOTLB_IAIG_MASK (0x3ULL << 57) /* Actual Invalidation
260 Granularity */
261 #define DMAR_IOTLB_IAIG_INVLD 0 /* Hw detected error */
262 #define DMAR_IOTLB_IAIG_GLB (0x1ULL << 57) /* Global */
263 #define DMAR_IOTLB_IAIG_DOM (0x2ULL << 57) /* Domain-selective */
264 #define DMAR_IOTLB_IAIG_PAGE (0x3ULL << 57) /* Page-selective */
265 #define DMAR_IOTLB_DR (0x1ULL << 49) /* Drain Reads */
266 #define DMAR_IOTLB_DW (0x1ULL << 48) /* Drain Writes */
267 #define DMAR_IOTLB_DID(x) (((uint64_t)(x) & 0xffff) << 32) /* Domain Id */
268
269 /* Fault Status register */
270 #define DMAR_FSTS_REG 0x34
271 #define DMAR_FSTS_FRI(x) (((x) >> 8) & 0xff) /* Fault Record Index */
272 #define DMAR_FSTS_ITE (1 << 6) /* Invalidation Time-out */
273 #define DMAR_FSTS_ICE (1 << 5) /* Invalidation Completion */
274 #define DMAR_FSTS_IQE (1 << 4) /* Invalidation Queue */
275 #define DMAR_FSTS_APF (1 << 3) /* Advanced Pending Fault */
276 #define DMAR_FSTS_AFO (1 << 2) /* Advanced Fault Overflow */
277 #define DMAR_FSTS_PPF (1 << 1) /* Primary Pending Fault */
278 #define DMAR_FSTS_PFO 1 /* Fault Overflow */
279
280 /* Fault Event Control register */
281 #define DMAR_FECTL_REG 0x38
282 #define DMAR_FECTL_IM (1U << 31) /* Interrupt Mask */
283 #define DMAR_FECTL_IP (1 << 30) /* Interrupt Pending */
284
285 /* Fault Event Data register */
286 #define DMAR_FEDATA_REG 0x3c
287
288 /* Fault Event Address register */
289 #define DMAR_FEADDR_REG 0x40
290
291 /* Fault Event Upper Address register */
292 #define DMAR_FEUADDR_REG 0x44
293
294 /* Advanced Fault Log register */
295 #define DMAR_AFLOG_REG 0x58
296
297 /* Fault Recording Register, also usable for Advanced Fault Log records */
298 #define DMAR_FRCD2_F (1ULL << 63) /* Fault */
299 #define DMAR_FRCD2_F32 (1U << 31)
300 #define DMAR_FRCD2_T(x) ((int)((x >> 62) & 1)) /* Type */
301 #define DMAR_FRCD2_T_W 0 /* Write request */
302 #define DMAR_FRCD2_T_R 1 /* Read or AtomicOp */
303 #define DMAR_FRCD2_AT(x) ((int)((x >> 60) & 0x3)) /* Address Type */
304 #define DMAR_FRCD2_FR(x) ((int)((x >> 32) & 0xff)) /* Fault Reason */
305 #define DMAR_FRCD2_SID(x) ((int)(x & 0xffff)) /* Source Identifier */
306 #define DMAR_FRCS1_FI_MASK 0xffffffffff000 /* Fault Info, Address Mask */
307
308 /* Protected Memory Enable register */
309 #define DMAR_PMEN_REG 0x64
310 #define DMAR_PMEN_EPM (1U << 31) /* Enable Protected Memory */
311 #define DMAR_PMEN_PRS 1 /* Protected Region Status */
312
313 /* Protected Low-Memory Base register */
314 #define DMAR_PLMBASE_REG 0x68
315
316 /* Protected Low-Memory Limit register */
317 #define DMAR_PLMLIMIT_REG 0x6c
318
319 /* Protected High-Memory Base register */
320 #define DMAR_PHMBASE_REG 0x70
321
322 /* Protected High-Memory Limit register */
323 #define DMAR_PHMLIMIT_REG 0x78
324
325 /* Queued Invalidation Descriptors */
326 #define DMAR_IQ_DESCR_SZ_SHIFT 4 /* Shift for descriptor count
327 to ring offset */
328 #define DMAR_IQ_DESCR_SZ (1 << DMAR_IQ_DESCR_SZ_SHIFT)
329 /* Descriptor size */
330
331 /* Context-cache Invalidate Descriptor */
332 #define DMAR_IQ_DESCR_CTX_INV 0x1
333 #define DMAR_IQ_DESCR_CTX_GLOB (0x1 << 4) /* Granularity: Global */
334 #define DMAR_IQ_DESCR_CTX_DOM (0x2 << 4) /* Granularity: Domain */
335 #define DMAR_IQ_DESCR_CTX_DEV (0x3 << 4) /* Granularity: Device */
336 #define DMAR_IQ_DESCR_CTX_DID(x) (((uint32_t)(x)) << 16) /* Domain Id */
337 #define DMAR_IQ_DESCR_CTX_SRC(x) (((uint64_t)(x)) << 32) /* Source Id */
338 #define DMAR_IQ_DESCR_CTX_FM(x) (((uint64_t)(x)) << 48) /* Function Mask */
339
340 /* IOTLB Invalidate Descriptor */
341 #define DMAR_IQ_DESCR_IOTLB_INV 0x2
342 #define DMAR_IQ_DESCR_IOTLB_GLOB (0x1 << 4) /* Granularity: Global */
343 #define DMAR_IQ_DESCR_IOTLB_DOM (0x2 << 4) /* Granularity: Domain */
344 #define DMAR_IQ_DESCR_IOTLB_PAGE (0x3 << 4) /* Granularity: Page */
345 #define DMAR_IQ_DESCR_IOTLB_DW (1 << 6) /* Drain Writes */
346 #define DMAR_IQ_DESCR_IOTLB_DR (1 << 7) /* Drain Reads */
347 #define DMAR_IQ_DESCR_IOTLB_DID(x) (((uint32_t)(x)) << 16) /* Domain Id */
348
349 /* Device-TLB Invalidate Descriptor */
350 #define DMAR_IQ_DESCR_DTLB_INV 0x3
351
352 /* Invalidate Interrupt Entry Cache */
353 #define DMAR_IQ_DESCR_IEC_INV 0x4
354 #define DMAR_IQ_DESCR_IEC_IDX (1 << 4) /* Index-Selective Invalidation */
355 #define DMAR_IQ_DESCR_IEC_IIDX(x) (((uint64_t)x) << 32) /* Interrupt Index */
356 #define DMAR_IQ_DESCR_IEC_IM(x) ((x) << 27) /* Index Mask */
357
358 /* Invalidation Wait Descriptor */
359 #define DMAR_IQ_DESCR_WAIT_ID 0x5
360 #define DMAR_IQ_DESCR_WAIT_IF (1 << 4) /* Interrupt Flag */
361 #define DMAR_IQ_DESCR_WAIT_SW (1 << 5) /* Status Write */
362 #define DMAR_IQ_DESCR_WAIT_FN (1 << 6) /* Fence */
363 #define DMAR_IQ_DESCR_WAIT_SD(x) (((uint64_t)(x)) << 32) /* Status Data */
364
365 /* Extended IOTLB Invalidate Descriptor */
366 #define DMAR_IQ_DESCR_EIOTLB_INV 0x6
367
368 /* PASID-Cache Invalidate Descriptor */
369 #define DMAR_IQ_DESCR_PASIDC_INV 0x7
370
371 /* Extended Device-TLB Invalidate Descriptor */
372 #define DMAR_IQ_DESCR_EDTLB_INV 0x8
373
374 /* Invalidation Queue Head register */
375 #define DMAR_IQH_REG 0x80
376 #define DMAR_IQH_MASK 0x7fff0 /* Next cmd index mask */
377
378 /* Invalidation Queue Tail register */
379 #define DMAR_IQT_REG 0x88
380 #define DMAR_IQT_MASK 0x7fff0
381
382 /* Invalidation Queue Address register */
383 #define DMAR_IQA_REG 0x90
384 #define DMAR_IQA_IQA_MASK 0xfffffffffffff000 /* Invalidation Queue
385 Base Address mask */
386 #define DMAR_IQA_QS_MASK 0x7 /* Queue Size in pages */
387 #define DMAR_IQA_QS_MAX 0x7 /* Max Queue size */
388 #define DMAR_IQA_QS_DEF 3
389
390 /* Invalidation Completion Status register */
391 #define DMAR_ICS_REG 0x9c
392 #define DMAR_ICS_IWC 1 /* Invalidation Wait
393 Descriptor Complete */
394
395 /* Invalidation Event Control register */
396 #define DMAR_IECTL_REG 0xa0
397 #define DMAR_IECTL_IM (1U << 31) /* Interrupt Mask */
398 #define DMAR_IECTL_IP (1 << 30) /* Interrupt Pending */
399
400 /* Invalidation Event Data register */
401 #define DMAR_IEDATA_REG 0xa4
402
403 /* Invalidation Event Address register */
404 #define DMAR_IEADDR_REG 0xa8
405
406 /* Invalidation Event Upper Address register */
407 #define DMAR_IEUADDR_REG 0xac
408
409 /* Interrupt Remapping Table Address register */
410 #define DMAR_IRTA_REG 0xb8
411 #define DMAR_IRTA_EIME (1 << 11) /* Extended Interrupt Mode
412 Enable */
413 #define DMAR_IRTA_S_MASK 0xf /* Size Mask */
414
415 #endif
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