intel_utils.c

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    1 /*-
    2  * Copyright (c) 2013 The FreeBSD Foundation
    3  * All rights reserved.
    4  *
    5  * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
    6  * under sponsorship from the FreeBSD Foundation.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  */
   29 
   30 #include <sys/cdefs.h>
   31 __FBSDID("$FreeBSD: releng/10.1/sys/x86/iommu/intel_utils.c 259512 2013-12-17 13:49:35Z kib $");
   32 
   33 #include <sys/param.h>
   34 #include <sys/bus.h>
   35 #include <sys/kernel.h>
   36 #include <sys/lock.h>
   37 #include <sys/malloc.h>
   38 #include <sys/memdesc.h>
   39 #include <sys/mutex.h>
   40 #include <sys/proc.h>
   41 #include <sys/queue.h>
   42 #include <sys/rman.h>
   43 #include <sys/rwlock.h>
   44 #include <sys/sched.h>
   45 #include <sys/sf_buf.h>
   46 #include <sys/sysctl.h>
   47 #include <sys/systm.h>
   48 #include <sys/taskqueue.h>
   49 #include <sys/tree.h>
   50 #include <vm/vm.h>
   51 #include <vm/vm_extern.h>
   52 #include <vm/vm_kern.h>
   53 #include <vm/vm_object.h>
   54 #include <vm/vm_page.h>
   55 #include <vm/vm_map.h>
   56 #include <vm/vm_pageout.h>
   57 #include <machine/bus.h>
   58 #include <machine/cpu.h>
   59 #include <x86/include/busdma_impl.h>
   60 #include <x86/iommu/intel_reg.h>
   61 #include <x86/iommu/busdma_dmar.h>
   62 #include <x86/iommu/intel_dmar.h>
   63 
   64 u_int
   65 dmar_nd2mask(u_int nd)
   66 {
   67         static const u_int masks[] = {
   68                 0x000f, /* nd == 0 */
   69                 0x002f, /* nd == 1 */
   70                 0x00ff, /* nd == 2 */
   71                 0x02ff, /* nd == 3 */
   72                 0x0fff, /* nd == 4 */
   73                 0x2fff, /* nd == 5 */
   74                 0xffff, /* nd == 6 */
   75                 0x0000, /* nd == 7 reserved */
   76         };
   77 
   78         KASSERT(nd <= 6, ("number of domains %d", nd));
   79         return (masks[nd]);
   80 }
   81 
   82 static const struct sagaw_bits_tag {
   83         int agaw;
   84         int cap;
   85         int awlvl;
   86         int pglvl;
   87 } sagaw_bits[] = {
   88         {.agaw = 30, .cap = DMAR_CAP_SAGAW_2LVL, .awlvl = DMAR_CTX2_AW_2LVL,
   89             .pglvl = 2},
   90         {.agaw = 39, .cap = DMAR_CAP_SAGAW_3LVL, .awlvl = DMAR_CTX2_AW_3LVL,
   91             .pglvl = 3},
   92         {.agaw = 48, .cap = DMAR_CAP_SAGAW_4LVL, .awlvl = DMAR_CTX2_AW_4LVL,
   93             .pglvl = 4},
   94         {.agaw = 57, .cap = DMAR_CAP_SAGAW_5LVL, .awlvl = DMAR_CTX2_AW_5LVL,
   95             .pglvl = 5},
   96         {.agaw = 64, .cap = DMAR_CAP_SAGAW_6LVL, .awlvl = DMAR_CTX2_AW_6LVL,
   97             .pglvl = 6}
   98 };
   99 #define SIZEOF_SAGAW_BITS (sizeof(sagaw_bits) / sizeof(sagaw_bits[0]))
  100 
  101 bool
  102 dmar_pglvl_supported(struct dmar_unit *unit, int pglvl)
  103 {
  104         int i;
  105 
  106         for (i = 0; i < SIZEOF_SAGAW_BITS; i++) {
  107                 if (sagaw_bits[i].pglvl != pglvl)
  108                         continue;
  109                 if ((DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap) != 0)
  110                         return (true);
  111         }
  112         return (false);
  113 }
  114 
  115 int
  116 ctx_set_agaw(struct dmar_ctx *ctx, int mgaw)
  117 {
  118         int sagaw, i;
  119 
  120         ctx->mgaw = mgaw;
  121         sagaw = DMAR_CAP_SAGAW(ctx->dmar->hw_cap);
  122         for (i = 0; i < SIZEOF_SAGAW_BITS; i++) {
  123                 if (sagaw_bits[i].agaw >= mgaw) {
  124                         ctx->agaw = sagaw_bits[i].agaw;
  125                         ctx->pglvl = sagaw_bits[i].pglvl;
  126                         ctx->awlvl = sagaw_bits[i].awlvl;
  127                         return (0);
  128                 }
  129         }
  130         device_printf(ctx->dmar->dev,
  131             "context request mgaw %d for pci%d:%d:%d:%d, "
  132             "no agaw found, sagaw %x\n", mgaw, ctx->dmar->segment, ctx->bus,
  133              ctx->slot, ctx->func, sagaw);
  134         return (EINVAL);
  135 }
  136 
  137 /*
  138  * Find a best fit mgaw for the given maxaddr:
  139  *   - if allow_less is false, must find sagaw which maps all requested
  140  *     addresses (used by identity mappings);
  141  *   - if allow_less is true, and no supported sagaw can map all requested
  142  *     address space, accept the biggest sagaw, whatever is it.
  143  */
  144 int
  145 dmar_maxaddr2mgaw(struct dmar_unit *unit, dmar_gaddr_t maxaddr, bool allow_less)
  146 {
  147         int i;
  148 
  149         for (i = 0; i < SIZEOF_SAGAW_BITS; i++) {
  150                 if ((1ULL << sagaw_bits[i].agaw) >= maxaddr &&
  151                     (DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap) != 0)
  152                         break;
  153         }
  154         if (allow_less && i == SIZEOF_SAGAW_BITS) {
  155                 do {
  156                         i--;
  157                 } while ((DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap)
  158                     == 0);
  159         }
  160         if (i < SIZEOF_SAGAW_BITS)
  161                 return (sagaw_bits[i].agaw);
  162         KASSERT(0, ("no mgaw for maxaddr %jx allow_less %d",
  163             (uintmax_t) maxaddr, allow_less));
  164         return (-1);
  165 }
  166 
  167 /*
  168  * Calculate the total amount of page table pages needed to map the
  169  * whole bus address space on the context with the selected agaw.
  170  */
  171 vm_pindex_t
  172 pglvl_max_pages(int pglvl)
  173 {
  174         vm_pindex_t res;
  175         int i;
  176 
  177         for (res = 0, i = pglvl; i > 0; i--) {
  178                 res *= DMAR_NPTEPG;
  179                 res++;
  180         }
  181         return (res);
  182 }
  183 
  184 /*
  185  * Return true if the page table level lvl supports the superpage for
  186  * the context ctx.
  187  */
  188 int
  189 ctx_is_sp_lvl(struct dmar_ctx *ctx, int lvl)
  190 {
  191         int alvl, cap_sps;
  192         static const int sagaw_sp[] = {
  193                 DMAR_CAP_SPS_2M,
  194                 DMAR_CAP_SPS_1G,
  195                 DMAR_CAP_SPS_512G,
  196                 DMAR_CAP_SPS_1T
  197         };
  198 
  199         alvl = ctx->pglvl - lvl - 1;
  200         cap_sps = DMAR_CAP_SPS(ctx->dmar->hw_cap);
  201         return (alvl < sizeof(sagaw_sp) / sizeof(sagaw_sp[0]) &&
  202             (sagaw_sp[alvl] & cap_sps) != 0);
  203 }
  204 
  205 dmar_gaddr_t
  206 pglvl_page_size(int total_pglvl, int lvl)
  207 {
  208         int rlvl;
  209         static const dmar_gaddr_t pg_sz[] = {
  210                 (dmar_gaddr_t)DMAR_PAGE_SIZE,
  211                 (dmar_gaddr_t)DMAR_PAGE_SIZE << DMAR_NPTEPGSHIFT,
  212                 (dmar_gaddr_t)DMAR_PAGE_SIZE << (2 * DMAR_NPTEPGSHIFT),
  213                 (dmar_gaddr_t)DMAR_PAGE_SIZE << (3 * DMAR_NPTEPGSHIFT),
  214                 (dmar_gaddr_t)DMAR_PAGE_SIZE << (4 * DMAR_NPTEPGSHIFT),
  215                 (dmar_gaddr_t)DMAR_PAGE_SIZE << (5 * DMAR_NPTEPGSHIFT)
  216         };
  217 
  218         KASSERT(lvl >= 0 && lvl < total_pglvl,
  219             ("total %d lvl %d", total_pglvl, lvl));
  220         rlvl = total_pglvl - lvl - 1;
  221         KASSERT(rlvl < sizeof(pg_sz) / sizeof(pg_sz[0]),
  222             ("sizeof pg_sz lvl %d", lvl));
  223         return (pg_sz[rlvl]);
  224 }
  225 
  226 dmar_gaddr_t
  227 ctx_page_size(struct dmar_ctx *ctx, int lvl)
  228 {
  229 
  230         return (pglvl_page_size(ctx->pglvl, lvl));
  231 }
  232 
  233 int
  234 calc_am(struct dmar_unit *unit, dmar_gaddr_t base, dmar_gaddr_t size,
  235     dmar_gaddr_t *isizep)
  236 {
  237         dmar_gaddr_t isize;
  238         int am;
  239 
  240         for (am = DMAR_CAP_MAMV(unit->hw_cap);; am--) {
  241                 isize = 1ULL << (am + DMAR_PAGE_SHIFT);
  242                 if ((base & (isize - 1)) == 0 && size >= isize)
  243                         break;
  244                 if (am == 0)
  245                         break;
  246         }
  247         *isizep = isize;
  248         return (am);
  249 }
  250 
  251 dmar_haddr_t dmar_high;
  252 int haw;
  253 int dmar_tbl_pagecnt;
  254 
  255 vm_page_t
  256 dmar_pgalloc(vm_object_t obj, vm_pindex_t idx, int flags)
  257 {
  258         vm_page_t m;
  259         int zeroed;
  260 
  261         zeroed = (flags & DMAR_PGF_ZERO) != 0 ? VM_ALLOC_ZERO : 0;
  262         for (;;) {
  263                 if ((flags & DMAR_PGF_OBJL) == 0)
  264                         VM_OBJECT_WLOCK(obj);
  265                 m = vm_page_lookup(obj, idx);
  266                 if ((flags & DMAR_PGF_NOALLOC) != 0 || m != NULL) {
  267                         if ((flags & DMAR_PGF_OBJL) == 0)
  268                                 VM_OBJECT_WUNLOCK(obj);
  269                         break;
  270                 }
  271                 m = vm_page_alloc_contig(obj, idx, VM_ALLOC_NOBUSY |
  272                     VM_ALLOC_SYSTEM | VM_ALLOC_NODUMP | zeroed, 1, 0,
  273                     dmar_high, PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
  274                 if ((flags & DMAR_PGF_OBJL) == 0)
  275                         VM_OBJECT_WUNLOCK(obj);
  276                 if (m != NULL) {
  277                         if (zeroed && (m->flags & PG_ZERO) == 0)
  278                                 pmap_zero_page(m);
  279                         atomic_add_int(&dmar_tbl_pagecnt, 1);
  280                         break;
  281                 }
  282                 if ((flags & DMAR_PGF_WAITOK) == 0)
  283                         break;
  284                 if ((flags & DMAR_PGF_OBJL) != 0)
  285                         VM_OBJECT_WUNLOCK(obj);
  286                 VM_WAIT;
  287                 if ((flags & DMAR_PGF_OBJL) != 0)
  288                         VM_OBJECT_WLOCK(obj);
  289         }
  290         return (m);
  291 }
  292 
  293 void
  294 dmar_pgfree(vm_object_t obj, vm_pindex_t idx, int flags)
  295 {
  296         vm_page_t m;
  297 
  298         if ((flags & DMAR_PGF_OBJL) == 0)
  299                 VM_OBJECT_WLOCK(obj);
  300         m = vm_page_lookup(obj, idx);
  301         if (m != NULL) {
  302                 vm_page_free(m);
  303                 atomic_subtract_int(&dmar_tbl_pagecnt, 1);
  304         }
  305         if ((flags & DMAR_PGF_OBJL) == 0)
  306                 VM_OBJECT_WUNLOCK(obj);
  307 }
  308 
  309 void *
  310 dmar_map_pgtbl(vm_object_t obj, vm_pindex_t idx, int flags,
  311     struct sf_buf **sf)
  312 {
  313         vm_page_t m;
  314         bool allocated;
  315 
  316         if ((flags & DMAR_PGF_OBJL) == 0)
  317                 VM_OBJECT_WLOCK(obj);
  318         m = vm_page_lookup(obj, idx);
  319         if (m == NULL && (flags & DMAR_PGF_ALLOC) != 0) {
  320                 m = dmar_pgalloc(obj, idx, flags | DMAR_PGF_OBJL);
  321                 allocated = true;
  322         } else
  323                 allocated = false;
  324         if (m == NULL) {
  325                 if ((flags & DMAR_PGF_OBJL) == 0)
  326                         VM_OBJECT_WUNLOCK(obj);
  327                 return (NULL);
  328         }
  329         /* Sleepable allocations cannot fail. */
  330         if ((flags & DMAR_PGF_WAITOK) != 0)
  331                 VM_OBJECT_WUNLOCK(obj);
  332         sched_pin();
  333         *sf = sf_buf_alloc(m, SFB_CPUPRIVATE | ((flags & DMAR_PGF_WAITOK)
  334             == 0 ? SFB_NOWAIT : 0));
  335         if (*sf == NULL) {
  336                 sched_unpin();
  337                 if (allocated) {
  338                         VM_OBJECT_ASSERT_WLOCKED(obj);
  339                         dmar_pgfree(obj, m->pindex, flags | DMAR_PGF_OBJL);
  340                 }
  341                 if ((flags & DMAR_PGF_OBJL) == 0)
  342                         VM_OBJECT_WUNLOCK(obj);
  343                 return (NULL);
  344         }
  345         if ((flags & (DMAR_PGF_WAITOK | DMAR_PGF_OBJL)) ==
  346             (DMAR_PGF_WAITOK | DMAR_PGF_OBJL))
  347                 VM_OBJECT_WLOCK(obj);
  348         else if ((flags & (DMAR_PGF_WAITOK | DMAR_PGF_OBJL)) == 0)
  349                 VM_OBJECT_WUNLOCK(obj);
  350         return ((void *)sf_buf_kva(*sf));
  351 }
  352 
  353 void
  354 dmar_unmap_pgtbl(struct sf_buf *sf, bool coherent)
  355 {
  356         vm_page_t m;
  357 
  358         m = sf_buf_page(sf);
  359         sf_buf_free(sf);
  360         sched_unpin();
  361 
  362         /*
  363          * If DMAR does not snoop paging structures accesses, flush
  364          * CPU cache to memory.
  365          */
  366         if (!coherent)
  367                 pmap_invalidate_cache_pages(&m, 1);
  368 }
  369 
  370 /*
  371  * Load the root entry pointer into the hardware, busily waiting for
  372  * the completion.
  373  */
  374 int
  375 dmar_load_root_entry_ptr(struct dmar_unit *unit)
  376 {
  377         vm_page_t root_entry;
  378 
  379         /*
  380          * Access to the GCMD register must be serialized while the
  381          * command is submitted.
  382          */
  383         DMAR_ASSERT_LOCKED(unit);
  384 
  385         /* VM_OBJECT_RLOCK(unit->ctx_obj); */
  386         VM_OBJECT_WLOCK(unit->ctx_obj);
  387         root_entry = vm_page_lookup(unit->ctx_obj, 0);
  388         /* VM_OBJECT_RUNLOCK(unit->ctx_obj); */
  389         VM_OBJECT_WUNLOCK(unit->ctx_obj);
  390         dmar_write8(unit, DMAR_RTADDR_REG, VM_PAGE_TO_PHYS(root_entry));
  391         dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_SRTP);
  392         /* XXXKIB should have a timeout */
  393         while ((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_RTPS) == 0)
  394                 cpu_spinwait();
  395         return (0);
  396 }
  397 
  398 /*
  399  * Globally invalidate the context entries cache, busily waiting for
  400  * the completion.
  401  */
  402 int
  403 dmar_inv_ctx_glob(struct dmar_unit *unit)
  404 {
  405 
  406         /*
  407          * Access to the CCMD register must be serialized while the
  408          * command is submitted.
  409          */
  410         DMAR_ASSERT_LOCKED(unit);
  411         KASSERT(!unit->qi_enabled, ("QI enabled"));
  412 
  413         /*
  414          * The DMAR_CCMD_ICC bit in the upper dword should be written
  415          * after the low dword write is completed.  Amd64
  416          * dmar_write8() does not have this issue, i386 dmar_write8()
  417          * writes the upper dword last.
  418          */
  419         dmar_write8(unit, DMAR_CCMD_REG, DMAR_CCMD_ICC | DMAR_CCMD_CIRG_GLOB);
  420         /* XXXKIB should have a timeout */
  421         while ((dmar_read4(unit, DMAR_CCMD_REG + 4) & DMAR_CCMD_ICC32) != 0)
  422                 cpu_spinwait();
  423         return (0);
  424 }
  425 
  426 /*
  427  * Globally invalidate the IOTLB, busily waiting for the completion.
  428  */
  429 int
  430 dmar_inv_iotlb_glob(struct dmar_unit *unit)
  431 {
  432         int reg;
  433 
  434         DMAR_ASSERT_LOCKED(unit);
  435         KASSERT(!unit->qi_enabled, ("QI enabled"));
  436 
  437         reg = 16 * DMAR_ECAP_IRO(unit->hw_ecap);
  438         /* See a comment about DMAR_CCMD_ICC in dmar_inv_ctx_glob. */
  439         dmar_write8(unit, reg + DMAR_IOTLB_REG_OFF, DMAR_IOTLB_IVT |
  440             DMAR_IOTLB_IIRG_GLB | DMAR_IOTLB_DR | DMAR_IOTLB_DW);
  441         /* XXXKIB should have a timeout */
  442         while ((dmar_read4(unit, reg + DMAR_IOTLB_REG_OFF + 4) &
  443             DMAR_IOTLB_IVT32) != 0)
  444                 cpu_spinwait();
  445         return (0);
  446 }
  447 
  448 /*
  449  * Flush the chipset write buffers.  See 11.1 "Write Buffer Flushing"
  450  * in the architecture specification.
  451  */
  452 int
  453 dmar_flush_write_bufs(struct dmar_unit *unit)
  454 {
  455 
  456         DMAR_ASSERT_LOCKED(unit);
  457 
  458         /*
  459          * DMAR_GCMD_WBF is only valid when CAP_RWBF is reported.
  460          */
  461         KASSERT((unit->hw_cap & DMAR_CAP_RWBF) != 0,
  462             ("dmar%d: no RWBF", unit->unit));
  463 
  464         dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_WBF);
  465         /* XXXKIB should have a timeout */
  466         while ((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_WBFS) == 0)
  467                 cpu_spinwait();
  468         return (0);
  469 }
  470 
  471 int
  472 dmar_enable_translation(struct dmar_unit *unit)
  473 {
  474 
  475         DMAR_ASSERT_LOCKED(unit);
  476         unit->hw_gcmd |= DMAR_GCMD_TE;
  477         dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd);
  478         /* XXXKIB should have a timeout */
  479         while ((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_TES) == 0)
  480                 cpu_spinwait();
  481         return (0);
  482 }
  483 
  484 int
  485 dmar_disable_translation(struct dmar_unit *unit)
  486 {
  487 
  488         DMAR_ASSERT_LOCKED(unit);
  489         unit->hw_gcmd &= ~DMAR_GCMD_TE;
  490         dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd);
  491         /* XXXKIB should have a timeout */
  492         while ((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_TES) != 0)
  493                 cpu_spinwait();
  494         return (0);
  495 }
  496 
  497 #define BARRIER_F                               \
  498         u_int f_done, f_inproc, f_wakeup;       \
  499                                                 \
  500         f_done = 1 << (barrier_id * 3);         \
  501         f_inproc = 1 << (barrier_id * 3 + 1);   \
  502         f_wakeup = 1 << (barrier_id * 3 + 2)
  503 
  504 bool
  505 dmar_barrier_enter(struct dmar_unit *dmar, u_int barrier_id)
  506 {
  507         BARRIER_F;
  508 
  509         DMAR_LOCK(dmar);
  510         if ((dmar->barrier_flags & f_done) != 0) {
  511                 DMAR_UNLOCK(dmar);
  512                 return (false);
  513         }
  514 
  515         if ((dmar->barrier_flags & f_inproc) != 0) {
  516                 while ((dmar->barrier_flags & f_inproc) != 0) {
  517                         dmar->barrier_flags |= f_wakeup;
  518                         msleep(&dmar->barrier_flags, &dmar->lock, 0,
  519                             "dmarb", 0);
  520                 }
  521                 KASSERT((dmar->barrier_flags & f_done) != 0,
  522                     ("dmar%d barrier %d missing done", dmar->unit, barrier_id));
  523                 DMAR_UNLOCK(dmar);
  524                 return (false);
  525         }
  526 
  527         dmar->barrier_flags |= f_inproc;
  528         DMAR_UNLOCK(dmar);
  529         return (true);
  530 }
  531 
  532 void
  533 dmar_barrier_exit(struct dmar_unit *dmar, u_int barrier_id)
  534 {
  535         BARRIER_F;
  536 
  537         DMAR_ASSERT_LOCKED(dmar);
  538         KASSERT((dmar->barrier_flags & (f_done | f_inproc)) == f_inproc,
  539             ("dmar%d barrier %d missed entry", dmar->unit, barrier_id));
  540         dmar->barrier_flags |= f_done;
  541         if ((dmar->barrier_flags & f_wakeup) != 0)
  542                 wakeup(&dmar->barrier_flags);
  543         dmar->barrier_flags &= ~(f_inproc | f_wakeup);
  544         DMAR_UNLOCK(dmar);
  545 }
  546 
  547 int dmar_match_verbose;
  548 
  549 static SYSCTL_NODE(_hw, OID_AUTO, dmar, CTLFLAG_RD, NULL,
  550     "");
  551 SYSCTL_INT(_hw_dmar, OID_AUTO, tbl_pagecnt, CTLFLAG_RD | CTLFLAG_TUN,
  552     &dmar_tbl_pagecnt, 0,
  553     "Count of pages used for DMAR pagetables");
  554 SYSCTL_INT(_hw_dmar, OID_AUTO, match_verbose, CTLFLAG_RW | CTLFLAG_TUN,
  555     &dmar_match_verbose, 0,
  556     "Verbose matching of the PCI devices to DMAR paths");
  557 #ifdef INVARIANTS
  558 int dmar_check_free;
  559 SYSCTL_INT(_hw_dmar, OID_AUTO, check_free, CTLFLAG_RW | CTLFLAG_TUN,
  560     &dmar_check_free, 0,
  561     "Check the GPA RBtree for free_down and free_after validity");
  562 #endif
  563
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FreeBSD/Linux Kernel Cross Reference sys/x86/iommu/intel_utils.c

FreeBSD/Linux Kernel Cross Reference
sys/x86/iommu/intel_utils.c
