1 /*-
2 * Copyright (c) 2013 The FreeBSD Foundation
3 * All rights reserved.
4 *
5 * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
6 * under sponsorship from the FreeBSD Foundation.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD: releng/11.0/sys/x86/iommu/intel_utils.c 298144 2016-04-17 10:56:56Z kib $");
32
33 #include <sys/param.h>
34 #include <sys/bus.h>
35 #include <sys/kernel.h>
36 #include <sys/lock.h>
37 #include <sys/malloc.h>
38 #include <sys/memdesc.h>
39 #include <sys/mutex.h>
40 #include <sys/proc.h>
41 #include <sys/queue.h>
42 #include <sys/rman.h>
43 #include <sys/rwlock.h>
44 #include <sys/sched.h>
45 #include <sys/sf_buf.h>
46 #include <sys/sysctl.h>
47 #include <sys/systm.h>
48 #include <sys/taskqueue.h>
49 #include <sys/tree.h>
50 #include <sys/vmem.h>
51 #include <dev/pci/pcivar.h>
52 #include <vm/vm.h>
53 #include <vm/vm_extern.h>
54 #include <vm/vm_kern.h>
55 #include <vm/vm_object.h>
56 #include <vm/vm_page.h>
57 #include <vm/vm_map.h>
58 #include <vm/vm_pageout.h>
59 #include <machine/bus.h>
60 #include <machine/cpu.h>
61 #include <machine/intr_machdep.h>
62 #include <x86/include/apicvar.h>
63 #include <x86/include/busdma_impl.h>
64 #include <x86/iommu/intel_reg.h>
65 #include <x86/iommu/busdma_dmar.h>
66 #include <x86/iommu/intel_dmar.h>
67
68 u_int
69 dmar_nd2mask(u_int nd)
70 {
71 static const u_int masks[] = {
72 0x000f, /* nd == 0 */
73 0x002f, /* nd == 1 */
74 0x00ff, /* nd == 2 */
75 0x02ff, /* nd == 3 */
76 0x0fff, /* nd == 4 */
77 0x2fff, /* nd == 5 */
78 0xffff, /* nd == 6 */
79 0x0000, /* nd == 7 reserved */
80 };
81
82 KASSERT(nd <= 6, ("number of domains %d", nd));
83 return (masks[nd]);
84 }
85
86 static const struct sagaw_bits_tag {
87 int agaw;
88 int cap;
89 int awlvl;
90 int pglvl;
91 } sagaw_bits[] = {
92 {.agaw = 30, .cap = DMAR_CAP_SAGAW_2LVL, .awlvl = DMAR_CTX2_AW_2LVL,
93 .pglvl = 2},
94 {.agaw = 39, .cap = DMAR_CAP_SAGAW_3LVL, .awlvl = DMAR_CTX2_AW_3LVL,
95 .pglvl = 3},
96 {.agaw = 48, .cap = DMAR_CAP_SAGAW_4LVL, .awlvl = DMAR_CTX2_AW_4LVL,
97 .pglvl = 4},
98 {.agaw = 57, .cap = DMAR_CAP_SAGAW_5LVL, .awlvl = DMAR_CTX2_AW_5LVL,
99 .pglvl = 5},
100 {.agaw = 64, .cap = DMAR_CAP_SAGAW_6LVL, .awlvl = DMAR_CTX2_AW_6LVL,
101 .pglvl = 6}
102 };
103
104 bool
105 dmar_pglvl_supported(struct dmar_unit *unit, int pglvl)
106 {
107 int i;
108
109 for (i = 0; i < nitems(sagaw_bits); i++) {
110 if (sagaw_bits[i].pglvl != pglvl)
111 continue;
112 if ((DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap) != 0)
113 return (true);
114 }
115 return (false);
116 }
117
118 int
119 domain_set_agaw(struct dmar_domain *domain, int mgaw)
120 {
121 int sagaw, i;
122
123 domain->mgaw = mgaw;
124 sagaw = DMAR_CAP_SAGAW(domain->dmar->hw_cap);
125 for (i = 0; i < nitems(sagaw_bits); i++) {
126 if (sagaw_bits[i].agaw >= mgaw) {
127 domain->agaw = sagaw_bits[i].agaw;
128 domain->pglvl = sagaw_bits[i].pglvl;
129 domain->awlvl = sagaw_bits[i].awlvl;
130 return (0);
131 }
132 }
133 device_printf(domain->dmar->dev,
134 "context request mgaw %d: no agaw found, sagaw %x\n",
135 mgaw, sagaw);
136 return (EINVAL);
137 }
138
139 /*
140 * Find a best fit mgaw for the given maxaddr:
141 * - if allow_less is false, must find sagaw which maps all requested
142 * addresses (used by identity mappings);
143 * - if allow_less is true, and no supported sagaw can map all requested
144 * address space, accept the biggest sagaw, whatever is it.
145 */
146 int
147 dmar_maxaddr2mgaw(struct dmar_unit *unit, dmar_gaddr_t maxaddr, bool allow_less)
148 {
149 int i;
150
151 for (i = 0; i < nitems(sagaw_bits); i++) {
152 if ((1ULL << sagaw_bits[i].agaw) >= maxaddr &&
153 (DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap) != 0)
154 break;
155 }
156 if (allow_less && i == nitems(sagaw_bits)) {
157 do {
158 i--;
159 } while ((DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap)
160 == 0);
161 }
162 if (i < nitems(sagaw_bits))
163 return (sagaw_bits[i].agaw);
164 KASSERT(0, ("no mgaw for maxaddr %jx allow_less %d",
165 (uintmax_t) maxaddr, allow_less));
166 return (-1);
167 }
168
169 /*
170 * Calculate the total amount of page table pages needed to map the
171 * whole bus address space on the context with the selected agaw.
172 */
173 vm_pindex_t
174 pglvl_max_pages(int pglvl)
175 {
176 vm_pindex_t res;
177 int i;
178
179 for (res = 0, i = pglvl; i > 0; i--) {
180 res *= DMAR_NPTEPG;
181 res++;
182 }
183 return (res);
184 }
185
186 /*
187 * Return true if the page table level lvl supports the superpage for
188 * the context ctx.
189 */
190 int
191 domain_is_sp_lvl(struct dmar_domain *domain, int lvl)
192 {
193 int alvl, cap_sps;
194 static const int sagaw_sp[] = {
195 DMAR_CAP_SPS_2M,
196 DMAR_CAP_SPS_1G,
197 DMAR_CAP_SPS_512G,
198 DMAR_CAP_SPS_1T
199 };
200
201 alvl = domain->pglvl - lvl - 1;
202 cap_sps = DMAR_CAP_SPS(domain->dmar->hw_cap);
203 return (alvl < nitems(sagaw_sp) && (sagaw_sp[alvl] & cap_sps) != 0);
204 }
205
206 dmar_gaddr_t
207 pglvl_page_size(int total_pglvl, int lvl)
208 {
209 int rlvl;
210 static const dmar_gaddr_t pg_sz[] = {
211 (dmar_gaddr_t)DMAR_PAGE_SIZE,
212 (dmar_gaddr_t)DMAR_PAGE_SIZE << DMAR_NPTEPGSHIFT,
213 (dmar_gaddr_t)DMAR_PAGE_SIZE << (2 * DMAR_NPTEPGSHIFT),
214 (dmar_gaddr_t)DMAR_PAGE_SIZE << (3 * DMAR_NPTEPGSHIFT),
215 (dmar_gaddr_t)DMAR_PAGE_SIZE << (4 * DMAR_NPTEPGSHIFT),
216 (dmar_gaddr_t)DMAR_PAGE_SIZE << (5 * DMAR_NPTEPGSHIFT)
217 };
218
219 KASSERT(lvl >= 0 && lvl < total_pglvl,
220 ("total %d lvl %d", total_pglvl, lvl));
221 rlvl = total_pglvl - lvl - 1;
222 KASSERT(rlvl < nitems(pg_sz), ("sizeof pg_sz lvl %d", lvl));
223 return (pg_sz[rlvl]);
224 }
225
226 dmar_gaddr_t
227 domain_page_size(struct dmar_domain *domain, int lvl)
228 {
229
230 return (pglvl_page_size(domain->pglvl, lvl));
231 }
232
233 int
234 calc_am(struct dmar_unit *unit, dmar_gaddr_t base, dmar_gaddr_t size,
235 dmar_gaddr_t *isizep)
236 {
237 dmar_gaddr_t isize;
238 int am;
239
240 for (am = DMAR_CAP_MAMV(unit->hw_cap);; am--) {
241 isize = 1ULL << (am + DMAR_PAGE_SHIFT);
242 if ((base & (isize - 1)) == 0 && size >= isize)
243 break;
244 if (am == 0)
245 break;
246 }
247 *isizep = isize;
248 return (am);
249 }
250
251 dmar_haddr_t dmar_high;
252 int haw;
253 int dmar_tbl_pagecnt;
254
255 vm_page_t
256 dmar_pgalloc(vm_object_t obj, vm_pindex_t idx, int flags)
257 {
258 vm_page_t m;
259 int zeroed;
260
261 zeroed = (flags & DMAR_PGF_ZERO) != 0 ? VM_ALLOC_ZERO : 0;
262 for (;;) {
263 if ((flags & DMAR_PGF_OBJL) == 0)
264 VM_OBJECT_WLOCK(obj);
265 m = vm_page_lookup(obj, idx);
266 if ((flags & DMAR_PGF_NOALLOC) != 0 || m != NULL) {
267 if ((flags & DMAR_PGF_OBJL) == 0)
268 VM_OBJECT_WUNLOCK(obj);
269 break;
270 }
271 m = vm_page_alloc_contig(obj, idx, VM_ALLOC_NOBUSY |
272 VM_ALLOC_SYSTEM | VM_ALLOC_NODUMP | zeroed, 1, 0,
273 dmar_high, PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
274 if ((flags & DMAR_PGF_OBJL) == 0)
275 VM_OBJECT_WUNLOCK(obj);
276 if (m != NULL) {
277 if (zeroed && (m->flags & PG_ZERO) == 0)
278 pmap_zero_page(m);
279 atomic_add_int(&dmar_tbl_pagecnt, 1);
280 break;
281 }
282 if ((flags & DMAR_PGF_WAITOK) == 0)
283 break;
284 if ((flags & DMAR_PGF_OBJL) != 0)
285 VM_OBJECT_WUNLOCK(obj);
286 VM_WAIT;
287 if ((flags & DMAR_PGF_OBJL) != 0)
288 VM_OBJECT_WLOCK(obj);
289 }
290 return (m);
291 }
292
293 void
294 dmar_pgfree(vm_object_t obj, vm_pindex_t idx, int flags)
295 {
296 vm_page_t m;
297
298 if ((flags & DMAR_PGF_OBJL) == 0)
299 VM_OBJECT_WLOCK(obj);
300 m = vm_page_lookup(obj, idx);
301 if (m != NULL) {
302 vm_page_free(m);
303 atomic_subtract_int(&dmar_tbl_pagecnt, 1);
304 }
305 if ((flags & DMAR_PGF_OBJL) == 0)
306 VM_OBJECT_WUNLOCK(obj);
307 }
308
309 void *
310 dmar_map_pgtbl(vm_object_t obj, vm_pindex_t idx, int flags,
311 struct sf_buf **sf)
312 {
313 vm_page_t m;
314 bool allocated;
315
316 if ((flags & DMAR_PGF_OBJL) == 0)
317 VM_OBJECT_WLOCK(obj);
318 m = vm_page_lookup(obj, idx);
319 if (m == NULL && (flags & DMAR_PGF_ALLOC) != 0) {
320 m = dmar_pgalloc(obj, idx, flags | DMAR_PGF_OBJL);
321 allocated = true;
322 } else
323 allocated = false;
324 if (m == NULL) {
325 if ((flags & DMAR_PGF_OBJL) == 0)
326 VM_OBJECT_WUNLOCK(obj);
327 return (NULL);
328 }
329 /* Sleepable allocations cannot fail. */
330 if ((flags & DMAR_PGF_WAITOK) != 0)
331 VM_OBJECT_WUNLOCK(obj);
332 sched_pin();
333 *sf = sf_buf_alloc(m, SFB_CPUPRIVATE | ((flags & DMAR_PGF_WAITOK)
334 == 0 ? SFB_NOWAIT : 0));
335 if (*sf == NULL) {
336 sched_unpin();
337 if (allocated) {
338 VM_OBJECT_ASSERT_WLOCKED(obj);
339 dmar_pgfree(obj, m->pindex, flags | DMAR_PGF_OBJL);
340 }
341 if ((flags & DMAR_PGF_OBJL) == 0)
342 VM_OBJECT_WUNLOCK(obj);
343 return (NULL);
344 }
345 if ((flags & (DMAR_PGF_WAITOK | DMAR_PGF_OBJL)) ==
346 (DMAR_PGF_WAITOK | DMAR_PGF_OBJL))
347 VM_OBJECT_WLOCK(obj);
348 else if ((flags & (DMAR_PGF_WAITOK | DMAR_PGF_OBJL)) == 0)
349 VM_OBJECT_WUNLOCK(obj);
350 return ((void *)sf_buf_kva(*sf));
351 }
352
353 void
354 dmar_unmap_pgtbl(struct sf_buf *sf)
355 {
356
357 sf_buf_free(sf);
358 sched_unpin();
359 }
360
361 static void
362 dmar_flush_transl_to_ram(struct dmar_unit *unit, void *dst, size_t sz)
363 {
364
365 if (DMAR_IS_COHERENT(unit))
366 return;
367 /*
368 * If DMAR does not snoop paging structures accesses, flush
369 * CPU cache to memory.
370 */
371 pmap_invalidate_cache_range((uintptr_t)dst, (uintptr_t)dst + sz,
372 TRUE);
373 }
374
375 void
376 dmar_flush_pte_to_ram(struct dmar_unit *unit, dmar_pte_t *dst)
377 {
378
379 dmar_flush_transl_to_ram(unit, dst, sizeof(*dst));
380 }
381
382 void
383 dmar_flush_ctx_to_ram(struct dmar_unit *unit, dmar_ctx_entry_t *dst)
384 {
385
386 dmar_flush_transl_to_ram(unit, dst, sizeof(*dst));
387 }
388
389 void
390 dmar_flush_root_to_ram(struct dmar_unit *unit, dmar_root_entry_t *dst)
391 {
392
393 dmar_flush_transl_to_ram(unit, dst, sizeof(*dst));
394 }
395
396 /*
397 * Load the root entry pointer into the hardware, busily waiting for
398 * the completion.
399 */
400 int
401 dmar_load_root_entry_ptr(struct dmar_unit *unit)
402 {
403 vm_page_t root_entry;
404
405 /*
406 * Access to the GCMD register must be serialized while the
407 * command is submitted.
408 */
409 DMAR_ASSERT_LOCKED(unit);
410
411 VM_OBJECT_RLOCK(unit->ctx_obj);
412 root_entry = vm_page_lookup(unit->ctx_obj, 0);
413 VM_OBJECT_RUNLOCK(unit->ctx_obj);
414 dmar_write8(unit, DMAR_RTADDR_REG, VM_PAGE_TO_PHYS(root_entry));
415 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_SRTP);
416 /* XXXKIB should have a timeout */
417 while ((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_RTPS) == 0)
418 cpu_spinwait();
419 return (0);
420 }
421
422 /*
423 * Globally invalidate the context entries cache, busily waiting for
424 * the completion.
425 */
426 int
427 dmar_inv_ctx_glob(struct dmar_unit *unit)
428 {
429
430 /*
431 * Access to the CCMD register must be serialized while the
432 * command is submitted.
433 */
434 DMAR_ASSERT_LOCKED(unit);
435 KASSERT(!unit->qi_enabled, ("QI enabled"));
436
437 /*
438 * The DMAR_CCMD_ICC bit in the upper dword should be written
439 * after the low dword write is completed. Amd64
440 * dmar_write8() does not have this issue, i386 dmar_write8()
441 * writes the upper dword last.
442 */
443 dmar_write8(unit, DMAR_CCMD_REG, DMAR_CCMD_ICC | DMAR_CCMD_CIRG_GLOB);
444 /* XXXKIB should have a timeout */
445 while ((dmar_read4(unit, DMAR_CCMD_REG + 4) & DMAR_CCMD_ICC32) != 0)
446 cpu_spinwait();
447 return (0);
448 }
449
450 /*
451 * Globally invalidate the IOTLB, busily waiting for the completion.
452 */
453 int
454 dmar_inv_iotlb_glob(struct dmar_unit *unit)
455 {
456 int reg;
457
458 DMAR_ASSERT_LOCKED(unit);
459 KASSERT(!unit->qi_enabled, ("QI enabled"));
460
461 reg = 16 * DMAR_ECAP_IRO(unit->hw_ecap);
462 /* See a comment about DMAR_CCMD_ICC in dmar_inv_ctx_glob. */
463 dmar_write8(unit, reg + DMAR_IOTLB_REG_OFF, DMAR_IOTLB_IVT |
464 DMAR_IOTLB_IIRG_GLB | DMAR_IOTLB_DR | DMAR_IOTLB_DW);
465 /* XXXKIB should have a timeout */
466 while ((dmar_read4(unit, reg + DMAR_IOTLB_REG_OFF + 4) &
467 DMAR_IOTLB_IVT32) != 0)
468 cpu_spinwait();
469 return (0);
470 }
471
472 /*
473 * Flush the chipset write buffers. See 11.1 "Write Buffer Flushing"
474 * in the architecture specification.
475 */
476 int
477 dmar_flush_write_bufs(struct dmar_unit *unit)
478 {
479
480 DMAR_ASSERT_LOCKED(unit);
481
482 /*
483 * DMAR_GCMD_WBF is only valid when CAP_RWBF is reported.
484 */
485 KASSERT((unit->hw_cap & DMAR_CAP_RWBF) != 0,
486 ("dmar%d: no RWBF", unit->unit));
487
488 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_WBF);
489 /* XXXKIB should have a timeout */
490 while ((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_WBFS) == 0)
491 cpu_spinwait();
492 return (0);
493 }
494
495 int
496 dmar_enable_translation(struct dmar_unit *unit)
497 {
498
499 DMAR_ASSERT_LOCKED(unit);
500 unit->hw_gcmd |= DMAR_GCMD_TE;
501 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd);
502 /* XXXKIB should have a timeout */
503 while ((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_TES) == 0)
504 cpu_spinwait();
505 return (0);
506 }
507
508 int
509 dmar_disable_translation(struct dmar_unit *unit)
510 {
511
512 DMAR_ASSERT_LOCKED(unit);
513 unit->hw_gcmd &= ~DMAR_GCMD_TE;
514 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd);
515 /* XXXKIB should have a timeout */
516 while ((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_TES) != 0)
517 cpu_spinwait();
518 return (0);
519 }
520
521 int
522 dmar_load_irt_ptr(struct dmar_unit *unit)
523 {
524 uint64_t irta, s;
525
526 DMAR_ASSERT_LOCKED(unit);
527 irta = unit->irt_phys;
528 if (DMAR_X2APIC(unit))
529 irta |= DMAR_IRTA_EIME;
530 s = fls(unit->irte_cnt) - 2;
531 KASSERT(unit->irte_cnt >= 2 && s <= DMAR_IRTA_S_MASK &&
532 powerof2(unit->irte_cnt),
533 ("IRTA_REG_S overflow %x", unit->irte_cnt));
534 irta |= s;
535 dmar_write8(unit, DMAR_IRTA_REG, irta);
536 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_SIRTP);
537 /* XXXKIB should have a timeout */
538 while ((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRTPS) == 0)
539 cpu_spinwait();
540 return (0);
541 }
542
543 int
544 dmar_enable_ir(struct dmar_unit *unit)
545 {
546
547 DMAR_ASSERT_LOCKED(unit);
548 unit->hw_gcmd |= DMAR_GCMD_IRE;
549 unit->hw_gcmd &= ~DMAR_GCMD_CFI;
550 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd);
551 /* XXXKIB should have a timeout */
552 while ((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRES) == 0)
553 cpu_spinwait();
554 return (0);
555 }
556
557 int
558 dmar_disable_ir(struct dmar_unit *unit)
559 {
560
561 DMAR_ASSERT_LOCKED(unit);
562 unit->hw_gcmd &= ~DMAR_GCMD_IRE;
563 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd);
564 /* XXXKIB should have a timeout */
565 while ((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRES) != 0)
566 cpu_spinwait();
567 return (0);
568 }
569
570 #define BARRIER_F \
571 u_int f_done, f_inproc, f_wakeup; \
572 \
573 f_done = 1 << (barrier_id * 3); \
574 f_inproc = 1 << (barrier_id * 3 + 1); \
575 f_wakeup = 1 << (barrier_id * 3 + 2)
576
577 bool
578 dmar_barrier_enter(struct dmar_unit *dmar, u_int barrier_id)
579 {
580 BARRIER_F;
581
582 DMAR_LOCK(dmar);
583 if ((dmar->barrier_flags & f_done) != 0) {
584 DMAR_UNLOCK(dmar);
585 return (false);
586 }
587
588 if ((dmar->barrier_flags & f_inproc) != 0) {
589 while ((dmar->barrier_flags & f_inproc) != 0) {
590 dmar->barrier_flags |= f_wakeup;
591 msleep(&dmar->barrier_flags, &dmar->lock, 0,
592 "dmarb", 0);
593 }
594 KASSERT((dmar->barrier_flags & f_done) != 0,
595 ("dmar%d barrier %d missing done", dmar->unit, barrier_id));
596 DMAR_UNLOCK(dmar);
597 return (false);
598 }
599
600 dmar->barrier_flags |= f_inproc;
601 DMAR_UNLOCK(dmar);
602 return (true);
603 }
604
605 void
606 dmar_barrier_exit(struct dmar_unit *dmar, u_int barrier_id)
607 {
608 BARRIER_F;
609
610 DMAR_ASSERT_LOCKED(dmar);
611 KASSERT((dmar->barrier_flags & (f_done | f_inproc)) == f_inproc,
612 ("dmar%d barrier %d missed entry", dmar->unit, barrier_id));
613 dmar->barrier_flags |= f_done;
614 if ((dmar->barrier_flags & f_wakeup) != 0)
615 wakeup(&dmar->barrier_flags);
616 dmar->barrier_flags &= ~(f_inproc | f_wakeup);
617 DMAR_UNLOCK(dmar);
618 }
619
620 int dmar_match_verbose;
621 int dmar_batch_coalesce = 100;
622
623 static SYSCTL_NODE(_hw, OID_AUTO, dmar, CTLFLAG_RD, NULL, "");
624 SYSCTL_INT(_hw_dmar, OID_AUTO, tbl_pagecnt, CTLFLAG_RD,
625 &dmar_tbl_pagecnt, 0,
626 "Count of pages used for DMAR pagetables");
627 SYSCTL_INT(_hw_dmar, OID_AUTO, match_verbose, CTLFLAG_RWTUN,
628 &dmar_match_verbose, 0,
629 "Verbose matching of the PCI devices to DMAR paths");
630 SYSCTL_INT(_hw_dmar, OID_AUTO, batch_coalesce, CTLFLAG_RWTUN,
631 &dmar_batch_coalesce, 0,
632 "Number of qi batches between interrupt");
633 #ifdef INVARIANTS
634 int dmar_check_free;
635 SYSCTL_INT(_hw_dmar, OID_AUTO, check_free, CTLFLAG_RWTUN,
636 &dmar_check_free, 0,
637 "Check the GPA RBtree for free_down and free_after validity");
638 #endif
639
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