The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/x86/iommu/intel_utils.c

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2013 The FreeBSD Foundation
    5  * All rights reserved.
    6  *
    7  * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
    8  * under sponsorship from the FreeBSD Foundation.
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  *
   19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   22  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   29  * SUCH DAMAGE.
   30  */
   31 
   32 #include <sys/cdefs.h>
   33 __FBSDID("$FreeBSD: stable/12/sys/x86/iommu/intel_utils.c 355086 2019-11-25 09:43:36Z kib $");
   34 
   35 #include <sys/param.h>
   36 #include <sys/bus.h>
   37 #include <sys/kernel.h>
   38 #include <sys/lock.h>
   39 #include <sys/malloc.h>
   40 #include <sys/memdesc.h>
   41 #include <sys/mutex.h>
   42 #include <sys/proc.h>
   43 #include <sys/queue.h>
   44 #include <sys/rman.h>
   45 #include <sys/rwlock.h>
   46 #include <sys/sched.h>
   47 #include <sys/sf_buf.h>
   48 #include <sys/sysctl.h>
   49 #include <sys/systm.h>
   50 #include <sys/taskqueue.h>
   51 #include <sys/time.h>
   52 #include <sys/tree.h>
   53 #include <sys/vmem.h>
   54 #include <dev/pci/pcivar.h>
   55 #include <vm/vm.h>
   56 #include <vm/vm_extern.h>
   57 #include <vm/vm_kern.h>
   58 #include <vm/vm_object.h>
   59 #include <vm/vm_page.h>
   60 #include <vm/vm_map.h>
   61 #include <vm/vm_pageout.h>
   62 #include <machine/bus.h>
   63 #include <machine/cpu.h>
   64 #include <machine/intr_machdep.h>
   65 #include <x86/include/apicvar.h>
   66 #include <x86/include/busdma_impl.h>
   67 #include <x86/iommu/intel_reg.h>
   68 #include <x86/iommu/busdma_dmar.h>
   69 #include <dev/pci/pcireg.h>
   70 #include <x86/iommu/intel_dmar.h>
   71 
   72 u_int
   73 dmar_nd2mask(u_int nd)
   74 {
   75         static const u_int masks[] = {
   76                 0x000f, /* nd == 0 */
   77                 0x002f, /* nd == 1 */
   78                 0x00ff, /* nd == 2 */
   79                 0x02ff, /* nd == 3 */
   80                 0x0fff, /* nd == 4 */
   81                 0x2fff, /* nd == 5 */
   82                 0xffff, /* nd == 6 */
   83                 0x0000, /* nd == 7 reserved */
   84         };
   85 
   86         KASSERT(nd <= 6, ("number of domains %d", nd));
   87         return (masks[nd]);
   88 }
   89 
   90 static const struct sagaw_bits_tag {
   91         int agaw;
   92         int cap;
   93         int awlvl;
   94         int pglvl;
   95 } sagaw_bits[] = {
   96         {.agaw = 30, .cap = DMAR_CAP_SAGAW_2LVL, .awlvl = DMAR_CTX2_AW_2LVL,
   97             .pglvl = 2},
   98         {.agaw = 39, .cap = DMAR_CAP_SAGAW_3LVL, .awlvl = DMAR_CTX2_AW_3LVL,
   99             .pglvl = 3},
  100         {.agaw = 48, .cap = DMAR_CAP_SAGAW_4LVL, .awlvl = DMAR_CTX2_AW_4LVL,
  101             .pglvl = 4},
  102         {.agaw = 57, .cap = DMAR_CAP_SAGAW_5LVL, .awlvl = DMAR_CTX2_AW_5LVL,
  103             .pglvl = 5},
  104         {.agaw = 64, .cap = DMAR_CAP_SAGAW_6LVL, .awlvl = DMAR_CTX2_AW_6LVL,
  105             .pglvl = 6}
  106 };
  107 
  108 bool
  109 dmar_pglvl_supported(struct dmar_unit *unit, int pglvl)
  110 {
  111         int i;
  112 
  113         for (i = 0; i < nitems(sagaw_bits); i++) {
  114                 if (sagaw_bits[i].pglvl != pglvl)
  115                         continue;
  116                 if ((DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap) != 0)
  117                         return (true);
  118         }
  119         return (false);
  120 }
  121 
  122 int
  123 domain_set_agaw(struct dmar_domain *domain, int mgaw)
  124 {
  125         int sagaw, i;
  126 
  127         domain->mgaw = mgaw;
  128         sagaw = DMAR_CAP_SAGAW(domain->dmar->hw_cap);
  129         for (i = 0; i < nitems(sagaw_bits); i++) {
  130                 if (sagaw_bits[i].agaw >= mgaw) {
  131                         domain->agaw = sagaw_bits[i].agaw;
  132                         domain->pglvl = sagaw_bits[i].pglvl;
  133                         domain->awlvl = sagaw_bits[i].awlvl;
  134                         return (0);
  135                 }
  136         }
  137         device_printf(domain->dmar->dev,
  138             "context request mgaw %d: no agaw found, sagaw %x\n",
  139             mgaw, sagaw);
  140         return (EINVAL);
  141 }
  142 
  143 /*
  144  * Find a best fit mgaw for the given maxaddr:
  145  *   - if allow_less is false, must find sagaw which maps all requested
  146  *     addresses (used by identity mappings);
  147  *   - if allow_less is true, and no supported sagaw can map all requested
  148  *     address space, accept the biggest sagaw, whatever is it.
  149  */
  150 int
  151 dmar_maxaddr2mgaw(struct dmar_unit *unit, dmar_gaddr_t maxaddr, bool allow_less)
  152 {
  153         int i;
  154 
  155         for (i = 0; i < nitems(sagaw_bits); i++) {
  156                 if ((1ULL << sagaw_bits[i].agaw) >= maxaddr &&
  157                     (DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap) != 0)
  158                         break;
  159         }
  160         if (allow_less && i == nitems(sagaw_bits)) {
  161                 do {
  162                         i--;
  163                 } while ((DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap)
  164                     == 0);
  165         }
  166         if (i < nitems(sagaw_bits))
  167                 return (sagaw_bits[i].agaw);
  168         KASSERT(0, ("no mgaw for maxaddr %jx allow_less %d",
  169             (uintmax_t) maxaddr, allow_less));
  170         return (-1);
  171 }
  172 
  173 /*
  174  * Calculate the total amount of page table pages needed to map the
  175  * whole bus address space on the context with the selected agaw.
  176  */
  177 vm_pindex_t
  178 pglvl_max_pages(int pglvl)
  179 {
  180         vm_pindex_t res;
  181         int i;
  182 
  183         for (res = 0, i = pglvl; i > 0; i--) {
  184                 res *= DMAR_NPTEPG;
  185                 res++;
  186         }
  187         return (res);
  188 }
  189 
  190 /*
  191  * Return true if the page table level lvl supports the superpage for
  192  * the context ctx.
  193  */
  194 int
  195 domain_is_sp_lvl(struct dmar_domain *domain, int lvl)
  196 {
  197         int alvl, cap_sps;
  198         static const int sagaw_sp[] = {
  199                 DMAR_CAP_SPS_2M,
  200                 DMAR_CAP_SPS_1G,
  201                 DMAR_CAP_SPS_512G,
  202                 DMAR_CAP_SPS_1T
  203         };
  204 
  205         alvl = domain->pglvl - lvl - 1;
  206         cap_sps = DMAR_CAP_SPS(domain->dmar->hw_cap);
  207         return (alvl < nitems(sagaw_sp) && (sagaw_sp[alvl] & cap_sps) != 0);
  208 }
  209 
  210 dmar_gaddr_t
  211 pglvl_page_size(int total_pglvl, int lvl)
  212 {
  213         int rlvl;
  214         static const dmar_gaddr_t pg_sz[] = {
  215                 (dmar_gaddr_t)DMAR_PAGE_SIZE,
  216                 (dmar_gaddr_t)DMAR_PAGE_SIZE << DMAR_NPTEPGSHIFT,
  217                 (dmar_gaddr_t)DMAR_PAGE_SIZE << (2 * DMAR_NPTEPGSHIFT),
  218                 (dmar_gaddr_t)DMAR_PAGE_SIZE << (3 * DMAR_NPTEPGSHIFT),
  219                 (dmar_gaddr_t)DMAR_PAGE_SIZE << (4 * DMAR_NPTEPGSHIFT),
  220                 (dmar_gaddr_t)DMAR_PAGE_SIZE << (5 * DMAR_NPTEPGSHIFT)
  221         };
  222 
  223         KASSERT(lvl >= 0 && lvl < total_pglvl,
  224             ("total %d lvl %d", total_pglvl, lvl));
  225         rlvl = total_pglvl - lvl - 1;
  226         KASSERT(rlvl < nitems(pg_sz), ("sizeof pg_sz lvl %d", lvl));
  227         return (pg_sz[rlvl]);
  228 }
  229 
  230 dmar_gaddr_t
  231 domain_page_size(struct dmar_domain *domain, int lvl)
  232 {
  233 
  234         return (pglvl_page_size(domain->pglvl, lvl));
  235 }
  236 
  237 int
  238 calc_am(struct dmar_unit *unit, dmar_gaddr_t base, dmar_gaddr_t size,
  239     dmar_gaddr_t *isizep)
  240 {
  241         dmar_gaddr_t isize;
  242         int am;
  243 
  244         for (am = DMAR_CAP_MAMV(unit->hw_cap);; am--) {
  245                 isize = 1ULL << (am + DMAR_PAGE_SHIFT);
  246                 if ((base & (isize - 1)) == 0 && size >= isize)
  247                         break;
  248                 if (am == 0)
  249                         break;
  250         }
  251         *isizep = isize;
  252         return (am);
  253 }
  254 
  255 dmar_haddr_t dmar_high;
  256 int haw;
  257 int dmar_tbl_pagecnt;
  258 
  259 vm_page_t
  260 dmar_pgalloc(vm_object_t obj, vm_pindex_t idx, int flags)
  261 {
  262         vm_page_t m;
  263         int zeroed, aflags;
  264 
  265         zeroed = (flags & DMAR_PGF_ZERO) != 0 ? VM_ALLOC_ZERO : 0;
  266         aflags = zeroed | VM_ALLOC_NOBUSY | VM_ALLOC_SYSTEM | VM_ALLOC_NODUMP |
  267             ((flags & DMAR_PGF_WAITOK) != 0 ? VM_ALLOC_WAITFAIL :
  268             VM_ALLOC_NOWAIT);
  269         for (;;) {
  270                 if ((flags & DMAR_PGF_OBJL) == 0)
  271                         VM_OBJECT_WLOCK(obj);
  272                 m = vm_page_lookup(obj, idx);
  273                 if ((flags & DMAR_PGF_NOALLOC) != 0 || m != NULL) {
  274                         if ((flags & DMAR_PGF_OBJL) == 0)
  275                                 VM_OBJECT_WUNLOCK(obj);
  276                         break;
  277                 }
  278                 m = vm_page_alloc_contig(obj, idx, aflags, 1, 0,
  279                     dmar_high, PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
  280                 if ((flags & DMAR_PGF_OBJL) == 0)
  281                         VM_OBJECT_WUNLOCK(obj);
  282                 if (m != NULL) {
  283                         if (zeroed && (m->flags & PG_ZERO) == 0)
  284                                 pmap_zero_page(m);
  285                         atomic_add_int(&dmar_tbl_pagecnt, 1);
  286                         break;
  287                 }
  288                 if ((flags & DMAR_PGF_WAITOK) == 0)
  289                         break;
  290         }
  291         return (m);
  292 }
  293 
  294 void
  295 dmar_pgfree(vm_object_t obj, vm_pindex_t idx, int flags)
  296 {
  297         vm_page_t m;
  298 
  299         if ((flags & DMAR_PGF_OBJL) == 0)
  300                 VM_OBJECT_WLOCK(obj);
  301         m = vm_page_lookup(obj, idx);
  302         if (m != NULL) {
  303                 vm_page_free(m);
  304                 atomic_subtract_int(&dmar_tbl_pagecnt, 1);
  305         }
  306         if ((flags & DMAR_PGF_OBJL) == 0)
  307                 VM_OBJECT_WUNLOCK(obj);
  308 }
  309 
  310 void *
  311 dmar_map_pgtbl(vm_object_t obj, vm_pindex_t idx, int flags,
  312     struct sf_buf **sf)
  313 {
  314         vm_page_t m;
  315         bool allocated;
  316 
  317         if ((flags & DMAR_PGF_OBJL) == 0)
  318                 VM_OBJECT_WLOCK(obj);
  319         m = vm_page_lookup(obj, idx);
  320         if (m == NULL && (flags & DMAR_PGF_ALLOC) != 0) {
  321                 m = dmar_pgalloc(obj, idx, flags | DMAR_PGF_OBJL);
  322                 allocated = true;
  323         } else
  324                 allocated = false;
  325         if (m == NULL) {
  326                 if ((flags & DMAR_PGF_OBJL) == 0)
  327                         VM_OBJECT_WUNLOCK(obj);
  328                 return (NULL);
  329         }
  330         /* Sleepable allocations cannot fail. */
  331         if ((flags & DMAR_PGF_WAITOK) != 0)
  332                 VM_OBJECT_WUNLOCK(obj);
  333         sched_pin();
  334         *sf = sf_buf_alloc(m, SFB_CPUPRIVATE | ((flags & DMAR_PGF_WAITOK)
  335             == 0 ? SFB_NOWAIT : 0));
  336         if (*sf == NULL) {
  337                 sched_unpin();
  338                 if (allocated) {
  339                         VM_OBJECT_ASSERT_WLOCKED(obj);
  340                         dmar_pgfree(obj, m->pindex, flags | DMAR_PGF_OBJL);
  341                 }
  342                 if ((flags & DMAR_PGF_OBJL) == 0)
  343                         VM_OBJECT_WUNLOCK(obj);
  344                 return (NULL);
  345         }
  346         if ((flags & (DMAR_PGF_WAITOK | DMAR_PGF_OBJL)) ==
  347             (DMAR_PGF_WAITOK | DMAR_PGF_OBJL))
  348                 VM_OBJECT_WLOCK(obj);
  349         else if ((flags & (DMAR_PGF_WAITOK | DMAR_PGF_OBJL)) == 0)
  350                 VM_OBJECT_WUNLOCK(obj);
  351         return ((void *)sf_buf_kva(*sf));
  352 }
  353 
  354 void
  355 dmar_unmap_pgtbl(struct sf_buf *sf)
  356 {
  357 
  358         sf_buf_free(sf);
  359         sched_unpin();
  360 }
  361 
  362 static void
  363 dmar_flush_transl_to_ram(struct dmar_unit *unit, void *dst, size_t sz)
  364 {
  365 
  366         if (DMAR_IS_COHERENT(unit))
  367                 return;
  368         /*
  369          * If DMAR does not snoop paging structures accesses, flush
  370          * CPU cache to memory.
  371          */
  372         pmap_force_invalidate_cache_range((uintptr_t)dst, (uintptr_t)dst + sz);
  373 }
  374 
  375 void
  376 dmar_flush_pte_to_ram(struct dmar_unit *unit, dmar_pte_t *dst)
  377 {
  378 
  379         dmar_flush_transl_to_ram(unit, dst, sizeof(*dst));
  380 }
  381 
  382 void
  383 dmar_flush_ctx_to_ram(struct dmar_unit *unit, dmar_ctx_entry_t *dst)
  384 {
  385 
  386         dmar_flush_transl_to_ram(unit, dst, sizeof(*dst));
  387 }
  388 
  389 void
  390 dmar_flush_root_to_ram(struct dmar_unit *unit, dmar_root_entry_t *dst)
  391 {
  392 
  393         dmar_flush_transl_to_ram(unit, dst, sizeof(*dst));
  394 }
  395 
  396 /*
  397  * Load the root entry pointer into the hardware, busily waiting for
  398  * the completion.
  399  */
  400 int
  401 dmar_load_root_entry_ptr(struct dmar_unit *unit)
  402 {
  403         vm_page_t root_entry;
  404         int error;
  405 
  406         /*
  407          * Access to the GCMD register must be serialized while the
  408          * command is submitted.
  409          */
  410         DMAR_ASSERT_LOCKED(unit);
  411 
  412         VM_OBJECT_RLOCK(unit->ctx_obj);
  413         root_entry = vm_page_lookup(unit->ctx_obj, 0);
  414         VM_OBJECT_RUNLOCK(unit->ctx_obj);
  415         dmar_write8(unit, DMAR_RTADDR_REG, VM_PAGE_TO_PHYS(root_entry));
  416         dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_SRTP);
  417         DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_RTPS)
  418             != 0));
  419         return (error);
  420 }
  421 
  422 /*
  423  * Globally invalidate the context entries cache, busily waiting for
  424  * the completion.
  425  */
  426 int
  427 dmar_inv_ctx_glob(struct dmar_unit *unit)
  428 {
  429         int error;
  430 
  431         /*
  432          * Access to the CCMD register must be serialized while the
  433          * command is submitted.
  434          */
  435         DMAR_ASSERT_LOCKED(unit);
  436         KASSERT(!unit->qi_enabled, ("QI enabled"));
  437 
  438         /*
  439          * The DMAR_CCMD_ICC bit in the upper dword should be written
  440          * after the low dword write is completed.  Amd64
  441          * dmar_write8() does not have this issue, i386 dmar_write8()
  442          * writes the upper dword last.
  443          */
  444         dmar_write8(unit, DMAR_CCMD_REG, DMAR_CCMD_ICC | DMAR_CCMD_CIRG_GLOB);
  445         DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_CCMD_REG + 4) & DMAR_CCMD_ICC32)
  446             == 0));
  447         return (error);
  448 }
  449 
  450 /*
  451  * Globally invalidate the IOTLB, busily waiting for the completion.
  452  */
  453 int
  454 dmar_inv_iotlb_glob(struct dmar_unit *unit)
  455 {
  456         int error, reg;
  457 
  458         DMAR_ASSERT_LOCKED(unit);
  459         KASSERT(!unit->qi_enabled, ("QI enabled"));
  460 
  461         reg = 16 * DMAR_ECAP_IRO(unit->hw_ecap);
  462         /* See a comment about DMAR_CCMD_ICC in dmar_inv_ctx_glob. */
  463         dmar_write8(unit, reg + DMAR_IOTLB_REG_OFF, DMAR_IOTLB_IVT |
  464             DMAR_IOTLB_IIRG_GLB | DMAR_IOTLB_DR | DMAR_IOTLB_DW);
  465         DMAR_WAIT_UNTIL(((dmar_read4(unit, reg + DMAR_IOTLB_REG_OFF + 4) &
  466             DMAR_IOTLB_IVT32) == 0));
  467         return (error);
  468 }
  469 
  470 /*
  471  * Flush the chipset write buffers.  See 11.1 "Write Buffer Flushing"
  472  * in the architecture specification.
  473  */
  474 int
  475 dmar_flush_write_bufs(struct dmar_unit *unit)
  476 {
  477         int error;
  478 
  479         DMAR_ASSERT_LOCKED(unit);
  480 
  481         /*
  482          * DMAR_GCMD_WBF is only valid when CAP_RWBF is reported.
  483          */
  484         KASSERT((unit->hw_cap & DMAR_CAP_RWBF) != 0,
  485             ("dmar%d: no RWBF", unit->unit));
  486 
  487         dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_WBF);
  488         DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_WBFS)
  489             != 0));
  490         return (error);
  491 }
  492 
  493 int
  494 dmar_enable_translation(struct dmar_unit *unit)
  495 {
  496         int error;
  497 
  498         DMAR_ASSERT_LOCKED(unit);
  499         unit->hw_gcmd |= DMAR_GCMD_TE;
  500         dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd);
  501         DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_TES)
  502             != 0));
  503         return (error);
  504 }
  505 
  506 int
  507 dmar_disable_translation(struct dmar_unit *unit)
  508 {
  509         int error;
  510 
  511         DMAR_ASSERT_LOCKED(unit);
  512         unit->hw_gcmd &= ~DMAR_GCMD_TE;
  513         dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd);
  514         DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_TES)
  515             == 0));
  516         return (error);
  517 }
  518 
  519 int
  520 dmar_load_irt_ptr(struct dmar_unit *unit)
  521 {
  522         uint64_t irta, s;
  523         int error;
  524 
  525         DMAR_ASSERT_LOCKED(unit);
  526         irta = unit->irt_phys;
  527         if (DMAR_X2APIC(unit))
  528                 irta |= DMAR_IRTA_EIME;
  529         s = fls(unit->irte_cnt) - 2;
  530         KASSERT(unit->irte_cnt >= 2 && s <= DMAR_IRTA_S_MASK &&
  531             powerof2(unit->irte_cnt),
  532             ("IRTA_REG_S overflow %x", unit->irte_cnt));
  533         irta |= s;
  534         dmar_write8(unit, DMAR_IRTA_REG, irta);
  535         dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_SIRTP);
  536         DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRTPS)
  537             != 0));
  538         return (error);
  539 }
  540 
  541 int
  542 dmar_enable_ir(struct dmar_unit *unit)
  543 {
  544         int error;
  545 
  546         DMAR_ASSERT_LOCKED(unit);
  547         unit->hw_gcmd |= DMAR_GCMD_IRE;
  548         unit->hw_gcmd &= ~DMAR_GCMD_CFI;
  549         dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd);
  550         DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRES)
  551             != 0));
  552         return (error);
  553 }
  554 
  555 int
  556 dmar_disable_ir(struct dmar_unit *unit)
  557 {
  558         int error;
  559 
  560         DMAR_ASSERT_LOCKED(unit);
  561         unit->hw_gcmd &= ~DMAR_GCMD_IRE;
  562         dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd);
  563         DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRES)
  564             == 0));
  565         return (error);
  566 }
  567 
  568 #define BARRIER_F                               \
  569         u_int f_done, f_inproc, f_wakeup;       \
  570                                                 \
  571         f_done = 1 << (barrier_id * 3);         \
  572         f_inproc = 1 << (barrier_id * 3 + 1);   \
  573         f_wakeup = 1 << (barrier_id * 3 + 2)
  574 
  575 bool
  576 dmar_barrier_enter(struct dmar_unit *dmar, u_int barrier_id)
  577 {
  578         BARRIER_F;
  579 
  580         DMAR_LOCK(dmar);
  581         if ((dmar->barrier_flags & f_done) != 0) {
  582                 DMAR_UNLOCK(dmar);
  583                 return (false);
  584         }
  585 
  586         if ((dmar->barrier_flags & f_inproc) != 0) {
  587                 while ((dmar->barrier_flags & f_inproc) != 0) {
  588                         dmar->barrier_flags |= f_wakeup;
  589                         msleep(&dmar->barrier_flags, &dmar->lock, 0,
  590                             "dmarb", 0);
  591                 }
  592                 KASSERT((dmar->barrier_flags & f_done) != 0,
  593                     ("dmar%d barrier %d missing done", dmar->unit, barrier_id));
  594                 DMAR_UNLOCK(dmar);
  595                 return (false);
  596         }
  597 
  598         dmar->barrier_flags |= f_inproc;
  599         DMAR_UNLOCK(dmar);
  600         return (true);
  601 }
  602 
  603 void
  604 dmar_barrier_exit(struct dmar_unit *dmar, u_int barrier_id)
  605 {
  606         BARRIER_F;
  607 
  608         DMAR_ASSERT_LOCKED(dmar);
  609         KASSERT((dmar->barrier_flags & (f_done | f_inproc)) == f_inproc,
  610             ("dmar%d barrier %d missed entry", dmar->unit, barrier_id));
  611         dmar->barrier_flags |= f_done;
  612         if ((dmar->barrier_flags & f_wakeup) != 0)
  613                 wakeup(&dmar->barrier_flags);
  614         dmar->barrier_flags &= ~(f_inproc | f_wakeup);
  615         DMAR_UNLOCK(dmar);
  616 }
  617 
  618 int dmar_batch_coalesce = 100;
  619 struct timespec dmar_hw_timeout = {
  620         .tv_sec = 0,
  621         .tv_nsec = 1000000
  622 };
  623 
  624 static const uint64_t d = 1000000000;
  625 
  626 void
  627 dmar_update_timeout(uint64_t newval)
  628 {
  629 
  630         /* XXXKIB not atomic */
  631         dmar_hw_timeout.tv_sec = newval / d;
  632         dmar_hw_timeout.tv_nsec = newval % d;
  633 }
  634 
  635 uint64_t
  636 dmar_get_timeout(void)
  637 {
  638 
  639         return ((uint64_t)dmar_hw_timeout.tv_sec * d +
  640             dmar_hw_timeout.tv_nsec);
  641 }
  642 
  643 static int
  644 dmar_timeout_sysctl(SYSCTL_HANDLER_ARGS)
  645 {
  646         uint64_t val;
  647         int error;
  648 
  649         val = dmar_get_timeout();
  650         error = sysctl_handle_long(oidp, &val, 0, req);
  651         if (error != 0 || req->newptr == NULL)
  652                 return (error);
  653         dmar_update_timeout(val);
  654         return (error);
  655 }
  656 
  657 static SYSCTL_NODE(_hw, OID_AUTO, dmar, CTLFLAG_RD, NULL, "");
  658 SYSCTL_INT(_hw_dmar, OID_AUTO, tbl_pagecnt, CTLFLAG_RD,
  659     &dmar_tbl_pagecnt, 0,
  660     "Count of pages used for DMAR pagetables");
  661 SYSCTL_INT(_hw_dmar, OID_AUTO, batch_coalesce, CTLFLAG_RWTUN,
  662     &dmar_batch_coalesce, 0,
  663     "Number of qi batches between interrupt");
  664 SYSCTL_PROC(_hw_dmar, OID_AUTO, timeout,
  665     CTLTYPE_U64 | CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 0,
  666     dmar_timeout_sysctl, "QU",
  667     "Timeout for command wait, in nanoseconds");
  668 #ifdef INVARIANTS
  669 int dmar_check_free;
  670 SYSCTL_INT(_hw_dmar, OID_AUTO, check_free, CTLFLAG_RWTUN,
  671     &dmar_check_free, 0,
  672     "Check the GPA RBtree for free_down and free_after validity");
  673 #endif
  674 

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