Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/x86/pci/pci_bus.c
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1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD: releng/10.4/sys/x86/pci/pci_bus.c 280970 2015-04-01 21:48:54Z jhb $"); 29 30 #include "opt_cpu.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/kernel.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/rman.h> 39 #include <sys/sysctl.h> 40 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcib_private.h> 44 #include <isa/isavar.h> 45 #ifdef CPU_ELAN 46 #include <machine/md_var.h> 47 #endif 48 #include <x86/legacyvar.h> 49 #include <machine/pci_cfgreg.h> 50 #include <machine/resource.h> 51 52 #include "pcib_if.h" 53 54 int 55 legacy_pcib_maxslots(device_t dev) 56 { 57 return 31; 58 } 59 60 /* read configuration space register */ 61 62 uint32_t 63 legacy_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 64 u_int reg, int bytes) 65 { 66 return(pci_cfgregread(bus, slot, func, reg, bytes)); 67 } 68 69 /* write configuration space register */ 70 71 void 72 legacy_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 73 u_int reg, uint32_t data, int bytes) 74 { 75 pci_cfgregwrite(bus, slot, func, reg, data, bytes); 76 } 77 78 /* route interrupt */ 79 80 static int 81 legacy_pcib_route_interrupt(device_t pcib, device_t dev, int pin) 82 { 83 84 #ifdef __HAVE_PIR 85 return (pci_pir_route_interrupt(pci_get_bus(dev), pci_get_slot(dev), 86 pci_get_function(dev), pin)); 87 #else 88 /* No routing possible */ 89 return (PCI_INVALID_IRQ); 90 #endif 91 } 92 93 /* Pass MSI requests up to the nexus. */ 94 95 int 96 legacy_pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, 97 int *irqs) 98 { 99 device_t bus; 100 101 bus = device_get_parent(pcib); 102 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount, 103 irqs)); 104 } 105 106 int 107 legacy_pcib_alloc_msix(device_t pcib, device_t dev, int *irq) 108 { 109 device_t bus; 110 111 bus = device_get_parent(pcib); 112 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq)); 113 } 114 115 int 116 legacy_pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 117 uint32_t *data) 118 { 119 device_t bus, hostb; 120 int error, func, slot; 121 122 bus = device_get_parent(pcib); 123 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data); 124 if (error) 125 return (error); 126 127 slot = legacy_get_pcislot(pcib); 128 func = legacy_get_pcifunc(pcib); 129 if (slot == -1 || func == -1) 130 return (0); 131 hostb = pci_find_bsf(0, slot, func); 132 KASSERT(hostb != NULL, ("%s: missing hostb for 0:%d:%d", __func__, 133 slot, func)); 134 pci_ht_map_msi(hostb, *addr); 135 return (0); 136 } 137 138 static const char * 139 legacy_pcib_is_host_bridge(int bus, int slot, int func, 140 uint32_t id, uint8_t class, uint8_t subclass, 141 uint8_t *busnum) 142 { 143 #ifdef __i386__ 144 const char *s = NULL; 145 static uint8_t pxb[4]; /* hack for 450nx */ 146 147 *busnum = 0; 148 149 switch (id) { 150 case 0x12258086: 151 s = "Intel 824?? host to PCI bridge"; 152 /* XXX This is a guess */ 153 /* *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x41, 1); */ 154 *busnum = bus; 155 break; 156 case 0x71208086: 157 s = "Intel 82810 (i810 GMCH) Host To Hub bridge"; 158 break; 159 case 0x71228086: 160 s = "Intel 82810-DC100 (i810-DC100 GMCH) Host To Hub bridge"; 161 break; 162 case 0x71248086: 163 s = "Intel 82810E (i810E GMCH) Host To Hub bridge"; 164 break; 165 case 0x11308086: 166 s = "Intel 82815 (i815 GMCH) Host To Hub bridge"; 167 break; 168 case 0x71808086: 169 s = "Intel 82443LX (440 LX) host to PCI bridge"; 170 break; 171 case 0x71908086: 172 s = "Intel 82443BX (440 BX) host to PCI bridge"; 173 break; 174 case 0x71928086: 175 s = "Intel 82443BX host to PCI bridge (AGP disabled)"; 176 break; 177 case 0x71948086: 178 s = "Intel 82443MX host to PCI bridge"; 179 break; 180 case 0x71a08086: 181 s = "Intel 82443GX host to PCI bridge"; 182 break; 183 case 0x71a18086: 184 s = "Intel 82443GX host to AGP bridge"; 185 break; 186 case 0x71a28086: 187 s = "Intel 82443GX host to PCI bridge (AGP disabled)"; 188 break; 189 case 0x84c48086: 190 s = "Intel 82454KX/GX (Orion) host to PCI bridge"; 191 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x4a, 1); 192 break; 193 case 0x84ca8086: 194 /* 195 * For the 450nx chipset, there is a whole bundle of 196 * things pretending to be host bridges. The MIOC will 197 * be seen first and isn't really a pci bridge (the 198 * actual busses are attached to the PXB's). We need to 199 * read the registers of the MIOC to figure out the 200 * bus numbers for the PXB channels. 201 * 202 * Since the MIOC doesn't have a pci bus attached, we 203 * pretend it wasn't there. 204 */ 205 pxb[0] = legacy_pcib_read_config(0, bus, slot, func, 206 0xd0, 1); /* BUSNO[0] */ 207 pxb[1] = legacy_pcib_read_config(0, bus, slot, func, 208 0xd1, 1) + 1; /* SUBA[0]+1 */ 209 pxb[2] = legacy_pcib_read_config(0, bus, slot, func, 210 0xd3, 1); /* BUSNO[1] */ 211 pxb[3] = legacy_pcib_read_config(0, bus, slot, func, 212 0xd4, 1) + 1; /* SUBA[1]+1 */ 213 return NULL; 214 case 0x84cb8086: 215 switch (slot) { 216 case 0x12: 217 s = "Intel 82454NX PXB#0, Bus#A"; 218 *busnum = pxb[0]; 219 break; 220 case 0x13: 221 s = "Intel 82454NX PXB#0, Bus#B"; 222 *busnum = pxb[1]; 223 break; 224 case 0x14: 225 s = "Intel 82454NX PXB#1, Bus#A"; 226 *busnum = pxb[2]; 227 break; 228 case 0x15: 229 s = "Intel 82454NX PXB#1, Bus#B"; 230 *busnum = pxb[3]; 231 break; 232 } 233 break; 234 case 0x1A308086: 235 s = "Intel 82845 Host to PCI bridge"; 236 break; 237 238 /* AMD -- vendor 0x1022 */ 239 case 0x30001022: 240 s = "AMD Elan SC520 host to PCI bridge"; 241 #ifdef CPU_ELAN 242 init_AMD_Elan_sc520(); 243 #else 244 printf( 245 "*** WARNING: missing CPU_ELAN -- timekeeping may be wrong\n"); 246 #endif 247 break; 248 case 0x70061022: 249 s = "AMD-751 host to PCI bridge"; 250 break; 251 case 0x700e1022: 252 s = "AMD-761 host to PCI bridge"; 253 break; 254 255 /* SiS -- vendor 0x1039 */ 256 case 0x04961039: 257 s = "SiS 85c496"; 258 break; 259 case 0x04061039: 260 s = "SiS 85c501"; 261 break; 262 case 0x06011039: 263 s = "SiS 85c601"; 264 break; 265 case 0x55911039: 266 s = "SiS 5591 host to PCI bridge"; 267 break; 268 case 0x00011039: 269 s = "SiS 5591 host to AGP bridge"; 270 break; 271 272 /* VLSI -- vendor 0x1004 */ 273 case 0x00051004: 274 s = "VLSI 82C592 Host to PCI bridge"; 275 break; 276 277 /* XXX Here is MVP3, I got the datasheet but NO M/B to test it */ 278 /* totally. Please let me know if anything wrong. -F */ 279 /* XXX need info on the MVP3 -- any takers? */ 280 case 0x05981106: 281 s = "VIA 82C598MVP (Apollo MVP3) host bridge"; 282 break; 283 284 /* AcerLabs -- vendor 0x10b9 */ 285 /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */ 286 /* id is '10b9" but the register always shows "10b9". -Foxfair */ 287 case 0x154110b9: 288 s = "AcerLabs M1541 (Aladdin-V) PCI host bridge"; 289 break; 290 291 /* OPTi -- vendor 0x1045 */ 292 case 0xc7011045: 293 s = "OPTi 82C700 host to PCI bridge"; 294 break; 295 case 0xc8221045: 296 s = "OPTi 82C822 host to PCI Bridge"; 297 break; 298 299 /* ServerWorks -- vendor 0x1166 */ 300 case 0x00051166: 301 s = "ServerWorks NB6536 2.0HE host to PCI bridge"; 302 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); 303 break; 304 305 case 0x00061166: 306 /* FALLTHROUGH */ 307 case 0x00081166: 308 /* FALLTHROUGH */ 309 case 0x02011166: 310 /* FALLTHROUGH */ 311 case 0x010f1014: /* IBM re-badged ServerWorks chipset */ 312 s = "ServerWorks host to PCI bridge"; 313 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); 314 break; 315 316 case 0x00091166: 317 s = "ServerWorks NB6635 3.0LE host to PCI bridge"; 318 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); 319 break; 320 321 case 0x00101166: 322 s = "ServerWorks CIOB30 host to PCI bridge"; 323 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); 324 break; 325 326 case 0x00111166: 327 /* FALLTHROUGH */ 328 case 0x03021014: /* IBM re-badged ServerWorks chipset */ 329 s = "ServerWorks CMIC-HE host to PCI-X bridge"; 330 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); 331 break; 332 333 /* XXX unknown chipset, but working */ 334 case 0x00171166: 335 /* FALLTHROUGH */ 336 case 0x01011166: 337 case 0x01101166: 338 case 0x02251166: 339 s = "ServerWorks host to PCI bridge(unknown chipset)"; 340 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); 341 break; 342 343 /* Compaq/HP -- vendor 0x0e11 */ 344 case 0x60100e11: 345 s = "Compaq/HP Model 6010 HotPlug PCI Bridge"; 346 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0xc8, 1); 347 break; 348 349 /* Integrated Micro Solutions -- vendor 0x10e0 */ 350 case 0x884910e0: 351 s = "Integrated Micro Solutions VL Bridge"; 352 break; 353 354 default: 355 if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST) 356 s = "Host to PCI bridge"; 357 break; 358 } 359 360 return s; 361 #else 362 const char *s = NULL; 363 364 *busnum = 0; 365 if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST) 366 s = "Host to PCI bridge"; 367 return s; 368 #endif 369 } 370 371 /* 372 * Scan the first pci bus for host-pci bridges and add pcib instances 373 * to the nexus for each bridge. 374 */ 375 static void 376 legacy_pcib_identify(driver_t *driver, device_t parent) 377 { 378 int bus, slot, func; 379 uint8_t hdrtype; 380 int found = 0; 381 int pcifunchigh; 382 int found824xx = 0; 383 int found_orion = 0; 384 device_t child; 385 devclass_t pci_devclass; 386 387 if (pci_cfgregopen() == 0) 388 return; 389 /* 390 * Check to see if we haven't already had a PCI bus added 391 * via some other means. If we have, bail since otherwise 392 * we're going to end up duplicating it. 393 */ 394 if ((pci_devclass = devclass_find("pci")) && 395 devclass_get_device(pci_devclass, 0)) 396 return; 397 398 399 bus = 0; 400 retry: 401 for (slot = 0; slot <= PCI_SLOTMAX; slot++) { 402 func = 0; 403 hdrtype = legacy_pcib_read_config(0, bus, slot, func, 404 PCIR_HDRTYPE, 1); 405 /* 406 * When enumerating bus devices, the standard says that 407 * one should check the header type and ignore the slots whose 408 * header types that the software doesn't know about. We use 409 * this to filter out devices. 410 */ 411 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 412 continue; 413 if ((hdrtype & PCIM_MFDEV) && 414 (!found_orion || hdrtype != 0xff)) 415 pcifunchigh = PCI_FUNCMAX; 416 else 417 pcifunchigh = 0; 418 for (func = 0; func <= pcifunchigh; func++) { 419 /* 420 * Read the IDs and class from the device. 421 */ 422 uint32_t id; 423 uint8_t class, subclass, busnum; 424 const char *s; 425 device_t *devs; 426 int ndevs, i; 427 428 id = legacy_pcib_read_config(0, bus, slot, func, 429 PCIR_DEVVENDOR, 4); 430 if (id == -1) 431 continue; 432 class = legacy_pcib_read_config(0, bus, slot, func, 433 PCIR_CLASS, 1); 434 subclass = legacy_pcib_read_config(0, bus, slot, func, 435 PCIR_SUBCLASS, 1); 436 437 s = legacy_pcib_is_host_bridge(bus, slot, func, 438 id, class, subclass, 439 &busnum); 440 if (s == NULL) 441 continue; 442 443 /* 444 * Check to see if the physical bus has already 445 * been seen. Eg: hybrid 32 and 64 bit host 446 * bridges to the same logical bus. 447 */ 448 if (device_get_children(parent, &devs, &ndevs) == 0) { 449 for (i = 0; s != NULL && i < ndevs; i++) { 450 if (strcmp(device_get_name(devs[i]), 451 "pcib") != 0) 452 continue; 453 if (legacy_get_pcibus(devs[i]) == busnum) 454 s = NULL; 455 } 456 free(devs, M_TEMP); 457 } 458 459 if (s == NULL) 460 continue; 461 /* 462 * Add at priority 100 to make sure we 463 * go after any motherboard resources 464 */ 465 child = BUS_ADD_CHILD(parent, 100, 466 "pcib", busnum); 467 device_set_desc(child, s); 468 legacy_set_pcibus(child, busnum); 469 legacy_set_pcislot(child, slot); 470 legacy_set_pcifunc(child, func); 471 472 found = 1; 473 if (id == 0x12258086) 474 found824xx = 1; 475 if (id == 0x84c48086) 476 found_orion = 1; 477 } 478 } 479 if (found824xx && bus == 0) { 480 bus++; 481 goto retry; 482 } 483 484 /* 485 * Make sure we add at least one bridge since some old 486 * hardware doesn't actually have a host-pci bridge device. 487 * Note that pci_cfgregopen() thinks we have PCI devices.. 488 */ 489 if (!found) { 490 if (bootverbose) 491 printf( 492 "legacy_pcib_identify: no bridge found, adding pcib0 anyway\n"); 493 child = BUS_ADD_CHILD(parent, 100, "pcib", 0); 494 legacy_set_pcibus(child, 0); 495 } 496 } 497 498 static int 499 legacy_pcib_probe(device_t dev) 500 { 501 502 if (pci_cfgregopen() == 0) 503 return ENXIO; 504 return -100; 505 } 506 507 static int 508 legacy_pcib_attach(device_t dev) 509 { 510 #ifdef __HAVE_PIR 511 device_t pir; 512 #endif 513 int bus; 514 515 bus = pcib_get_bus(dev); 516 #ifdef __HAVE_PIR 517 /* 518 * Look for a PCI BIOS interrupt routing table as that will be 519 * our method of routing interrupts if we have one. 520 */ 521 if (pci_pir_probe(bus, 0)) { 522 pir = BUS_ADD_CHILD(device_get_parent(dev), 0, "pir", 0); 523 if (pir != NULL) 524 device_probe_and_attach(pir); 525 } 526 #endif 527 device_add_child(dev, "pci", bus); 528 return bus_generic_attach(dev); 529 } 530 531 int 532 legacy_pcib_read_ivar(device_t dev, device_t child, int which, 533 uintptr_t *result) 534 { 535 536 switch (which) { 537 case PCIB_IVAR_DOMAIN: 538 *result = 0; 539 return 0; 540 case PCIB_IVAR_BUS: 541 *result = legacy_get_pcibus(dev); 542 return 0; 543 } 544 return ENOENT; 545 } 546 547 int 548 legacy_pcib_write_ivar(device_t dev, device_t child, int which, 549 uintptr_t value) 550 { 551 552 switch (which) { 553 case PCIB_IVAR_DOMAIN: 554 return EINVAL; 555 case PCIB_IVAR_BUS: 556 legacy_set_pcibus(dev, value); 557 return 0; 558 } 559 return ENOENT; 560 } 561 562 /* 563 * Helper routine for x86 Host-PCI bridge driver resource allocation. 564 * This is used to adjust the start address of wildcard allocation 565 * requests to avoid low addresses that are known to be problematic. 566 * 567 * If no memory preference is given, use upper 32MB slot most BIOSes 568 * use for their memory window. This is typically only used on older 569 * laptops that don't have PCI busses behind a PCI bridge, so assuming 570 * > 32MB is likely OK. 571 * 572 * However, this can cause problems for other chipsets, so we make 573 * this tunable by hw.pci.host_mem_start. 574 */ 575 SYSCTL_DECL(_hw_pci); 576 577 static unsigned long host_mem_start = 0x80000000; 578 TUNABLE_ULONG("hw.pci.host_mem_start", &host_mem_start); 579 SYSCTL_ULONG(_hw_pci, OID_AUTO, host_mem_start, CTLFLAG_RDTUN, &host_mem_start, 580 0, "Limit the host bridge memory to being above this address."); 581 582 u_long 583 hostb_alloc_start(int type, u_long start, u_long end, u_long count) 584 { 585 586 if (start + count - 1 != end) { 587 if (type == SYS_RES_MEMORY && start < host_mem_start) 588 start = host_mem_start; 589 if (type == SYS_RES_IOPORT && start < 0x1000) 590 start = 0x1000; 591 } 592 return (start); 593 } 594 595 struct resource * 596 legacy_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 597 u_long start, u_long end, u_long count, u_int flags) 598 { 599 600 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 601 if (type == PCI_RES_BUS) 602 return (pci_domain_alloc_bus(0, child, rid, start, end, count, 603 flags)); 604 #endif 605 start = hostb_alloc_start(type, start, end, count); 606 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, 607 count, flags)); 608 } 609 610 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 611 int 612 legacy_pcib_adjust_resource(device_t dev, device_t child, int type, 613 struct resource *r, u_long start, u_long end) 614 { 615 616 if (type == PCI_RES_BUS) 617 return (pci_domain_adjust_bus(0, child, r, start, end)); 618 return (bus_generic_adjust_resource(dev, child, type, r, start, end)); 619 } 620 621 int 622 legacy_pcib_release_resource(device_t dev, device_t child, int type, int rid, 623 struct resource *r) 624 { 625 626 if (type == PCI_RES_BUS) 627 return (pci_domain_release_bus(0, child, rid, r)); 628 return (bus_generic_release_resource(dev, child, type, rid, r)); 629 } 630 #endif 631 632 static device_method_t legacy_pcib_methods[] = { 633 /* Device interface */ 634 DEVMETHOD(device_identify, legacy_pcib_identify), 635 DEVMETHOD(device_probe, legacy_pcib_probe), 636 DEVMETHOD(device_attach, legacy_pcib_attach), 637 DEVMETHOD(device_shutdown, bus_generic_shutdown), 638 DEVMETHOD(device_suspend, bus_generic_suspend), 639 DEVMETHOD(device_resume, bus_generic_resume), 640 641 /* Bus interface */ 642 DEVMETHOD(bus_read_ivar, legacy_pcib_read_ivar), 643 DEVMETHOD(bus_write_ivar, legacy_pcib_write_ivar), 644 DEVMETHOD(bus_alloc_resource, legacy_pcib_alloc_resource), 645 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 646 DEVMETHOD(bus_adjust_resource, legacy_pcib_adjust_resource), 647 DEVMETHOD(bus_release_resource, legacy_pcib_release_resource), 648 #else 649 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 650 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 651 #endif 652 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 653 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 654 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 655 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 656 657 /* pcib interface */ 658 DEVMETHOD(pcib_maxslots, legacy_pcib_maxslots), 659 DEVMETHOD(pcib_read_config, legacy_pcib_read_config), 660 DEVMETHOD(pcib_write_config, legacy_pcib_write_config), 661 DEVMETHOD(pcib_route_interrupt, legacy_pcib_route_interrupt), 662 DEVMETHOD(pcib_alloc_msi, legacy_pcib_alloc_msi), 663 DEVMETHOD(pcib_release_msi, pcib_release_msi), 664 DEVMETHOD(pcib_alloc_msix, legacy_pcib_alloc_msix), 665 DEVMETHOD(pcib_release_msix, pcib_release_msix), 666 DEVMETHOD(pcib_map_msi, legacy_pcib_map_msi), 667 668 DEVMETHOD_END 669 }; 670 671 static devclass_t hostb_devclass; 672 673 DEFINE_CLASS_0(pcib, legacy_pcib_driver, legacy_pcib_methods, 1); 674 DRIVER_MODULE(pcib, legacy, legacy_pcib_driver, hostb_devclass, 0, 0); 675 676 677 /* 678 * Install placeholder to claim the resources owned by the 679 * PCI bus interface. This could be used to extract the 680 * config space registers in the extreme case where the PnP 681 * ID is available and the PCI BIOS isn't, but for now we just 682 * eat the PnP ID and do nothing else. 683 * 684 * XXX we should silence this probe, as it will generally confuse 685 * people. 686 */ 687 static struct isa_pnp_id pcibus_pnp_ids[] = { 688 { 0x030ad041 /* PNP0A03 */, "PCI Bus" }, 689 { 0x080ad041 /* PNP0A08 */, "PCIe Bus" }, 690 { 0 } 691 }; 692 693 static int 694 pcibus_pnp_probe(device_t dev) 695 { 696 int result; 697 698 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, pcibus_pnp_ids)) <= 0) 699 device_quiet(dev); 700 return(result); 701 } 702 703 static int 704 pcibus_pnp_attach(device_t dev) 705 { 706 return(0); 707 } 708 709 static device_method_t pcibus_pnp_methods[] = { 710 /* Device interface */ 711 DEVMETHOD(device_probe, pcibus_pnp_probe), 712 DEVMETHOD(device_attach, pcibus_pnp_attach), 713 DEVMETHOD(device_detach, bus_generic_detach), 714 DEVMETHOD(device_shutdown, bus_generic_shutdown), 715 DEVMETHOD(device_suspend, bus_generic_suspend), 716 DEVMETHOD(device_resume, bus_generic_resume), 717 { 0, 0 } 718 }; 719 720 static devclass_t pcibus_pnp_devclass; 721 722 DEFINE_CLASS_0(pcibus_pnp, pcibus_pnp_driver, pcibus_pnp_methods, 1); 723 DRIVER_MODULE(pcibus_pnp, isa, pcibus_pnp_driver, pcibus_pnp_devclass, 0, 0); 724 725 #ifdef __HAVE_PIR 726 /* 727 * Provide a PCI-PCI bridge driver for PCI busses behind PCI-PCI bridges 728 * that appear in the PCIBIOS Interrupt Routing Table to use the routing 729 * table for interrupt routing when possible. 730 */ 731 static int pcibios_pcib_probe(device_t bus); 732 733 static device_method_t pcibios_pcib_pci_methods[] = { 734 /* Device interface */ 735 DEVMETHOD(device_probe, pcibios_pcib_probe), 736 737 /* pcib interface */ 738 DEVMETHOD(pcib_route_interrupt, legacy_pcib_route_interrupt), 739 740 {0, 0} 741 }; 742 743 static devclass_t pcib_devclass; 744 745 DEFINE_CLASS_1(pcib, pcibios_pcib_driver, pcibios_pcib_pci_methods, 746 sizeof(struct pcib_softc), pcib_driver); 747 DRIVER_MODULE(pcibios_pcib, pci, pcibios_pcib_driver, pcib_devclass, 0, 0); 748 749 static int 750 pcibios_pcib_probe(device_t dev) 751 { 752 int bus; 753 754 if ((pci_get_class(dev) != PCIC_BRIDGE) || 755 (pci_get_subclass(dev) != PCIS_BRIDGE_PCI)) 756 return (ENXIO); 757 bus = pci_read_config(dev, PCIR_SECBUS_1, 1); 758 if (bus == 0) 759 return (ENXIO); 760 if (!pci_pir_probe(bus, 1)) 761 return (ENXIO); 762 device_set_desc(dev, "PCIBIOS PCI-PCI bridge"); 763 return (-2000); 764 } 765 #endif
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