FreeBSD/Linux Kernel Cross Reference
sys/x86/pci/pci_bus.c
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD: releng/12.0/sys/x86/pci/pci_bus.c 328524 2018-01-29 00:22:30Z imp $");
31
32 #include "opt_cpu.h"
33
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/bus.h>
37 #include <sys/kernel.h>
38 #include <sys/malloc.h>
39 #include <sys/module.h>
40 #include <sys/rman.h>
41 #include <sys/sysctl.h>
42
43 #include <dev/pci/pcivar.h>
44 #include <dev/pci/pcireg.h>
45 #include <dev/pci/pcib_private.h>
46 #include <isa/isavar.h>
47 #ifdef CPU_ELAN
48 #include <machine/md_var.h>
49 #endif
50 #include <x86/legacyvar.h>
51 #include <machine/pci_cfgreg.h>
52 #include <machine/resource.h>
53
54 #include "pcib_if.h"
55
56 int
57 legacy_pcib_maxslots(device_t dev)
58 {
59 return 31;
60 }
61
62 /* read configuration space register */
63
64 uint32_t
65 legacy_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
66 u_int reg, int bytes)
67 {
68 return(pci_cfgregread(bus, slot, func, reg, bytes));
69 }
70
71 /* write configuration space register */
72
73 void
74 legacy_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
75 u_int reg, uint32_t data, int bytes)
76 {
77 pci_cfgregwrite(bus, slot, func, reg, data, bytes);
78 }
79
80 /* route interrupt */
81
82 static int
83 legacy_pcib_route_interrupt(device_t pcib, device_t dev, int pin)
84 {
85
86 #ifdef __HAVE_PIR
87 return (pci_pir_route_interrupt(pci_get_bus(dev), pci_get_slot(dev),
88 pci_get_function(dev), pin));
89 #else
90 /* No routing possible */
91 return (PCI_INVALID_IRQ);
92 #endif
93 }
94
95 /* Pass MSI requests up to the nexus. */
96
97 int
98 legacy_pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount,
99 int *irqs)
100 {
101 device_t bus;
102
103 bus = device_get_parent(pcib);
104 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
105 irqs));
106 }
107
108 int
109 legacy_pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
110 {
111 device_t bus;
112
113 bus = device_get_parent(pcib);
114 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq));
115 }
116
117 int
118 legacy_pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
119 uint32_t *data)
120 {
121 device_t bus, hostb;
122 int error, func, slot;
123
124 bus = device_get_parent(pcib);
125 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data);
126 if (error)
127 return (error);
128
129 slot = legacy_get_pcislot(pcib);
130 func = legacy_get_pcifunc(pcib);
131 if (slot == -1 || func == -1)
132 return (0);
133 hostb = pci_find_bsf(0, slot, func);
134 KASSERT(hostb != NULL, ("%s: missing hostb for 0:%d:%d", __func__,
135 slot, func));
136 pci_ht_map_msi(hostb, *addr);
137 return (0);
138 }
139
140 static const char *
141 legacy_pcib_is_host_bridge(int bus, int slot, int func,
142 uint32_t id, uint8_t class, uint8_t subclass,
143 uint8_t *busnum)
144 {
145 #ifdef __i386__
146 const char *s = NULL;
147 static uint8_t pxb[4]; /* hack for 450nx */
148
149 *busnum = 0;
150
151 switch (id) {
152 case 0x12258086:
153 s = "Intel 824?? host to PCI bridge";
154 /* XXX This is a guess */
155 /* *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x41, 1); */
156 *busnum = bus;
157 break;
158 case 0x71208086:
159 s = "Intel 82810 (i810 GMCH) Host To Hub bridge";
160 break;
161 case 0x71228086:
162 s = "Intel 82810-DC100 (i810-DC100 GMCH) Host To Hub bridge";
163 break;
164 case 0x71248086:
165 s = "Intel 82810E (i810E GMCH) Host To Hub bridge";
166 break;
167 case 0x11308086:
168 s = "Intel 82815 (i815 GMCH) Host To Hub bridge";
169 break;
170 case 0x71808086:
171 s = "Intel 82443LX (440 LX) host to PCI bridge";
172 break;
173 case 0x71908086:
174 s = "Intel 82443BX (440 BX) host to PCI bridge";
175 break;
176 case 0x71928086:
177 s = "Intel 82443BX host to PCI bridge (AGP disabled)";
178 break;
179 case 0x71948086:
180 s = "Intel 82443MX host to PCI bridge";
181 break;
182 case 0x71a08086:
183 s = "Intel 82443GX host to PCI bridge";
184 break;
185 case 0x71a18086:
186 s = "Intel 82443GX host to AGP bridge";
187 break;
188 case 0x71a28086:
189 s = "Intel 82443GX host to PCI bridge (AGP disabled)";
190 break;
191 case 0x84c48086:
192 s = "Intel 82454KX/GX (Orion) host to PCI bridge";
193 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x4a, 1);
194 break;
195 case 0x84ca8086:
196 /*
197 * For the 450nx chipset, there is a whole bundle of
198 * things pretending to be host bridges. The MIOC will
199 * be seen first and isn't really a pci bridge (the
200 * actual buses are attached to the PXB's). We need to
201 * read the registers of the MIOC to figure out the
202 * bus numbers for the PXB channels.
203 *
204 * Since the MIOC doesn't have a pci bus attached, we
205 * pretend it wasn't there.
206 */
207 pxb[0] = legacy_pcib_read_config(0, bus, slot, func,
208 0xd0, 1); /* BUSNO[0] */
209 pxb[1] = legacy_pcib_read_config(0, bus, slot, func,
210 0xd1, 1) + 1; /* SUBA[0]+1 */
211 pxb[2] = legacy_pcib_read_config(0, bus, slot, func,
212 0xd3, 1); /* BUSNO[1] */
213 pxb[3] = legacy_pcib_read_config(0, bus, slot, func,
214 0xd4, 1) + 1; /* SUBA[1]+1 */
215 return NULL;
216 case 0x84cb8086:
217 switch (slot) {
218 case 0x12:
219 s = "Intel 82454NX PXB#0, Bus#A";
220 *busnum = pxb[0];
221 break;
222 case 0x13:
223 s = "Intel 82454NX PXB#0, Bus#B";
224 *busnum = pxb[1];
225 break;
226 case 0x14:
227 s = "Intel 82454NX PXB#1, Bus#A";
228 *busnum = pxb[2];
229 break;
230 case 0x15:
231 s = "Intel 82454NX PXB#1, Bus#B";
232 *busnum = pxb[3];
233 break;
234 }
235 break;
236 case 0x1A308086:
237 s = "Intel 82845 Host to PCI bridge";
238 break;
239
240 /* AMD -- vendor 0x1022 */
241 case 0x30001022:
242 s = "AMD Elan SC520 host to PCI bridge";
243 #ifdef CPU_ELAN
244 init_AMD_Elan_sc520();
245 #else
246 printf(
247 "*** WARNING: missing CPU_ELAN -- timekeeping may be wrong\n");
248 #endif
249 break;
250 case 0x70061022:
251 s = "AMD-751 host to PCI bridge";
252 break;
253 case 0x700e1022:
254 s = "AMD-761 host to PCI bridge";
255 break;
256
257 /* SiS -- vendor 0x1039 */
258 case 0x04961039:
259 s = "SiS 85c496";
260 break;
261 case 0x04061039:
262 s = "SiS 85c501";
263 break;
264 case 0x06011039:
265 s = "SiS 85c601";
266 break;
267 case 0x55911039:
268 s = "SiS 5591 host to PCI bridge";
269 break;
270 case 0x00011039:
271 s = "SiS 5591 host to AGP bridge";
272 break;
273
274 /* VLSI -- vendor 0x1004 */
275 case 0x00051004:
276 s = "VLSI 82C592 Host to PCI bridge";
277 break;
278
279 /* XXX Here is MVP3, I got the datasheet but NO M/B to test it */
280 /* totally. Please let me know if anything wrong. -F */
281 /* XXX need info on the MVP3 -- any takers? */
282 case 0x05981106:
283 s = "VIA 82C598MVP (Apollo MVP3) host bridge";
284 break;
285
286 /* AcerLabs -- vendor 0x10b9 */
287 /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
288 /* id is '10b9" but the register always shows "10b9". -Foxfair */
289 case 0x154110b9:
290 s = "AcerLabs M1541 (Aladdin-V) PCI host bridge";
291 break;
292
293 /* OPTi -- vendor 0x1045 */
294 case 0xc7011045:
295 s = "OPTi 82C700 host to PCI bridge";
296 break;
297 case 0xc8221045:
298 s = "OPTi 82C822 host to PCI Bridge";
299 break;
300
301 /* ServerWorks -- vendor 0x1166 */
302 case 0x00051166:
303 s = "ServerWorks NB6536 2.0HE host to PCI bridge";
304 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
305 break;
306
307 case 0x00061166:
308 /* FALLTHROUGH */
309 case 0x00081166:
310 /* FALLTHROUGH */
311 case 0x02011166:
312 /* FALLTHROUGH */
313 case 0x010f1014: /* IBM re-badged ServerWorks chipset */
314 s = "ServerWorks host to PCI bridge";
315 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
316 break;
317
318 case 0x00091166:
319 s = "ServerWorks NB6635 3.0LE host to PCI bridge";
320 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
321 break;
322
323 case 0x00101166:
324 s = "ServerWorks CIOB30 host to PCI bridge";
325 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
326 break;
327
328 case 0x00111166:
329 /* FALLTHROUGH */
330 case 0x03021014: /* IBM re-badged ServerWorks chipset */
331 s = "ServerWorks CMIC-HE host to PCI-X bridge";
332 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
333 break;
334
335 /* XXX unknown chipset, but working */
336 case 0x00171166:
337 /* FALLTHROUGH */
338 case 0x01011166:
339 case 0x01101166:
340 case 0x02251166:
341 s = "ServerWorks host to PCI bridge(unknown chipset)";
342 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
343 break;
344
345 /* Compaq/HP -- vendor 0x0e11 */
346 case 0x60100e11:
347 s = "Compaq/HP Model 6010 HotPlug PCI Bridge";
348 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0xc8, 1);
349 break;
350
351 /* Integrated Micro Solutions -- vendor 0x10e0 */
352 case 0x884910e0:
353 s = "Integrated Micro Solutions VL Bridge";
354 break;
355
356 default:
357 if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST)
358 s = "Host to PCI bridge";
359 break;
360 }
361
362 return s;
363 #else
364 const char *s = NULL;
365
366 *busnum = 0;
367 if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST)
368 s = "Host to PCI bridge";
369 return s;
370 #endif
371 }
372
373 /*
374 * Scan the first pci bus for host-pci bridges and add pcib instances
375 * to the nexus for each bridge.
376 */
377 static void
378 legacy_pcib_identify(driver_t *driver, device_t parent)
379 {
380 int bus, slot, func;
381 uint8_t hdrtype;
382 int found = 0;
383 int pcifunchigh;
384 int found824xx = 0;
385 int found_orion = 0;
386 device_t child;
387 devclass_t pci_devclass;
388
389 if (pci_cfgregopen() == 0)
390 return;
391 /*
392 * Check to see if we haven't already had a PCI bus added
393 * via some other means. If we have, bail since otherwise
394 * we're going to end up duplicating it.
395 */
396 if ((pci_devclass = devclass_find("pci")) &&
397 devclass_get_device(pci_devclass, 0))
398 return;
399
400
401 bus = 0;
402 retry:
403 for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
404 func = 0;
405 hdrtype = legacy_pcib_read_config(0, bus, slot, func,
406 PCIR_HDRTYPE, 1);
407 /*
408 * When enumerating bus devices, the standard says that
409 * one should check the header type and ignore the slots whose
410 * header types that the software doesn't know about. We use
411 * this to filter out devices.
412 */
413 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
414 continue;
415 if ((hdrtype & PCIM_MFDEV) &&
416 (!found_orion || hdrtype != 0xff))
417 pcifunchigh = PCI_FUNCMAX;
418 else
419 pcifunchigh = 0;
420 for (func = 0; func <= pcifunchigh; func++) {
421 /*
422 * Read the IDs and class from the device.
423 */
424 uint32_t id;
425 uint8_t class, subclass, busnum;
426 const char *s;
427 device_t *devs;
428 int ndevs, i;
429
430 id = legacy_pcib_read_config(0, bus, slot, func,
431 PCIR_DEVVENDOR, 4);
432 if (id == -1)
433 continue;
434 class = legacy_pcib_read_config(0, bus, slot, func,
435 PCIR_CLASS, 1);
436 subclass = legacy_pcib_read_config(0, bus, slot, func,
437 PCIR_SUBCLASS, 1);
438
439 s = legacy_pcib_is_host_bridge(bus, slot, func,
440 id, class, subclass,
441 &busnum);
442 if (s == NULL)
443 continue;
444
445 /*
446 * Check to see if the physical bus has already
447 * been seen. Eg: hybrid 32 and 64 bit host
448 * bridges to the same logical bus.
449 */
450 if (device_get_children(parent, &devs, &ndevs) == 0) {
451 for (i = 0; s != NULL && i < ndevs; i++) {
452 if (strcmp(device_get_name(devs[i]),
453 "pcib") != 0)
454 continue;
455 if (legacy_get_pcibus(devs[i]) == busnum)
456 s = NULL;
457 }
458 free(devs, M_TEMP);
459 }
460
461 if (s == NULL)
462 continue;
463 /*
464 * Add at priority 100 to make sure we
465 * go after any motherboard resources
466 */
467 child = BUS_ADD_CHILD(parent, 100,
468 "pcib", busnum);
469 device_set_desc(child, s);
470 legacy_set_pcibus(child, busnum);
471 legacy_set_pcislot(child, slot);
472 legacy_set_pcifunc(child, func);
473
474 found = 1;
475 if (id == 0x12258086)
476 found824xx = 1;
477 if (id == 0x84c48086)
478 found_orion = 1;
479 }
480 }
481 if (found824xx && bus == 0) {
482 bus++;
483 goto retry;
484 }
485
486 /*
487 * Make sure we add at least one bridge since some old
488 * hardware doesn't actually have a host-pci bridge device.
489 * Note that pci_cfgregopen() thinks we have PCI devices..
490 */
491 if (!found) {
492 if (bootverbose)
493 printf(
494 "legacy_pcib_identify: no bridge found, adding pcib0 anyway\n");
495 child = BUS_ADD_CHILD(parent, 100, "pcib", 0);
496 legacy_set_pcibus(child, 0);
497 }
498 }
499
500 static int
501 legacy_pcib_probe(device_t dev)
502 {
503
504 if (pci_cfgregopen() == 0)
505 return ENXIO;
506 return -100;
507 }
508
509 static int
510 legacy_pcib_attach(device_t dev)
511 {
512 #ifdef __HAVE_PIR
513 device_t pir;
514 #endif
515 int bus;
516
517 bus = pcib_get_bus(dev);
518 #ifdef __HAVE_PIR
519 /*
520 * Look for a PCI BIOS interrupt routing table as that will be
521 * our method of routing interrupts if we have one.
522 */
523 if (pci_pir_probe(bus, 0)) {
524 pir = BUS_ADD_CHILD(device_get_parent(dev), 0, "pir", 0);
525 if (pir != NULL)
526 device_probe_and_attach(pir);
527 }
528 #endif
529 device_add_child(dev, "pci", -1);
530 return bus_generic_attach(dev);
531 }
532
533 int
534 legacy_pcib_read_ivar(device_t dev, device_t child, int which,
535 uintptr_t *result)
536 {
537
538 switch (which) {
539 case PCIB_IVAR_DOMAIN:
540 *result = 0;
541 return 0;
542 case PCIB_IVAR_BUS:
543 *result = legacy_get_pcibus(dev);
544 return 0;
545 }
546 return ENOENT;
547 }
548
549 int
550 legacy_pcib_write_ivar(device_t dev, device_t child, int which,
551 uintptr_t value)
552 {
553
554 switch (which) {
555 case PCIB_IVAR_DOMAIN:
556 return EINVAL;
557 case PCIB_IVAR_BUS:
558 legacy_set_pcibus(dev, value);
559 return 0;
560 }
561 return ENOENT;
562 }
563
564 /*
565 * Helper routine for x86 Host-PCI bridge driver resource allocation.
566 * This is used to adjust the start address of wildcard allocation
567 * requests to avoid low addresses that are known to be problematic.
568 *
569 * If no memory preference is given, use upper 32MB slot most BIOSes
570 * use for their memory window. This is typically only used on older
571 * laptops that don't have PCI buses behind a PCI bridge, so assuming
572 * > 32MB is likely OK.
573 *
574 * However, this can cause problems for other chipsets, so we make
575 * this tunable by hw.pci.host_mem_start.
576 */
577 SYSCTL_DECL(_hw_pci);
578
579 static unsigned long host_mem_start = 0x80000000;
580 SYSCTL_ULONG(_hw_pci, OID_AUTO, host_mem_start, CTLFLAG_RDTUN, &host_mem_start,
581 0, "Limit the host bridge memory to being above this address.");
582
583 rman_res_t
584 hostb_alloc_start(int type, rman_res_t start, rman_res_t end, rman_res_t count)
585 {
586
587 if (start + count - 1 != end) {
588 if (type == SYS_RES_MEMORY && start < host_mem_start)
589 start = host_mem_start;
590 if (type == SYS_RES_IOPORT && start < 0x1000)
591 start = 0x1000;
592 }
593 return (start);
594 }
595
596 struct resource *
597 legacy_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
598 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
599 {
600
601 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
602 if (type == PCI_RES_BUS)
603 return (pci_domain_alloc_bus(0, child, rid, start, end, count,
604 flags));
605 #endif
606 start = hostb_alloc_start(type, start, end, count);
607 return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
608 count, flags));
609 }
610
611 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
612 int
613 legacy_pcib_adjust_resource(device_t dev, device_t child, int type,
614 struct resource *r, rman_res_t start, rman_res_t end)
615 {
616
617 if (type == PCI_RES_BUS)
618 return (pci_domain_adjust_bus(0, child, r, start, end));
619 return (bus_generic_adjust_resource(dev, child, type, r, start, end));
620 }
621
622 int
623 legacy_pcib_release_resource(device_t dev, device_t child, int type, int rid,
624 struct resource *r)
625 {
626
627 if (type == PCI_RES_BUS)
628 return (pci_domain_release_bus(0, child, rid, r));
629 return (bus_generic_release_resource(dev, child, type, rid, r));
630 }
631 #endif
632
633 static device_method_t legacy_pcib_methods[] = {
634 /* Device interface */
635 DEVMETHOD(device_identify, legacy_pcib_identify),
636 DEVMETHOD(device_probe, legacy_pcib_probe),
637 DEVMETHOD(device_attach, legacy_pcib_attach),
638 DEVMETHOD(device_shutdown, bus_generic_shutdown),
639 DEVMETHOD(device_suspend, bus_generic_suspend),
640 DEVMETHOD(device_resume, bus_generic_resume),
641
642 /* Bus interface */
643 DEVMETHOD(bus_read_ivar, legacy_pcib_read_ivar),
644 DEVMETHOD(bus_write_ivar, legacy_pcib_write_ivar),
645 DEVMETHOD(bus_alloc_resource, legacy_pcib_alloc_resource),
646 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
647 DEVMETHOD(bus_adjust_resource, legacy_pcib_adjust_resource),
648 DEVMETHOD(bus_release_resource, legacy_pcib_release_resource),
649 #else
650 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
651 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
652 #endif
653 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
654 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
655 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
656 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
657
658 /* pcib interface */
659 DEVMETHOD(pcib_maxslots, legacy_pcib_maxslots),
660 DEVMETHOD(pcib_read_config, legacy_pcib_read_config),
661 DEVMETHOD(pcib_write_config, legacy_pcib_write_config),
662 DEVMETHOD(pcib_route_interrupt, legacy_pcib_route_interrupt),
663 DEVMETHOD(pcib_alloc_msi, legacy_pcib_alloc_msi),
664 DEVMETHOD(pcib_release_msi, pcib_release_msi),
665 DEVMETHOD(pcib_alloc_msix, legacy_pcib_alloc_msix),
666 DEVMETHOD(pcib_release_msix, pcib_release_msix),
667 DEVMETHOD(pcib_map_msi, legacy_pcib_map_msi),
668 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
669
670 DEVMETHOD_END
671 };
672
673 static devclass_t hostb_devclass;
674
675 DEFINE_CLASS_0(pcib, legacy_pcib_driver, legacy_pcib_methods, 1);
676 DRIVER_MODULE(pcib, legacy, legacy_pcib_driver, hostb_devclass, 0, 0);
677
678
679 /*
680 * Install placeholder to claim the resources owned by the
681 * PCI bus interface. This could be used to extract the
682 * config space registers in the extreme case where the PnP
683 * ID is available and the PCI BIOS isn't, but for now we just
684 * eat the PnP ID and do nothing else.
685 *
686 * we silence this probe, as it will generally confuse people.
687 */
688 static struct isa_pnp_id pcibus_pnp_ids[] = {
689 { 0x030ad041 /* PNP0A03 */, "PCI Bus" },
690 { 0x080ad041 /* PNP0A08 */, "PCIe Bus" },
691 { 0 }
692 };
693
694 static int
695 pcibus_pnp_probe(device_t dev)
696 {
697 int result;
698
699 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, pcibus_pnp_ids)) <= 0)
700 device_quiet(dev);
701 return(result);
702 }
703
704 static int
705 pcibus_pnp_attach(device_t dev)
706 {
707 return(0);
708 }
709
710 static device_method_t pcibus_pnp_methods[] = {
711 /* Device interface */
712 DEVMETHOD(device_probe, pcibus_pnp_probe),
713 DEVMETHOD(device_attach, pcibus_pnp_attach),
714 DEVMETHOD(device_detach, bus_generic_detach),
715 DEVMETHOD(device_shutdown, bus_generic_shutdown),
716 DEVMETHOD(device_suspend, bus_generic_suspend),
717 DEVMETHOD(device_resume, bus_generic_resume),
718 { 0, 0 }
719 };
720
721 static devclass_t pcibus_pnp_devclass;
722
723 DEFINE_CLASS_0(pcibus_pnp, pcibus_pnp_driver, pcibus_pnp_methods, 1);
724 DRIVER_MODULE(pcibus_pnp, isa, pcibus_pnp_driver, pcibus_pnp_devclass, 0, 0);
725
726 #ifdef __HAVE_PIR
727 /*
728 * Provide a PCI-PCI bridge driver for PCI buses behind PCI-PCI bridges
729 * that appear in the PCIBIOS Interrupt Routing Table to use the routing
730 * table for interrupt routing when possible.
731 */
732 static int pcibios_pcib_probe(device_t bus);
733
734 static device_method_t pcibios_pcib_pci_methods[] = {
735 /* Device interface */
736 DEVMETHOD(device_probe, pcibios_pcib_probe),
737
738 /* pcib interface */
739 DEVMETHOD(pcib_route_interrupt, legacy_pcib_route_interrupt),
740
741 {0, 0}
742 };
743
744 static devclass_t pcib_devclass;
745
746 DEFINE_CLASS_1(pcib, pcibios_pcib_driver, pcibios_pcib_pci_methods,
747 sizeof(struct pcib_softc), pcib_driver);
748 DRIVER_MODULE(pcibios_pcib, pci, pcibios_pcib_driver, pcib_devclass, 0, 0);
749 ISA_PNP_INFO(pcibus_pnp_ids);
750
751 static int
752 pcibios_pcib_probe(device_t dev)
753 {
754 int bus;
755
756 if ((pci_get_class(dev) != PCIC_BRIDGE) ||
757 (pci_get_subclass(dev) != PCIS_BRIDGE_PCI))
758 return (ENXIO);
759 bus = pci_read_config(dev, PCIR_SECBUS_1, 1);
760 if (bus == 0)
761 return (ENXIO);
762 if (!pci_pir_probe(bus, 1))
763 return (ENXIO);
764 device_set_desc(dev, "PCIBIOS PCI-PCI bridge");
765 return (-2000);
766 }
767 #endif
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