Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/x86/pci/pci_bus.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD: releng/9.1/sys/x86/pci/pci_bus.c 234150 2012-04-11 20:50:17Z jhb $"); 29 30 #include "opt_cpu.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/kernel.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/rman.h> 39 #include <sys/sysctl.h> 40 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcib_private.h> 44 #include <isa/isavar.h> 45 #ifdef CPU_ELAN 46 #include <machine/md_var.h> 47 #endif 48 #include <machine/legacyvar.h> 49 #include <machine/pci_cfgreg.h> 50 #include <machine/resource.h> 51 52 #include "pcib_if.h" 53 54 int 55 legacy_pcib_maxslots(device_t dev) 56 { 57 return 31; 58 } 59 60 /* read configuration space register */ 61 62 uint32_t 63 legacy_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 64 u_int reg, int bytes) 65 { 66 return(pci_cfgregread(bus, slot, func, reg, bytes)); 67 } 68 69 /* write configuration space register */ 70 71 void 72 legacy_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 73 u_int reg, uint32_t data, int bytes) 74 { 75 pci_cfgregwrite(bus, slot, func, reg, data, bytes); 76 } 77 78 /* route interrupt */ 79 80 static int 81 legacy_pcib_route_interrupt(device_t pcib, device_t dev, int pin) 82 { 83 84 #ifdef __HAVE_PIR 85 return (pci_pir_route_interrupt(pci_get_bus(dev), pci_get_slot(dev), 86 pci_get_function(dev), pin)); 87 #else 88 /* No routing possible */ 89 return (PCI_INVALID_IRQ); 90 #endif 91 } 92 93 /* Pass MSI requests up to the nexus. */ 94 95 static int 96 legacy_pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, 97 int *irqs) 98 { 99 device_t bus; 100 101 bus = device_get_parent(pcib); 102 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount, 103 irqs)); 104 } 105 106 static int 107 legacy_pcib_alloc_msix(device_t pcib, device_t dev, int *irq) 108 { 109 device_t bus; 110 111 bus = device_get_parent(pcib); 112 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq)); 113 } 114 115 int 116 legacy_pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 117 uint32_t *data) 118 { 119 device_t bus, hostb; 120 int error, func, slot; 121 122 bus = device_get_parent(pcib); 123 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data); 124 if (error) 125 return (error); 126 127 slot = legacy_get_pcislot(pcib); 128 func = legacy_get_pcifunc(pcib); 129 if (slot == -1 || func == -1) 130 return (0); 131 hostb = pci_find_bsf(0, slot, func); 132 KASSERT(hostb != NULL, ("%s: missing hostb for 0:%d:%d", __func__, 133 slot, func)); 134 pci_ht_map_msi(hostb, *addr); 135 return (0); 136 137 } 138 139 static const char * 140 legacy_pcib_is_host_bridge(int bus, int slot, int func, 141 uint32_t id, uint8_t class, uint8_t subclass, 142 uint8_t *busnum) 143 { 144 #ifdef __i386__ 145 const char *s = NULL; 146 static uint8_t pxb[4]; /* hack for 450nx */ 147 148 *busnum = 0; 149 150 switch (id) { 151 case 0x12258086: 152 s = "Intel 824?? host to PCI bridge"; 153 /* XXX This is a guess */ 154 /* *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x41, 1); */ 155 *busnum = bus; 156 break; 157 case 0x71208086: 158 s = "Intel 82810 (i810 GMCH) Host To Hub bridge"; 159 break; 160 case 0x71228086: 161 s = "Intel 82810-DC100 (i810-DC100 GMCH) Host To Hub bridge"; 162 break; 163 case 0x71248086: 164 s = "Intel 82810E (i810E GMCH) Host To Hub bridge"; 165 break; 166 case 0x11308086: 167 s = "Intel 82815 (i815 GMCH) Host To Hub bridge"; 168 break; 169 case 0x71808086: 170 s = "Intel 82443LX (440 LX) host to PCI bridge"; 171 break; 172 case 0x71908086: 173 s = "Intel 82443BX (440 BX) host to PCI bridge"; 174 break; 175 case 0x71928086: 176 s = "Intel 82443BX host to PCI bridge (AGP disabled)"; 177 break; 178 case 0x71948086: 179 s = "Intel 82443MX host to PCI bridge"; 180 break; 181 case 0x71a08086: 182 s = "Intel 82443GX host to PCI bridge"; 183 break; 184 case 0x71a18086: 185 s = "Intel 82443GX host to AGP bridge"; 186 break; 187 case 0x71a28086: 188 s = "Intel 82443GX host to PCI bridge (AGP disabled)"; 189 break; 190 case 0x84c48086: 191 s = "Intel 82454KX/GX (Orion) host to PCI bridge"; 192 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x4a, 1); 193 break; 194 case 0x84ca8086: 195 /* 196 * For the 450nx chipset, there is a whole bundle of 197 * things pretending to be host bridges. The MIOC will 198 * be seen first and isn't really a pci bridge (the 199 * actual busses are attached to the PXB's). We need to 200 * read the registers of the MIOC to figure out the 201 * bus numbers for the PXB channels. 202 * 203 * Since the MIOC doesn't have a pci bus attached, we 204 * pretend it wasn't there. 205 */ 206 pxb[0] = legacy_pcib_read_config(0, bus, slot, func, 207 0xd0, 1); /* BUSNO[0] */ 208 pxb[1] = legacy_pcib_read_config(0, bus, slot, func, 209 0xd1, 1) + 1; /* SUBA[0]+1 */ 210 pxb[2] = legacy_pcib_read_config(0, bus, slot, func, 211 0xd3, 1); /* BUSNO[1] */ 212 pxb[3] = legacy_pcib_read_config(0, bus, slot, func, 213 0xd4, 1) + 1; /* SUBA[1]+1 */ 214 return NULL; 215 case 0x84cb8086: 216 switch (slot) { 217 case 0x12: 218 s = "Intel 82454NX PXB#0, Bus#A"; 219 *busnum = pxb[0]; 220 break; 221 case 0x13: 222 s = "Intel 82454NX PXB#0, Bus#B"; 223 *busnum = pxb[1]; 224 break; 225 case 0x14: 226 s = "Intel 82454NX PXB#1, Bus#A"; 227 *busnum = pxb[2]; 228 break; 229 case 0x15: 230 s = "Intel 82454NX PXB#1, Bus#B"; 231 *busnum = pxb[3]; 232 break; 233 } 234 break; 235 case 0x1A308086: 236 s = "Intel 82845 Host to PCI bridge"; 237 break; 238 239 /* AMD -- vendor 0x1022 */ 240 case 0x30001022: 241 s = "AMD Elan SC520 host to PCI bridge"; 242 #ifdef CPU_ELAN 243 init_AMD_Elan_sc520(); 244 #else 245 printf( 246 "*** WARNING: missing CPU_ELAN -- timekeeping may be wrong\n"); 247 #endif 248 break; 249 case 0x70061022: 250 s = "AMD-751 host to PCI bridge"; 251 break; 252 case 0x700e1022: 253 s = "AMD-761 host to PCI bridge"; 254 break; 255 256 /* SiS -- vendor 0x1039 */ 257 case 0x04961039: 258 s = "SiS 85c496"; 259 break; 260 case 0x04061039: 261 s = "SiS 85c501"; 262 break; 263 case 0x06011039: 264 s = "SiS 85c601"; 265 break; 266 case 0x55911039: 267 s = "SiS 5591 host to PCI bridge"; 268 break; 269 case 0x00011039: 270 s = "SiS 5591 host to AGP bridge"; 271 break; 272 273 /* VLSI -- vendor 0x1004 */ 274 case 0x00051004: 275 s = "VLSI 82C592 Host to PCI bridge"; 276 break; 277 278 /* XXX Here is MVP3, I got the datasheet but NO M/B to test it */ 279 /* totally. Please let me know if anything wrong. -F */ 280 /* XXX need info on the MVP3 -- any takers? */ 281 case 0x05981106: 282 s = "VIA 82C598MVP (Apollo MVP3) host bridge"; 283 break; 284 285 /* AcerLabs -- vendor 0x10b9 */ 286 /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */ 287 /* id is '10b9" but the register always shows "10b9". -Foxfair */ 288 case 0x154110b9: 289 s = "AcerLabs M1541 (Aladdin-V) PCI host bridge"; 290 break; 291 292 /* OPTi -- vendor 0x1045 */ 293 case 0xc7011045: 294 s = "OPTi 82C700 host to PCI bridge"; 295 break; 296 case 0xc8221045: 297 s = "OPTi 82C822 host to PCI Bridge"; 298 break; 299 300 /* ServerWorks -- vendor 0x1166 */ 301 case 0x00051166: 302 s = "ServerWorks NB6536 2.0HE host to PCI bridge"; 303 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); 304 break; 305 306 case 0x00061166: 307 /* FALLTHROUGH */ 308 case 0x00081166: 309 /* FALLTHROUGH */ 310 case 0x02011166: 311 /* FALLTHROUGH */ 312 case 0x010f1014: /* IBM re-badged ServerWorks chipset */ 313 s = "ServerWorks host to PCI bridge"; 314 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); 315 break; 316 317 case 0x00091166: 318 s = "ServerWorks NB6635 3.0LE host to PCI bridge"; 319 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); 320 break; 321 322 case 0x00101166: 323 s = "ServerWorks CIOB30 host to PCI bridge"; 324 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); 325 break; 326 327 case 0x00111166: 328 /* FALLTHROUGH */ 329 case 0x03021014: /* IBM re-badged ServerWorks chipset */ 330 s = "ServerWorks CMIC-HE host to PCI-X bridge"; 331 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); 332 break; 333 334 /* XXX unknown chipset, but working */ 335 case 0x00171166: 336 /* FALLTHROUGH */ 337 case 0x01011166: 338 case 0x01101166: 339 case 0x02251166: 340 s = "ServerWorks host to PCI bridge(unknown chipset)"; 341 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); 342 break; 343 344 /* Compaq/HP -- vendor 0x0e11 */ 345 case 0x60100e11: 346 s = "Compaq/HP Model 6010 HotPlug PCI Bridge"; 347 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0xc8, 1); 348 break; 349 350 /* Integrated Micro Solutions -- vendor 0x10e0 */ 351 case 0x884910e0: 352 s = "Integrated Micro Solutions VL Bridge"; 353 break; 354 355 default: 356 if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST) 357 s = "Host to PCI bridge"; 358 break; 359 } 360 361 return s; 362 #else 363 const char *s = NULL; 364 365 *busnum = 0; 366 if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST) 367 s = "Host to PCI bridge"; 368 return s; 369 #endif 370 } 371 372 /* 373 * Scan the first pci bus for host-pci bridges and add pcib instances 374 * to the nexus for each bridge. 375 */ 376 static void 377 legacy_pcib_identify(driver_t *driver, device_t parent) 378 { 379 int bus, slot, func; 380 uint8_t hdrtype; 381 int found = 0; 382 int pcifunchigh; 383 int found824xx = 0; 384 int found_orion = 0; 385 device_t child; 386 devclass_t pci_devclass; 387 388 if (pci_cfgregopen() == 0) 389 return; 390 /* 391 * Check to see if we haven't already had a PCI bus added 392 * via some other means. If we have, bail since otherwise 393 * we're going to end up duplicating it. 394 */ 395 if ((pci_devclass = devclass_find("pci")) && 396 devclass_get_device(pci_devclass, 0)) 397 return; 398 399 400 bus = 0; 401 retry: 402 for (slot = 0; slot <= PCI_SLOTMAX; slot++) { 403 func = 0; 404 hdrtype = legacy_pcib_read_config(0, bus, slot, func, 405 PCIR_HDRTYPE, 1); 406 /* 407 * When enumerating bus devices, the standard says that 408 * one should check the header type and ignore the slots whose 409 * header types that the software doesn't know about. We use 410 * this to filter out devices. 411 */ 412 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 413 continue; 414 if ((hdrtype & PCIM_MFDEV) && 415 (!found_orion || hdrtype != 0xff)) 416 pcifunchigh = PCI_FUNCMAX; 417 else 418 pcifunchigh = 0; 419 for (func = 0; func <= pcifunchigh; func++) { 420 /* 421 * Read the IDs and class from the device. 422 */ 423 uint32_t id; 424 uint8_t class, subclass, busnum; 425 const char *s; 426 device_t *devs; 427 int ndevs, i; 428 429 id = legacy_pcib_read_config(0, bus, slot, func, 430 PCIR_DEVVENDOR, 4); 431 if (id == -1) 432 continue; 433 class = legacy_pcib_read_config(0, bus, slot, func, 434 PCIR_CLASS, 1); 435 subclass = legacy_pcib_read_config(0, bus, slot, func, 436 PCIR_SUBCLASS, 1); 437 438 s = legacy_pcib_is_host_bridge(bus, slot, func, 439 id, class, subclass, 440 &busnum); 441 if (s == NULL) 442 continue; 443 444 /* 445 * Check to see if the physical bus has already 446 * been seen. Eg: hybrid 32 and 64 bit host 447 * bridges to the same logical bus. 448 */ 449 if (device_get_children(parent, &devs, &ndevs) == 0) { 450 for (i = 0; s != NULL && i < ndevs; i++) { 451 if (strcmp(device_get_name(devs[i]), 452 "pcib") != 0) 453 continue; 454 if (legacy_get_pcibus(devs[i]) == busnum) 455 s = NULL; 456 } 457 free(devs, M_TEMP); 458 } 459 460 if (s == NULL) 461 continue; 462 /* 463 * Add at priority 100 to make sure we 464 * go after any motherboard resources 465 */ 466 child = BUS_ADD_CHILD(parent, 100, 467 "pcib", busnum); 468 device_set_desc(child, s); 469 legacy_set_pcibus(child, busnum); 470 legacy_set_pcislot(child, slot); 471 legacy_set_pcifunc(child, func); 472 473 found = 1; 474 if (id == 0x12258086) 475 found824xx = 1; 476 if (id == 0x84c48086) 477 found_orion = 1; 478 } 479 } 480 if (found824xx && bus == 0) { 481 bus++; 482 goto retry; 483 } 484 485 /* 486 * Make sure we add at least one bridge since some old 487 * hardware doesn't actually have a host-pci bridge device. 488 * Note that pci_cfgregopen() thinks we have PCI devices.. 489 */ 490 if (!found) { 491 if (bootverbose) 492 printf( 493 "legacy_pcib_identify: no bridge found, adding pcib0 anyway\n"); 494 child = BUS_ADD_CHILD(parent, 100, "pcib", 0); 495 legacy_set_pcibus(child, 0); 496 } 497 } 498 499 static int 500 legacy_pcib_probe(device_t dev) 501 { 502 503 if (pci_cfgregopen() == 0) 504 return ENXIO; 505 return -100; 506 } 507 508 static int 509 legacy_pcib_attach(device_t dev) 510 { 511 #ifdef __HAVE_PIR 512 device_t pir; 513 #endif 514 int bus; 515 516 bus = pcib_get_bus(dev); 517 #ifdef __HAVE_PIR 518 /* 519 * Look for a PCI BIOS interrupt routing table as that will be 520 * our method of routing interrupts if we have one. 521 */ 522 if (pci_pir_probe(bus, 0)) { 523 pir = BUS_ADD_CHILD(device_get_parent(dev), 0, "pir", 0); 524 if (pir != NULL) 525 device_probe_and_attach(pir); 526 } 527 #endif 528 device_add_child(dev, "pci", bus); 529 return bus_generic_attach(dev); 530 } 531 532 int 533 legacy_pcib_read_ivar(device_t dev, device_t child, int which, 534 uintptr_t *result) 535 { 536 537 switch (which) { 538 case PCIB_IVAR_DOMAIN: 539 *result = 0; 540 return 0; 541 case PCIB_IVAR_BUS: 542 *result = legacy_get_pcibus(dev); 543 return 0; 544 } 545 return ENOENT; 546 } 547 548 int 549 legacy_pcib_write_ivar(device_t dev, device_t child, int which, 550 uintptr_t value) 551 { 552 553 switch (which) { 554 case PCIB_IVAR_DOMAIN: 555 return EINVAL; 556 case PCIB_IVAR_BUS: 557 legacy_set_pcibus(dev, value); 558 return 0; 559 } 560 return ENOENT; 561 } 562 563 /* 564 * Helper routine for x86 Host-PCI bridge driver resource allocation. 565 * This is used to adjust the start address of wildcard allocation 566 * requests to avoid low addresses that are known to be problematic. 567 * 568 * If no memory preference is given, use upper 32MB slot most BIOSes 569 * use for their memory window. This is typically only used on older 570 * laptops that don't have PCI busses behind a PCI bridge, so assuming 571 * > 32MB is likely OK. 572 * 573 * However, this can cause problems for other chipsets, so we make 574 * this tunable by hw.pci.host_mem_start. 575 */ 576 SYSCTL_DECL(_hw_pci); 577 578 static unsigned long host_mem_start = 0x80000000; 579 TUNABLE_ULONG("hw.pci.host_mem_start", &host_mem_start); 580 SYSCTL_ULONG(_hw_pci, OID_AUTO, host_mem_start, CTLFLAG_RDTUN, &host_mem_start, 581 0, "Limit the host bridge memory to being above this address."); 582 583 u_long 584 hostb_alloc_start(int type, u_long start, u_long end, u_long count) 585 { 586 587 if (start + count - 1 != end) { 588 if (type == SYS_RES_MEMORY && start < host_mem_start) 589 start = host_mem_start; 590 if (type == SYS_RES_IOPORT && start < 0x1000) 591 start = 0x1000; 592 } 593 return (start); 594 } 595 596 struct resource * 597 legacy_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 598 u_long start, u_long end, u_long count, u_int flags) 599 { 600 601 start = hostb_alloc_start(type, start, end, count); 602 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, 603 count, flags)); 604 } 605 606 static device_method_t legacy_pcib_methods[] = { 607 /* Device interface */ 608 DEVMETHOD(device_identify, legacy_pcib_identify), 609 DEVMETHOD(device_probe, legacy_pcib_probe), 610 DEVMETHOD(device_attach, legacy_pcib_attach), 611 DEVMETHOD(device_shutdown, bus_generic_shutdown), 612 DEVMETHOD(device_suspend, bus_generic_suspend), 613 DEVMETHOD(device_resume, bus_generic_resume), 614 615 /* Bus interface */ 616 DEVMETHOD(bus_read_ivar, legacy_pcib_read_ivar), 617 DEVMETHOD(bus_write_ivar, legacy_pcib_write_ivar), 618 DEVMETHOD(bus_alloc_resource, legacy_pcib_alloc_resource), 619 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 620 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 621 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 622 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 623 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 624 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 625 626 /* pcib interface */ 627 DEVMETHOD(pcib_maxslots, legacy_pcib_maxslots), 628 DEVMETHOD(pcib_read_config, legacy_pcib_read_config), 629 DEVMETHOD(pcib_write_config, legacy_pcib_write_config), 630 DEVMETHOD(pcib_route_interrupt, legacy_pcib_route_interrupt), 631 DEVMETHOD(pcib_alloc_msi, legacy_pcib_alloc_msi), 632 DEVMETHOD(pcib_release_msi, pcib_release_msi), 633 DEVMETHOD(pcib_alloc_msix, legacy_pcib_alloc_msix), 634 DEVMETHOD(pcib_release_msix, pcib_release_msix), 635 DEVMETHOD(pcib_map_msi, legacy_pcib_map_msi), 636 637 DEVMETHOD_END 638 }; 639 640 static devclass_t hostb_devclass; 641 642 DEFINE_CLASS_0(pcib, legacy_pcib_driver, legacy_pcib_methods, 1); 643 DRIVER_MODULE(pcib, legacy, legacy_pcib_driver, hostb_devclass, 0, 0); 644 645 646 /* 647 * Install placeholder to claim the resources owned by the 648 * PCI bus interface. This could be used to extract the 649 * config space registers in the extreme case where the PnP 650 * ID is available and the PCI BIOS isn't, but for now we just 651 * eat the PnP ID and do nothing else. 652 * 653 * XXX we should silence this probe, as it will generally confuse 654 * people. 655 */ 656 static struct isa_pnp_id pcibus_pnp_ids[] = { 657 { 0x030ad041 /* PNP0A03 */, "PCI Bus" }, 658 { 0x080ad041 /* PNP0A08 */, "PCIe Bus" }, 659 { 0 } 660 }; 661 662 static int 663 pcibus_pnp_probe(device_t dev) 664 { 665 int result; 666 667 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, pcibus_pnp_ids)) <= 0) 668 device_quiet(dev); 669 return(result); 670 } 671 672 static int 673 pcibus_pnp_attach(device_t dev) 674 { 675 return(0); 676 } 677 678 static device_method_t pcibus_pnp_methods[] = { 679 /* Device interface */ 680 DEVMETHOD(device_probe, pcibus_pnp_probe), 681 DEVMETHOD(device_attach, pcibus_pnp_attach), 682 DEVMETHOD(device_detach, bus_generic_detach), 683 DEVMETHOD(device_shutdown, bus_generic_shutdown), 684 DEVMETHOD(device_suspend, bus_generic_suspend), 685 DEVMETHOD(device_resume, bus_generic_resume), 686 { 0, 0 } 687 }; 688 689 static devclass_t pcibus_pnp_devclass; 690 691 DEFINE_CLASS_0(pcibus_pnp, pcibus_pnp_driver, pcibus_pnp_methods, 1); 692 DRIVER_MODULE(pcibus_pnp, isa, pcibus_pnp_driver, pcibus_pnp_devclass, 0, 0); 693 694 #ifdef __HAVE_PIR 695 /* 696 * Provide a PCI-PCI bridge driver for PCI busses behind PCI-PCI bridges 697 * that appear in the PCIBIOS Interrupt Routing Table to use the routing 698 * table for interrupt routing when possible. 699 */ 700 static int pcibios_pcib_probe(device_t bus); 701 702 static device_method_t pcibios_pcib_pci_methods[] = { 703 /* Device interface */ 704 DEVMETHOD(device_probe, pcibios_pcib_probe), 705 706 /* pcib interface */ 707 DEVMETHOD(pcib_route_interrupt, legacy_pcib_route_interrupt), 708 709 {0, 0} 710 }; 711 712 static devclass_t pcib_devclass; 713 714 DEFINE_CLASS_1(pcib, pcibios_pcib_driver, pcibios_pcib_pci_methods, 715 sizeof(struct pcib_softc), pcib_driver); 716 DRIVER_MODULE(pcibios_pcib, pci, pcibios_pcib_driver, pcib_devclass, 0, 0); 717 718 static int 719 pcibios_pcib_probe(device_t dev) 720 { 721 int bus; 722 723 if ((pci_get_class(dev) != PCIC_BRIDGE) || 724 (pci_get_subclass(dev) != PCIS_BRIDGE_PCI)) 725 return (ENXIO); 726 bus = pci_read_config(dev, PCIR_SECBUS_1, 1); 727 if (bus == 0) 728 return (ENXIO); 729 if (!pci_pir_probe(bus, 1)) 730 return (ENXIO); 731 device_set_desc(dev, "PCIBIOS PCI-PCI bridge"); 732 return (-2000); 733 } 734 #endif
Cache object: 20f8188932e26371f9f0eb3195a2914a
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]