FreeBSD/Linux Kernel Cross Reference
sys/x86/x86/identcpu.c
1 /*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * Copyright (c) 1997 KATO Takenori.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to Berkeley by
8 * William Jolitz.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * SUCH DAMAGE.
37 *
38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
39 */
40
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD: releng/10.2/sys/x86/x86/identcpu.c 284338 2015-06-13 07:31:50Z kib $");
43
44 #include "opt_cpu.h"
45
46 #include <sys/param.h>
47 #include <sys/bus.h>
48 #include <sys/cpu.h>
49 #include <sys/eventhandler.h>
50 #include <sys/limits.h>
51 #include <sys/systm.h>
52 #include <sys/kernel.h>
53 #include <sys/sysctl.h>
54 #include <sys/power.h>
55
56 #include <machine/asmacros.h>
57 #include <machine/clock.h>
58 #include <machine/cputypes.h>
59 #include <machine/frame.h>
60 #include <machine/intr_machdep.h>
61 #include <machine/md_var.h>
62 #include <machine/segments.h>
63 #include <machine/specialreg.h>
64
65 #include <amd64/vmm/intel/vmx_controls.h>
66 #include <x86/isa/icu.h>
67 #include <x86/vmware.h>
68
69 #ifdef __i386__
70 #define IDENTBLUE_CYRIX486 0
71 #define IDENTBLUE_IBMCPU 1
72 #define IDENTBLUE_CYRIXM2 2
73
74 static void identifycyrix(void);
75 static void print_transmeta_info(void);
76 #endif
77 static u_int find_cpu_vendor_id(void);
78 static void print_AMD_info(void);
79 static void print_INTEL_info(void);
80 static void print_INTEL_TLB(u_int data);
81 static void print_hypervisor_info(void);
82 static void print_svm_info(void);
83 static void print_via_padlock_info(void);
84 static void print_vmx_info(void);
85
86 int cpu_class;
87 char machine[] = MACHINE;
88
89 #ifdef __amd64__
90 #ifdef SCTL_MASK32
91 extern int adaptive_machine_arch;
92 #endif
93
94 static int
95 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
96 {
97 #ifdef SCTL_MASK32
98 static const char machine32[] = "i386";
99 #endif
100 int error;
101
102 #ifdef SCTL_MASK32
103 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
104 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
105 else
106 #endif
107 error = SYSCTL_OUT(req, machine, sizeof(machine));
108 return (error);
109
110 }
111 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD,
112 NULL, 0, sysctl_hw_machine, "A", "Machine class");
113 #else
114 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
115 machine, 0, "Machine class");
116 #endif
117
118 static char cpu_model[128];
119 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
120 cpu_model, 0, "Machine model");
121
122 static int hw_clockrate;
123 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
124 &hw_clockrate, 0, "CPU instruction clock rate");
125
126 u_int hv_high;
127 char hv_vendor[16];
128 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD, hv_vendor, 0,
129 "Hypervisor vendor");
130
131 static eventhandler_tag tsc_post_tag;
132
133 static char cpu_brand[48];
134
135 #ifdef __i386__
136 #define MAX_BRAND_INDEX 8
137
138 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
139 NULL, /* No brand */
140 "Intel Celeron",
141 "Intel Pentium III",
142 "Intel Pentium III Xeon",
143 NULL,
144 NULL,
145 NULL,
146 NULL,
147 "Intel Pentium 4"
148 };
149 #endif
150
151 static struct {
152 char *cpu_name;
153 int cpu_class;
154 } cpus[] = {
155 #ifdef __i386__
156 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
157 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
158 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
159 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
160 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
161 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
162 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
163 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
164 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
165 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
166 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
167 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
168 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
169 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
170 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
171 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
172 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
173 #else
174 { "Clawhammer", CPUCLASS_K8 }, /* CPU_CLAWHAMMER */
175 { "Sledgehammer", CPUCLASS_K8 }, /* CPU_SLEDGEHAMMER */
176 #endif
177 };
178
179 static struct {
180 char *vendor;
181 u_int vendor_id;
182 } cpu_vendors[] = {
183 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */
184 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */
185 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */
186 #ifdef __i386__
187 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */
188 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */
189 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
190 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */
191 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */
192 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */
193 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */
194 #if 0
195 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
196 { "TransmetaCPU", CPU_VENDOR_TRANSMETA },
197 #endif
198 #endif
199 };
200
201 void
202 printcpuinfo(void)
203 {
204 u_int regs[4], i;
205 char *brand;
206
207 cpu_class = cpus[cpu].cpu_class;
208 printf("CPU: ");
209 strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
210
211 /* Check for extended CPUID information and a processor name. */
212 if (cpu_exthigh >= 0x80000004) {
213 brand = cpu_brand;
214 for (i = 0x80000002; i < 0x80000005; i++) {
215 do_cpuid(i, regs);
216 memcpy(brand, regs, sizeof(regs));
217 brand += sizeof(regs);
218 }
219 }
220
221 switch (cpu_vendor_id) {
222 case CPU_VENDOR_INTEL:
223 #ifdef __i386__
224 if ((cpu_id & 0xf00) > 0x300) {
225 u_int brand_index;
226
227 cpu_model[0] = '\0';
228
229 switch (cpu_id & 0x3000) {
230 case 0x1000:
231 strcpy(cpu_model, "Overdrive ");
232 break;
233 case 0x2000:
234 strcpy(cpu_model, "Dual ");
235 break;
236 }
237
238 switch (cpu_id & 0xf00) {
239 case 0x400:
240 strcat(cpu_model, "i486 ");
241 /* Check the particular flavor of 486 */
242 switch (cpu_id & 0xf0) {
243 case 0x00:
244 case 0x10:
245 strcat(cpu_model, "DX");
246 break;
247 case 0x20:
248 strcat(cpu_model, "SX");
249 break;
250 case 0x30:
251 strcat(cpu_model, "DX2");
252 break;
253 case 0x40:
254 strcat(cpu_model, "SL");
255 break;
256 case 0x50:
257 strcat(cpu_model, "SX2");
258 break;
259 case 0x70:
260 strcat(cpu_model,
261 "DX2 Write-Back Enhanced");
262 break;
263 case 0x80:
264 strcat(cpu_model, "DX4");
265 break;
266 }
267 break;
268 case 0x500:
269 /* Check the particular flavor of 586 */
270 strcat(cpu_model, "Pentium");
271 switch (cpu_id & 0xf0) {
272 case 0x00:
273 strcat(cpu_model, " A-step");
274 break;
275 case 0x10:
276 strcat(cpu_model, "/P5");
277 break;
278 case 0x20:
279 strcat(cpu_model, "/P54C");
280 break;
281 case 0x30:
282 strcat(cpu_model, "/P24T");
283 break;
284 case 0x40:
285 strcat(cpu_model, "/P55C");
286 break;
287 case 0x70:
288 strcat(cpu_model, "/P54C");
289 break;
290 case 0x80:
291 strcat(cpu_model, "/P55C (quarter-micron)");
292 break;
293 default:
294 /* nothing */
295 break;
296 }
297 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
298 /*
299 * XXX - If/when Intel fixes the bug, this
300 * should also check the version of the
301 * CPU, not just that it's a Pentium.
302 */
303 has_f00f_bug = 1;
304 #endif
305 break;
306 case 0x600:
307 /* Check the particular flavor of 686 */
308 switch (cpu_id & 0xf0) {
309 case 0x00:
310 strcat(cpu_model, "Pentium Pro A-step");
311 break;
312 case 0x10:
313 strcat(cpu_model, "Pentium Pro");
314 break;
315 case 0x30:
316 case 0x50:
317 case 0x60:
318 strcat(cpu_model,
319 "Pentium II/Pentium II Xeon/Celeron");
320 cpu = CPU_PII;
321 break;
322 case 0x70:
323 case 0x80:
324 case 0xa0:
325 case 0xb0:
326 strcat(cpu_model,
327 "Pentium III/Pentium III Xeon/Celeron");
328 cpu = CPU_PIII;
329 break;
330 default:
331 strcat(cpu_model, "Unknown 80686");
332 break;
333 }
334 break;
335 case 0xf00:
336 strcat(cpu_model, "Pentium 4");
337 cpu = CPU_P4;
338 break;
339 default:
340 strcat(cpu_model, "unknown");
341 break;
342 }
343
344 /*
345 * If we didn't get a brand name from the extended
346 * CPUID, try to look it up in the brand table.
347 */
348 if (cpu_high > 0 && *cpu_brand == '\0') {
349 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
350 if (brand_index <= MAX_BRAND_INDEX &&
351 cpu_brandtable[brand_index] != NULL)
352 strcpy(cpu_brand,
353 cpu_brandtable[brand_index]);
354 }
355 }
356 #else
357 /* Please make up your mind folks! */
358 strcat(cpu_model, "EM64T");
359 #endif
360 break;
361 case CPU_VENDOR_AMD:
362 /*
363 * Values taken from AMD Processor Recognition
364 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
365 * (also describes ``Features'' encodings.
366 */
367 strcpy(cpu_model, "AMD ");
368 #ifdef __i386__
369 switch (cpu_id & 0xFF0) {
370 case 0x410:
371 strcat(cpu_model, "Standard Am486DX");
372 break;
373 case 0x430:
374 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
375 break;
376 case 0x470:
377 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
378 break;
379 case 0x480:
380 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
381 break;
382 case 0x490:
383 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
384 break;
385 case 0x4E0:
386 strcat(cpu_model, "Am5x86 Write-Through");
387 break;
388 case 0x4F0:
389 strcat(cpu_model, "Am5x86 Write-Back");
390 break;
391 case 0x500:
392 strcat(cpu_model, "K5 model 0");
393 break;
394 case 0x510:
395 strcat(cpu_model, "K5 model 1");
396 break;
397 case 0x520:
398 strcat(cpu_model, "K5 PR166 (model 2)");
399 break;
400 case 0x530:
401 strcat(cpu_model, "K5 PR200 (model 3)");
402 break;
403 case 0x560:
404 strcat(cpu_model, "K6");
405 break;
406 case 0x570:
407 strcat(cpu_model, "K6 266 (model 1)");
408 break;
409 case 0x580:
410 strcat(cpu_model, "K6-2");
411 break;
412 case 0x590:
413 strcat(cpu_model, "K6-III");
414 break;
415 case 0x5a0:
416 strcat(cpu_model, "Geode LX");
417 break;
418 default:
419 strcat(cpu_model, "Unknown");
420 break;
421 }
422 #else
423 if ((cpu_id & 0xf00) == 0xf00)
424 strcat(cpu_model, "AMD64 Processor");
425 else
426 strcat(cpu_model, "Unknown");
427 #endif
428 break;
429 #ifdef __i386__
430 case CPU_VENDOR_CYRIX:
431 strcpy(cpu_model, "Cyrix ");
432 switch (cpu_id & 0xff0) {
433 case 0x440:
434 strcat(cpu_model, "MediaGX");
435 break;
436 case 0x520:
437 strcat(cpu_model, "6x86");
438 break;
439 case 0x540:
440 cpu_class = CPUCLASS_586;
441 strcat(cpu_model, "GXm");
442 break;
443 case 0x600:
444 strcat(cpu_model, "6x86MX");
445 break;
446 default:
447 /*
448 * Even though CPU supports the cpuid
449 * instruction, it can be disabled.
450 * Therefore, this routine supports all Cyrix
451 * CPUs.
452 */
453 switch (cyrix_did & 0xf0) {
454 case 0x00:
455 switch (cyrix_did & 0x0f) {
456 case 0x00:
457 strcat(cpu_model, "486SLC");
458 break;
459 case 0x01:
460 strcat(cpu_model, "486DLC");
461 break;
462 case 0x02:
463 strcat(cpu_model, "486SLC2");
464 break;
465 case 0x03:
466 strcat(cpu_model, "486DLC2");
467 break;
468 case 0x04:
469 strcat(cpu_model, "486SRx");
470 break;
471 case 0x05:
472 strcat(cpu_model, "486DRx");
473 break;
474 case 0x06:
475 strcat(cpu_model, "486SRx2");
476 break;
477 case 0x07:
478 strcat(cpu_model, "486DRx2");
479 break;
480 case 0x08:
481 strcat(cpu_model, "486SRu");
482 break;
483 case 0x09:
484 strcat(cpu_model, "486DRu");
485 break;
486 case 0x0a:
487 strcat(cpu_model, "486SRu2");
488 break;
489 case 0x0b:
490 strcat(cpu_model, "486DRu2");
491 break;
492 default:
493 strcat(cpu_model, "Unknown");
494 break;
495 }
496 break;
497 case 0x10:
498 switch (cyrix_did & 0x0f) {
499 case 0x00:
500 strcat(cpu_model, "486S");
501 break;
502 case 0x01:
503 strcat(cpu_model, "486S2");
504 break;
505 case 0x02:
506 strcat(cpu_model, "486Se");
507 break;
508 case 0x03:
509 strcat(cpu_model, "486S2e");
510 break;
511 case 0x0a:
512 strcat(cpu_model, "486DX");
513 break;
514 case 0x0b:
515 strcat(cpu_model, "486DX2");
516 break;
517 case 0x0f:
518 strcat(cpu_model, "486DX4");
519 break;
520 default:
521 strcat(cpu_model, "Unknown");
522 break;
523 }
524 break;
525 case 0x20:
526 if ((cyrix_did & 0x0f) < 8)
527 strcat(cpu_model, "6x86"); /* Where did you get it? */
528 else
529 strcat(cpu_model, "5x86");
530 break;
531 case 0x30:
532 strcat(cpu_model, "6x86");
533 break;
534 case 0x40:
535 if ((cyrix_did & 0xf000) == 0x3000) {
536 cpu_class = CPUCLASS_586;
537 strcat(cpu_model, "GXm");
538 } else
539 strcat(cpu_model, "MediaGX");
540 break;
541 case 0x50:
542 strcat(cpu_model, "6x86MX");
543 break;
544 case 0xf0:
545 switch (cyrix_did & 0x0f) {
546 case 0x0d:
547 strcat(cpu_model, "Overdrive CPU");
548 break;
549 case 0x0e:
550 strcpy(cpu_model, "Texas Instruments 486SXL");
551 break;
552 case 0x0f:
553 strcat(cpu_model, "486SLC/DLC");
554 break;
555 default:
556 strcat(cpu_model, "Unknown");
557 break;
558 }
559 break;
560 default:
561 strcat(cpu_model, "Unknown");
562 break;
563 }
564 break;
565 }
566 break;
567 case CPU_VENDOR_RISE:
568 strcpy(cpu_model, "Rise ");
569 switch (cpu_id & 0xff0) {
570 case 0x500: /* 6401 and 6441 (Kirin) */
571 case 0x520: /* 6510 (Lynx) */
572 strcat(cpu_model, "mP6");
573 break;
574 default:
575 strcat(cpu_model, "Unknown");
576 }
577 break;
578 #endif
579 case CPU_VENDOR_CENTAUR:
580 #ifdef __i386__
581 switch (cpu_id & 0xff0) {
582 case 0x540:
583 strcpy(cpu_model, "IDT WinChip C6");
584 break;
585 case 0x580:
586 strcpy(cpu_model, "IDT WinChip 2");
587 break;
588 case 0x590:
589 strcpy(cpu_model, "IDT WinChip 3");
590 break;
591 case 0x660:
592 strcpy(cpu_model, "VIA C3 Samuel");
593 break;
594 case 0x670:
595 if (cpu_id & 0x8)
596 strcpy(cpu_model, "VIA C3 Ezra");
597 else
598 strcpy(cpu_model, "VIA C3 Samuel 2");
599 break;
600 case 0x680:
601 strcpy(cpu_model, "VIA C3 Ezra-T");
602 break;
603 case 0x690:
604 strcpy(cpu_model, "VIA C3 Nehemiah");
605 break;
606 case 0x6a0:
607 case 0x6d0:
608 strcpy(cpu_model, "VIA C7 Esther");
609 break;
610 case 0x6f0:
611 strcpy(cpu_model, "VIA Nano");
612 break;
613 default:
614 strcpy(cpu_model, "VIA/IDT Unknown");
615 }
616 #else
617 strcpy(cpu_model, "VIA ");
618 if ((cpu_id & 0xff0) == 0x6f0)
619 strcat(cpu_model, "Nano Processor");
620 else
621 strcat(cpu_model, "Unknown");
622 #endif
623 break;
624 #ifdef __i386__
625 case CPU_VENDOR_IBM:
626 strcpy(cpu_model, "Blue Lightning CPU");
627 break;
628 case CPU_VENDOR_NSC:
629 switch (cpu_id & 0xff0) {
630 case 0x540:
631 strcpy(cpu_model, "Geode SC1100");
632 cpu = CPU_GEODE1100;
633 break;
634 default:
635 strcpy(cpu_model, "Geode/NSC unknown");
636 break;
637 }
638 break;
639 #endif
640 default:
641 strcat(cpu_model, "Unknown");
642 break;
643 }
644
645 /*
646 * Replace cpu_model with cpu_brand minus leading spaces if
647 * we have one.
648 */
649 brand = cpu_brand;
650 while (*brand == ' ')
651 ++brand;
652 if (*brand != '\0')
653 strcpy(cpu_model, brand);
654
655 printf("%s (", cpu_model);
656 if (tsc_freq != 0) {
657 hw_clockrate = (tsc_freq + 5000) / 1000000;
658 printf("%jd.%02d-MHz ",
659 (intmax_t)(tsc_freq + 4999) / 1000000,
660 (u_int)((tsc_freq + 4999) / 10000) % 100);
661 }
662 switch(cpu_class) {
663 #ifdef __i386__
664 case CPUCLASS_286:
665 printf("286");
666 break;
667 case CPUCLASS_386:
668 printf("386");
669 break;
670 #if defined(I486_CPU)
671 case CPUCLASS_486:
672 printf("486");
673 break;
674 #endif
675 #if defined(I586_CPU)
676 case CPUCLASS_586:
677 printf("586");
678 break;
679 #endif
680 #if defined(I686_CPU)
681 case CPUCLASS_686:
682 printf("686");
683 break;
684 #endif
685 #else
686 case CPUCLASS_K8:
687 printf("K8");
688 break;
689 #endif
690 default:
691 printf("Unknown"); /* will panic below... */
692 }
693 printf("-class CPU)\n");
694 if (*cpu_vendor)
695 printf(" Origin=\"%s\"", cpu_vendor);
696 if (cpu_id)
697 printf(" Id=0x%x", cpu_id);
698
699 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
700 cpu_vendor_id == CPU_VENDOR_AMD ||
701 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
702 #ifdef __i386__
703 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
704 cpu_vendor_id == CPU_VENDOR_RISE ||
705 cpu_vendor_id == CPU_VENDOR_NSC ||
706 (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
707 #endif
708 0) {
709 printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id));
710 printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id));
711 printf(" Stepping=%u", cpu_id & CPUID_STEPPING);
712 #ifdef __i386__
713 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
714 printf("\n DIR=0x%04x", cyrix_did);
715 #endif
716
717 /*
718 * AMD CPUID Specification
719 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
720 *
721 * Intel Processor Identification and CPUID Instruction
722 * http://www.intel.com/assets/pdf/appnote/241618.pdf
723 */
724 if (cpu_high > 0) {
725
726 /*
727 * Here we should probably set up flags indicating
728 * whether or not various features are available.
729 * The interesting ones are probably VME, PSE, PAE,
730 * and PGE. The code already assumes without bothering
731 * to check that all CPUs >= Pentium have a TSC and
732 * MSRs.
733 */
734 printf("\n Features=0x%b", cpu_feature,
735 "\020"
736 "\001FPU" /* Integral FPU */
737 "\002VME" /* Extended VM86 mode support */
738 "\003DE" /* Debugging Extensions (CR4.DE) */
739 "\004PSE" /* 4MByte page tables */
740 "\005TSC" /* Timestamp counter */
741 "\006MSR" /* Machine specific registers */
742 "\007PAE" /* Physical address extension */
743 "\010MCE" /* Machine Check support */
744 "\011CX8" /* CMPEXCH8 instruction */
745 "\012APIC" /* SMP local APIC */
746 "\013oldMTRR" /* Previous implementation of MTRR */
747 "\014SEP" /* Fast System Call */
748 "\015MTRR" /* Memory Type Range Registers */
749 "\016PGE" /* PG_G (global bit) support */
750 "\017MCA" /* Machine Check Architecture */
751 "\020CMOV" /* CMOV instruction */
752 "\021PAT" /* Page attributes table */
753 "\022PSE36" /* 36 bit address space support */
754 "\023PN" /* Processor Serial number */
755 "\024CLFLUSH" /* Has the CLFLUSH instruction */
756 "\025<b20>"
757 "\026DTS" /* Debug Trace Store */
758 "\027ACPI" /* ACPI support */
759 "\030MMX" /* MMX instructions */
760 "\031FXSR" /* FXSAVE/FXRSTOR */
761 "\032SSE" /* Streaming SIMD Extensions */
762 "\033SSE2" /* Streaming SIMD Extensions #2 */
763 "\034SS" /* Self snoop */
764 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
765 "\036TM" /* Thermal Monitor clock slowdown */
766 "\037IA64" /* CPU can execute IA64 instructions */
767 "\040PBE" /* Pending Break Enable */
768 );
769
770 if (cpu_feature2 != 0) {
771 printf("\n Features2=0x%b", cpu_feature2,
772 "\020"
773 "\001SSE3" /* SSE3 */
774 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
775 "\003DTES64" /* 64-bit Debug Trace */
776 "\004MON" /* MONITOR/MWAIT Instructions */
777 "\005DS_CPL" /* CPL Qualified Debug Store */
778 "\006VMX" /* Virtual Machine Extensions */
779 "\007SMX" /* Safer Mode Extensions */
780 "\010EST" /* Enhanced SpeedStep */
781 "\011TM2" /* Thermal Monitor 2 */
782 "\012SSSE3" /* SSSE3 */
783 "\013CNXT-ID" /* L1 context ID available */
784 "\014<b11>"
785 "\015FMA" /* Fused Multiply Add */
786 "\016CX16" /* CMPXCHG16B Instruction */
787 "\017xTPR" /* Send Task Priority Messages*/
788 "\020PDCM" /* Perf/Debug Capability MSR */
789 "\021<b16>"
790 "\022PCID" /* Process-context Identifiers*/
791 "\023DCA" /* Direct Cache Access */
792 "\024SSE4.1" /* SSE 4.1 */
793 "\025SSE4.2" /* SSE 4.2 */
794 "\026x2APIC" /* xAPIC Extensions */
795 "\027MOVBE" /* MOVBE Instruction */
796 "\030POPCNT" /* POPCNT Instruction */
797 "\031TSCDLT" /* TSC-Deadline Timer */
798 "\032AESNI" /* AES Crypto */
799 "\033XSAVE" /* XSAVE/XRSTOR States */
800 "\034OSXSAVE" /* OS-Enabled State Management*/
801 "\035AVX" /* Advanced Vector Extensions */
802 "\036F16C" /* Half-precision conversions */
803 "\037RDRAND" /* RDRAND Instruction */
804 "\040HV" /* Hypervisor */
805 );
806 }
807
808 if (amd_feature != 0) {
809 printf("\n AMD Features=0x%b", amd_feature,
810 "\020" /* in hex */
811 "\001<s0>" /* Same */
812 "\002<s1>" /* Same */
813 "\003<s2>" /* Same */
814 "\004<s3>" /* Same */
815 "\005<s4>" /* Same */
816 "\006<s5>" /* Same */
817 "\007<s6>" /* Same */
818 "\010<s7>" /* Same */
819 "\011<s8>" /* Same */
820 "\012<s9>" /* Same */
821 "\013<b10>" /* Undefined */
822 "\014SYSCALL" /* Have SYSCALL/SYSRET */
823 "\015<s12>" /* Same */
824 "\016<s13>" /* Same */
825 "\017<s14>" /* Same */
826 "\020<s15>" /* Same */
827 "\021<s16>" /* Same */
828 "\022<s17>" /* Same */
829 "\023<b18>" /* Reserved, unknown */
830 "\024MP" /* Multiprocessor Capable */
831 "\025NX" /* Has EFER.NXE, NX */
832 "\026<b21>" /* Undefined */
833 "\027MMX+" /* AMD MMX Extensions */
834 "\030<s23>" /* Same */
835 "\031<s24>" /* Same */
836 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */
837 "\033Page1GB" /* 1-GB large page support */
838 "\034RDTSCP" /* RDTSCP */
839 "\035<b28>" /* Undefined */
840 "\036LM" /* 64 bit long mode */
841 "\0373DNow!+" /* AMD 3DNow! Extensions */
842 "\0403DNow!" /* AMD 3DNow! */
843 );
844 }
845
846 if (amd_feature2 != 0) {
847 printf("\n AMD Features2=0x%b", amd_feature2,
848 "\020"
849 "\001LAHF" /* LAHF/SAHF in long mode */
850 "\002CMP" /* CMP legacy */
851 "\003SVM" /* Secure Virtual Mode */
852 "\004ExtAPIC" /* Extended APIC register */
853 "\005CR8" /* CR8 in legacy mode */
854 "\006ABM" /* LZCNT instruction */
855 "\007SSE4A" /* SSE4A */
856 "\010MAS" /* Misaligned SSE mode */
857 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
858 "\012OSVW" /* OS visible workaround */
859 "\013IBS" /* Instruction based sampling */
860 "\014XOP" /* XOP extended instructions */
861 "\015SKINIT" /* SKINIT/STGI */
862 "\016WDT" /* Watchdog timer */
863 "\017<b14>"
864 "\020LWP" /* Lightweight Profiling */
865 "\021FMA4" /* 4-operand FMA instructions */
866 "\022TCE" /* Translation Cache Extension */
867 "\023<b18>"
868 "\024NodeId" /* NodeId MSR support */
869 "\025<b20>"
870 "\026TBM" /* Trailing Bit Manipulation */
871 "\027Topology" /* Topology Extensions */
872 "\030PCXC" /* Core perf count */
873 "\031PNXC" /* NB perf count */
874 "\032<b25>"
875 "\033DBE" /* Data Breakpoint extension */
876 "\034PTSC" /* Performance TSC */
877 "\035PL2I" /* L2I perf count */
878 "\036<b29>"
879 "\037<b30>"
880 "\040<b31>"
881 );
882 }
883
884 if (cpu_stdext_feature != 0) {
885 printf("\n Structured Extended Features=0x%b",
886 cpu_stdext_feature,
887 "\020"
888 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
889 "\001FSGSBASE"
890 "\002TSCADJ"
891 /* Bit Manipulation Instructions */
892 "\004BMI1"
893 /* Hardware Lock Elision */
894 "\005HLE"
895 /* Advanced Vector Instructions 2 */
896 "\006AVX2"
897 /* Supervisor Mode Execution Prot. */
898 "\010SMEP"
899 /* Bit Manipulation Instructions */
900 "\011BMI2"
901 "\012ERMS"
902 /* Invalidate Processor Context ID */
903 "\013INVPCID"
904 /* Restricted Transactional Memory */
905 "\014RTM"
906 "\015PQM"
907 "\016NFPUSG"
908 "\020PQE"
909 /* Intel Memory Protection Extensions */
910 "\017MPX"
911 /* AVX512 Foundation */
912 "\021AVX512F"
913 /* Enhanced NRBG */
914 "\023RDSEED"
915 /* ADCX + ADOX */
916 "\024ADX"
917 /* Supervisor Mode Access Prevention */
918 "\025SMAP"
919 "\030CLFLUSHOPT"
920 "\032PROCTRACE"
921 "\033AVX512PF"
922 "\034AVX512ER"
923 "\035AVX512CD"
924 "\036SHA"
925 );
926 }
927
928 if (cpu_stdext_feature2 != 0) {
929 printf("\n Structured Extended Features2=0x%b",
930 cpu_stdext_feature2,
931 "\020"
932 "\001PREFETCHWT1"
933 "\004PKU"
934 "\005OSPKE"
935 );
936 }
937
938 if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
939 cpuid_count(0xd, 0x1, regs);
940 if (regs[0] != 0) {
941 printf("\n XSAVE Features=0x%b",
942 regs[0],
943 "\020"
944 "\001XSAVEOPT"
945 "\002XSAVEC"
946 "\003XINUSE"
947 "\004XSAVES");
948 }
949 }
950
951 if (via_feature_rng != 0 || via_feature_xcrypt != 0)
952 print_via_padlock_info();
953
954 if (cpu_feature2 & CPUID2_VMX)
955 print_vmx_info();
956
957 if (amd_feature2 & AMDID2_SVM)
958 print_svm_info();
959
960 if ((cpu_feature & CPUID_HTT) &&
961 cpu_vendor_id == CPU_VENDOR_AMD)
962 cpu_feature &= ~CPUID_HTT;
963
964 /*
965 * If this CPU supports P-state invariant TSC then
966 * mention the capability.
967 */
968 if (tsc_is_invariant) {
969 printf("\n TSC: P-state invariant");
970 if (tsc_perf_stat)
971 printf(", performance statistics");
972 }
973 }
974 #ifdef __i386__
975 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
976 printf(" DIR=0x%04x", cyrix_did);
977 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
978 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
979 #ifndef CYRIX_CACHE_REALLY_WORKS
980 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
981 printf("\n CPU cache: write-through mode");
982 #endif
983 #endif
984 }
985
986 /* Avoid ugly blank lines: only print newline when we have to. */
987 if (*cpu_vendor || cpu_id)
988 printf("\n");
989
990 if (bootverbose) {
991 if (cpu_vendor_id == CPU_VENDOR_AMD)
992 print_AMD_info();
993 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
994 print_INTEL_info();
995 #ifdef __i386__
996 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
997 print_transmeta_info();
998 #endif
999 }
1000
1001 print_hypervisor_info();
1002 }
1003
1004 void
1005 panicifcpuunsupported(void)
1006 {
1007
1008 #ifdef __i386__
1009 #if !defined(lint)
1010 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1011 #error This kernel is not configured for one of the supported CPUs
1012 #endif
1013 #else /* lint */
1014 #endif /* lint */
1015 #else /* __amd64__ */
1016 #ifndef HAMMER
1017 #error "You need to specify a cpu type"
1018 #endif
1019 #endif
1020 /*
1021 * Now that we have told the user what they have,
1022 * let them know if that machine type isn't configured.
1023 */
1024 switch (cpu_class) {
1025 #ifdef __i386__
1026 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
1027 case CPUCLASS_386:
1028 #if !defined(I486_CPU)
1029 case CPUCLASS_486:
1030 #endif
1031 #if !defined(I586_CPU)
1032 case CPUCLASS_586:
1033 #endif
1034 #if !defined(I686_CPU)
1035 case CPUCLASS_686:
1036 #endif
1037 #else /* __amd64__ */
1038 case CPUCLASS_X86:
1039 #ifndef HAMMER
1040 case CPUCLASS_K8:
1041 #endif
1042 #endif
1043 panic("CPU class not configured");
1044 default:
1045 break;
1046 }
1047 }
1048
1049 #ifdef __i386__
1050 static volatile u_int trap_by_rdmsr;
1051
1052 /*
1053 * Special exception 6 handler.
1054 * The rdmsr instruction generates invalid opcodes fault on 486-class
1055 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
1056 * function identblue() when this handler is called. Stacked eip should
1057 * be advanced.
1058 */
1059 inthand_t bluetrap6;
1060 #ifdef __GNUCLIKE_ASM
1061 __asm
1062 (" \n\
1063 .text \n\
1064 .p2align 2,0x90 \n\
1065 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\
1066 " __XSTRING(CNAME(bluetrap6)) ": \n\
1067 ss \n\
1068 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1069 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1070 iret \n\
1071 ");
1072 #endif
1073
1074 /*
1075 * Special exception 13 handler.
1076 * Accessing non-existent MSR generates general protection fault.
1077 */
1078 inthand_t bluetrap13;
1079 #ifdef __GNUCLIKE_ASM
1080 __asm
1081 (" \n\
1082 .text \n\
1083 .p2align 2,0x90 \n\
1084 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\
1085 " __XSTRING(CNAME(bluetrap13)) ": \n\
1086 ss \n\
1087 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1088 popl %eax /* discard error code */ \n\
1089 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1090 iret \n\
1091 ");
1092 #endif
1093
1094 /*
1095 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1096 * support cpuid instruction. This function should be called after
1097 * loading interrupt descriptor table register.
1098 *
1099 * I don't like this method that handles fault, but I couldn't get
1100 * information for any other methods. Does blue giant know?
1101 */
1102 static int
1103 identblue(void)
1104 {
1105
1106 trap_by_rdmsr = 0;
1107
1108 /*
1109 * Cyrix 486-class CPU does not support rdmsr instruction.
1110 * The rdmsr instruction generates invalid opcode fault, and exception
1111 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
1112 * bluetrap6() set the magic number to trap_by_rdmsr.
1113 */
1114 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1115 GSEL(GCODE_SEL, SEL_KPL));
1116
1117 /*
1118 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1119 * In this case, rdmsr generates general protection fault, and
1120 * exception will be trapped by bluetrap13().
1121 */
1122 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1123 GSEL(GCODE_SEL, SEL_KPL));
1124
1125 rdmsr(0x1002); /* Cyrix CPU generates fault. */
1126
1127 if (trap_by_rdmsr == 0xa8c1d)
1128 return IDENTBLUE_CYRIX486;
1129 else if (trap_by_rdmsr == 0xa89c4)
1130 return IDENTBLUE_CYRIXM2;
1131 return IDENTBLUE_IBMCPU;
1132 }
1133
1134
1135 /*
1136 * identifycyrix() set lower 16 bits of cyrix_did as follows:
1137 *
1138 * F E D C B A 9 8 7 6 5 4 3 2 1 0
1139 * +-------+-------+---------------+
1140 * | SID | RID | Device ID |
1141 * | (DIR 1) | (DIR 0) |
1142 * +-------+-------+---------------+
1143 */
1144 static void
1145 identifycyrix(void)
1146 {
1147 register_t saveintr;
1148 int ccr2_test = 0, dir_test = 0;
1149 u_char ccr2, ccr3;
1150
1151 saveintr = intr_disable();
1152
1153 ccr2 = read_cyrix_reg(CCR2);
1154 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1155 read_cyrix_reg(CCR2);
1156 if (read_cyrix_reg(CCR2) != ccr2)
1157 ccr2_test = 1;
1158 write_cyrix_reg(CCR2, ccr2);
1159
1160 ccr3 = read_cyrix_reg(CCR3);
1161 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1162 read_cyrix_reg(CCR3);
1163 if (read_cyrix_reg(CCR3) != ccr3)
1164 dir_test = 1; /* CPU supports DIRs. */
1165 write_cyrix_reg(CCR3, ccr3);
1166
1167 if (dir_test) {
1168 /* Device ID registers are available. */
1169 cyrix_did = read_cyrix_reg(DIR1) << 8;
1170 cyrix_did += read_cyrix_reg(DIR0);
1171 } else if (ccr2_test)
1172 cyrix_did = 0x0010; /* 486S A-step */
1173 else
1174 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
1175
1176 intr_restore(saveintr);
1177 }
1178 #endif
1179
1180 /* Update TSC freq with the value indicated by the caller. */
1181 static void
1182 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1183 {
1184
1185 /* If there was an error during the transition, don't do anything. */
1186 if (status != 0)
1187 return;
1188
1189 /* Total setting for this level gives the new frequency in MHz. */
1190 hw_clockrate = level->total_set.freq;
1191 }
1192
1193 static void
1194 hook_tsc_freq(void *arg __unused)
1195 {
1196
1197 if (tsc_is_invariant)
1198 return;
1199
1200 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1201 tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1202 }
1203
1204 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1205
1206 #ifndef XEN
1207 static const char *const vm_bnames[] = {
1208 "QEMU", /* QEMU */
1209 "Plex86", /* Plex86 */
1210 "Bochs", /* Bochs */
1211 "Xen", /* Xen */
1212 "BHYVE", /* bhyve */
1213 "Seabios", /* KVM */
1214 NULL
1215 };
1216
1217 static const char *const vm_pnames[] = {
1218 "VMware Virtual Platform", /* VMWare VM */
1219 "Virtual Machine", /* Microsoft VirtualPC */
1220 "VirtualBox", /* Sun xVM VirtualBox */
1221 "Parallels Virtual Platform", /* Parallels VM */
1222 "KVM", /* KVM */
1223 NULL
1224 };
1225
1226 static void
1227 identify_hypervisor(void)
1228 {
1229 u_int regs[4];
1230 char *p;
1231 int i;
1232
1233 /*
1234 * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1235 * http://lkml.org/lkml/2008/10/1/246
1236 *
1237 * KB1009458: Mechanisms to determine if software is running in
1238 * a VMware virtual machine
1239 * http://kb.vmware.com/kb/1009458
1240 */
1241 if (cpu_feature2 & CPUID2_HV) {
1242 vm_guest = VM_GUEST_VM;
1243 do_cpuid(0x40000000, regs);
1244 if (regs[0] >= 0x40000000) {
1245 hv_high = regs[0];
1246 ((u_int *)&hv_vendor)[0] = regs[1];
1247 ((u_int *)&hv_vendor)[1] = regs[2];
1248 ((u_int *)&hv_vendor)[2] = regs[3];
1249 hv_vendor[12] = '\0';
1250 if (strcmp(hv_vendor, "VMwareVMware") == 0)
1251 vm_guest = VM_GUEST_VMWARE;
1252 }
1253 return;
1254 }
1255
1256 /*
1257 * Examine SMBIOS strings for older hypervisors.
1258 */
1259 p = getenv("smbios.system.serial");
1260 if (p != NULL) {
1261 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1262 vmware_hvcall(VMW_HVCMD_GETVERSION, regs);
1263 if (regs[1] == VMW_HVMAGIC) {
1264 vm_guest = VM_GUEST_VMWARE;
1265 freeenv(p);
1266 return;
1267 }
1268 }
1269 freeenv(p);
1270 }
1271
1272 /*
1273 * XXX: Some of these entries may not be needed since they were
1274 * added to FreeBSD before the checks above.
1275 */
1276 p = getenv("smbios.bios.vendor");
1277 if (p != NULL) {
1278 for (i = 0; vm_bnames[i] != NULL; i++)
1279 if (strcmp(p, vm_bnames[i]) == 0) {
1280 vm_guest = VM_GUEST_VM;
1281 freeenv(p);
1282 return;
1283 }
1284 freeenv(p);
1285 }
1286 p = getenv("smbios.system.product");
1287 if (p != NULL) {
1288 for (i = 0; vm_pnames[i] != NULL; i++)
1289 if (strcmp(p, vm_pnames[i]) == 0) {
1290 vm_guest = VM_GUEST_VM;
1291 freeenv(p);
1292 return;
1293 }
1294 freeenv(p);
1295 }
1296 }
1297 #endif
1298
1299 /*
1300 * Final stage of CPU identification.
1301 */
1302 #ifdef __i386__
1303 void
1304 finishidentcpu(void)
1305 #else
1306 void
1307 identify_cpu(void)
1308 #endif
1309 {
1310 u_int regs[4], cpu_stdext_disable;
1311 #ifdef __i386__
1312 u_char ccr3;
1313 #endif
1314
1315 #ifdef __amd64__
1316 do_cpuid(0, regs);
1317 cpu_high = regs[0];
1318 ((u_int *)&cpu_vendor)[0] = regs[1];
1319 ((u_int *)&cpu_vendor)[1] = regs[3];
1320 ((u_int *)&cpu_vendor)[2] = regs[2];
1321 cpu_vendor[12] = '\0';
1322
1323 do_cpuid(1, regs);
1324 cpu_id = regs[0];
1325 cpu_procinfo = regs[1];
1326 cpu_feature = regs[3];
1327 cpu_feature2 = regs[2];
1328 #endif
1329
1330 #ifndef XEN
1331 identify_hypervisor();
1332 #endif
1333 cpu_vendor_id = find_cpu_vendor_id();
1334
1335 /*
1336 * Clear "Limit CPUID Maxval" bit and get the largest standard CPUID
1337 * function number again if it is set from BIOS. It is necessary
1338 * for probing correct CPU topology later.
1339 * XXX This is only done on the BSP package.
1340 */
1341 if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high > 0 && cpu_high < 4 &&
1342 ((CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1343 (CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1344 uint64_t msr;
1345 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1346 if ((msr & 0x400000ULL) != 0) {
1347 wrmsr(MSR_IA32_MISC_ENABLE, msr & ~0x400000ULL);
1348 do_cpuid(0, regs);
1349 cpu_high = regs[0];
1350 }
1351 }
1352
1353 if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1354 do_cpuid(5, regs);
1355 cpu_mon_mwait_flags = regs[2];
1356 cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE;
1357 cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE;
1358 }
1359
1360 if (cpu_high >= 7) {
1361 cpuid_count(7, 0, regs);
1362 cpu_stdext_feature = regs[1];
1363
1364 /*
1365 * Some hypervisors fail to filter out unsupported
1366 * extended features. For now, disable the
1367 * extensions, activation of which requires setting a
1368 * bit in CR4, and which VM monitors do not support.
1369 */
1370 if (cpu_feature2 & CPUID2_HV) {
1371 cpu_stdext_disable = CPUID_STDEXT_FSGSBASE |
1372 CPUID_STDEXT_SMEP;
1373 } else
1374 cpu_stdext_disable = 0;
1375 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1376 cpu_stdext_feature &= ~cpu_stdext_disable;
1377 cpu_stdext_feature2 = regs[2];
1378 }
1379
1380 #ifdef __i386__
1381 if (cpu_high > 0 &&
1382 (cpu_vendor_id == CPU_VENDOR_INTEL ||
1383 cpu_vendor_id == CPU_VENDOR_AMD ||
1384 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1385 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1386 cpu_vendor_id == CPU_VENDOR_NSC)) {
1387 do_cpuid(0x80000000, regs);
1388 if (regs[0] >= 0x80000000)
1389 cpu_exthigh = regs[0];
1390 }
1391 #else
1392 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1393 cpu_vendor_id == CPU_VENDOR_AMD ||
1394 cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1395 do_cpuid(0x80000000, regs);
1396 cpu_exthigh = regs[0];
1397 }
1398 #endif
1399 if (cpu_exthigh >= 0x80000001) {
1400 do_cpuid(0x80000001, regs);
1401 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1402 amd_feature2 = regs[2];
1403 }
1404 if (cpu_exthigh >= 0x80000007) {
1405 do_cpuid(0x80000007, regs);
1406 amd_pminfo = regs[3];
1407 }
1408 if (cpu_exthigh >= 0x80000008) {
1409 do_cpuid(0x80000008, regs);
1410 cpu_maxphyaddr = regs[0] & 0xff;
1411 cpu_procinfo2 = regs[2];
1412 } else {
1413 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1414 }
1415
1416 #ifdef __i386__
1417 if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1418 if (cpu == CPU_486) {
1419 /*
1420 * These conditions are equivalent to:
1421 * - CPU does not support cpuid instruction.
1422 * - Cyrix/IBM CPU is detected.
1423 */
1424 if (identblue() == IDENTBLUE_IBMCPU) {
1425 strcpy(cpu_vendor, "IBM");
1426 cpu_vendor_id = CPU_VENDOR_IBM;
1427 cpu = CPU_BLUE;
1428 return;
1429 }
1430 }
1431 switch (cpu_id & 0xf00) {
1432 case 0x600:
1433 /*
1434 * Cyrix's datasheet does not describe DIRs.
1435 * Therefor, I assume it does not have them
1436 * and use the result of the cpuid instruction.
1437 * XXX they seem to have it for now at least. -Peter
1438 */
1439 identifycyrix();
1440 cpu = CPU_M2;
1441 break;
1442 default:
1443 identifycyrix();
1444 /*
1445 * This routine contains a trick.
1446 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1447 */
1448 switch (cyrix_did & 0x00f0) {
1449 case 0x00:
1450 case 0xf0:
1451 cpu = CPU_486DLC;
1452 break;
1453 case 0x10:
1454 cpu = CPU_CY486DX;
1455 break;
1456 case 0x20:
1457 if ((cyrix_did & 0x000f) < 8)
1458 cpu = CPU_M1;
1459 else
1460 cpu = CPU_M1SC;
1461 break;
1462 case 0x30:
1463 cpu = CPU_M1;
1464 break;
1465 case 0x40:
1466 /* MediaGX CPU */
1467 cpu = CPU_M1SC;
1468 break;
1469 default:
1470 /* M2 and later CPUs are treated as M2. */
1471 cpu = CPU_M2;
1472
1473 /*
1474 * enable cpuid instruction.
1475 */
1476 ccr3 = read_cyrix_reg(CCR3);
1477 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1478 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1479 write_cyrix_reg(CCR3, ccr3);
1480
1481 do_cpuid(0, regs);
1482 cpu_high = regs[0]; /* eax */
1483 do_cpuid(1, regs);
1484 cpu_id = regs[0]; /* eax */
1485 cpu_feature = regs[3]; /* edx */
1486 break;
1487 }
1488 }
1489 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1490 /*
1491 * There are BlueLightning CPUs that do not change
1492 * undefined flags by dividing 5 by 2. In this case,
1493 * the CPU identification routine in locore.s leaves
1494 * cpu_vendor null string and puts CPU_486 into the
1495 * cpu.
1496 */
1497 if (identblue() == IDENTBLUE_IBMCPU) {
1498 strcpy(cpu_vendor, "IBM");
1499 cpu_vendor_id = CPU_VENDOR_IBM;
1500 cpu = CPU_BLUE;
1501 return;
1502 }
1503 }
1504 #else
1505 /* XXX */
1506 cpu = CPU_CLAWHAMMER;
1507 #endif
1508 }
1509
1510 static u_int
1511 find_cpu_vendor_id(void)
1512 {
1513 int i;
1514
1515 for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++)
1516 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1517 return (cpu_vendors[i].vendor_id);
1518 return (0);
1519 }
1520
1521 static void
1522 print_AMD_assoc(int i)
1523 {
1524 if (i == 255)
1525 printf(", fully associative\n");
1526 else
1527 printf(", %d-way associative\n", i);
1528 }
1529
1530 static void
1531 print_AMD_l2_assoc(int i)
1532 {
1533 switch (i & 0x0f) {
1534 case 0: printf(", disabled/not present\n"); break;
1535 case 1: printf(", direct mapped\n"); break;
1536 case 2: printf(", 2-way associative\n"); break;
1537 case 4: printf(", 4-way associative\n"); break;
1538 case 6: printf(", 8-way associative\n"); break;
1539 case 8: printf(", 16-way associative\n"); break;
1540 case 15: printf(", fully associative\n"); break;
1541 default: printf(", reserved configuration\n"); break;
1542 }
1543 }
1544
1545 static void
1546 print_AMD_info(void)
1547 {
1548 #ifdef __i386__
1549 uint64_t amd_whcr;
1550 #endif
1551 u_int regs[4];
1552
1553 if (cpu_exthigh >= 0x80000005) {
1554 do_cpuid(0x80000005, regs);
1555 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1556 print_AMD_assoc(regs[0] >> 24);
1557
1558 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1559 print_AMD_assoc((regs[0] >> 8) & 0xff);
1560
1561 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1562 print_AMD_assoc(regs[1] >> 24);
1563
1564 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1565 print_AMD_assoc((regs[1] >> 8) & 0xff);
1566
1567 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1568 printf(", %d bytes/line", regs[2] & 0xff);
1569 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1570 print_AMD_assoc((regs[2] >> 16) & 0xff);
1571
1572 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1573 printf(", %d bytes/line", regs[3] & 0xff);
1574 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1575 print_AMD_assoc((regs[3] >> 16) & 0xff);
1576 }
1577
1578 if (cpu_exthigh >= 0x80000006) {
1579 do_cpuid(0x80000006, regs);
1580 if ((regs[0] >> 16) != 0) {
1581 printf("L2 2MB data TLB: %d entries",
1582 (regs[0] >> 16) & 0xfff);
1583 print_AMD_l2_assoc(regs[0] >> 28);
1584 printf("L2 2MB instruction TLB: %d entries",
1585 regs[0] & 0xfff);
1586 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1587 } else {
1588 printf("L2 2MB unified TLB: %d entries",
1589 regs[0] & 0xfff);
1590 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1591 }
1592 if ((regs[1] >> 16) != 0) {
1593 printf("L2 4KB data TLB: %d entries",
1594 (regs[1] >> 16) & 0xfff);
1595 print_AMD_l2_assoc(regs[1] >> 28);
1596
1597 printf("L2 4KB instruction TLB: %d entries",
1598 (regs[1] >> 16) & 0xfff);
1599 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1600 } else {
1601 printf("L2 4KB unified TLB: %d entries",
1602 (regs[1] >> 16) & 0xfff);
1603 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1604 }
1605 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1606 printf(", %d bytes/line", regs[2] & 0xff);
1607 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1608 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1609 }
1610
1611 #ifdef __i386__
1612 if (((cpu_id & 0xf00) == 0x500)
1613 && (((cpu_id & 0x0f0) > 0x80)
1614 || (((cpu_id & 0x0f0) == 0x80)
1615 && (cpu_id & 0x00f) > 0x07))) {
1616 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1617 amd_whcr = rdmsr(0xc0000082);
1618 if (!(amd_whcr & (0x3ff << 22))) {
1619 printf("Write Allocate Disable\n");
1620 } else {
1621 printf("Write Allocate Enable Limit: %dM bytes\n",
1622 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1623 printf("Write Allocate 15-16M bytes: %s\n",
1624 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1625 }
1626 } else if (((cpu_id & 0xf00) == 0x500)
1627 && ((cpu_id & 0x0f0) > 0x50)) {
1628 /* K6, K6-2(old core) */
1629 amd_whcr = rdmsr(0xc0000082);
1630 if (!(amd_whcr & (0x7f << 1))) {
1631 printf("Write Allocate Disable\n");
1632 } else {
1633 printf("Write Allocate Enable Limit: %dM bytes\n",
1634 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1635 printf("Write Allocate 15-16M bytes: %s\n",
1636 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1637 printf("Hardware Write Allocate Control: %s\n",
1638 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1639 }
1640 }
1641 #endif
1642 /*
1643 * Opteron Rev E shows a bug as in very rare occasions a read memory
1644 * barrier is not performed as expected if it is followed by a
1645 * non-atomic read-modify-write instruction.
1646 * As long as that bug pops up very rarely (intensive machine usage
1647 * on other operating systems generally generates one unexplainable
1648 * crash any 2 months) and as long as a model specific fix would be
1649 * impratical at this stage, print out a warning string if the broken
1650 * model and family are identified.
1651 */
1652 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1653 CPUID_TO_MODEL(cpu_id) <= 0x3f)
1654 printf("WARNING: This architecture revision has known SMP "
1655 "hardware bugs which may cause random instability\n");
1656 }
1657
1658 static void
1659 print_INTEL_info(void)
1660 {
1661 u_int regs[4];
1662 u_int rounds, regnum;
1663 u_int nwaycode, nway;
1664
1665 if (cpu_high >= 2) {
1666 rounds = 0;
1667 do {
1668 do_cpuid(0x2, regs);
1669 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1670 break; /* we have a buggy CPU */
1671
1672 for (regnum = 0; regnum <= 3; ++regnum) {
1673 if (regs[regnum] & (1<<31))
1674 continue;
1675 if (regnum != 0)
1676 print_INTEL_TLB(regs[regnum] & 0xff);
1677 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1678 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1679 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1680 }
1681 } while (--rounds > 0);
1682 }
1683
1684 if (cpu_exthigh >= 0x80000006) {
1685 do_cpuid(0x80000006, regs);
1686 nwaycode = (regs[2] >> 12) & 0x0f;
1687 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1688 nway = 1 << (nwaycode / 2);
1689 else
1690 nway = 0;
1691 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1692 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1693 }
1694 }
1695
1696 static void
1697 print_INTEL_TLB(u_int data)
1698 {
1699 switch (data) {
1700 case 0x0:
1701 case 0x40:
1702 default:
1703 break;
1704 case 0x1:
1705 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1706 break;
1707 case 0x2:
1708 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1709 break;
1710 case 0x3:
1711 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1712 break;
1713 case 0x4:
1714 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1715 break;
1716 case 0x6:
1717 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1718 break;
1719 case 0x8:
1720 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
1721 break;
1722 case 0x9:
1723 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
1724 break;
1725 case 0xa:
1726 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
1727 break;
1728 case 0xb:
1729 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
1730 break;
1731 case 0xc:
1732 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
1733 break;
1734 case 0xd:
1735 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
1736 break;
1737 case 0xe:
1738 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
1739 break;
1740 case 0x1d:
1741 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
1742 break;
1743 case 0x21:
1744 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
1745 break;
1746 case 0x22:
1747 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1748 break;
1749 case 0x23:
1750 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1751 break;
1752 case 0x24:
1753 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
1754 break;
1755 case 0x25:
1756 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1757 break;
1758 case 0x29:
1759 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1760 break;
1761 case 0x2c:
1762 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
1763 break;
1764 case 0x30:
1765 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
1766 break;
1767 case 0x39: /* De-listed in SDM rev. 54 */
1768 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1769 break;
1770 case 0x3b: /* De-listed in SDM rev. 54 */
1771 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
1772 break;
1773 case 0x3c: /* De-listed in SDM rev. 54 */
1774 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1775 break;
1776 case 0x41:
1777 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
1778 break;
1779 case 0x42:
1780 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
1781 break;
1782 case 0x43:
1783 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
1784 break;
1785 case 0x44:
1786 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
1787 break;
1788 case 0x45:
1789 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
1790 break;
1791 case 0x46:
1792 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
1793 break;
1794 case 0x47:
1795 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
1796 break;
1797 case 0x48:
1798 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
1799 break;
1800 case 0x49:
1801 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
1802 CPUID_TO_MODEL(cpu_id) == 0x6)
1803 printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
1804 else
1805 printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
1806 break;
1807 case 0x4a:
1808 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
1809 break;
1810 case 0x4b:
1811 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
1812 break;
1813 case 0x4c:
1814 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
1815 break;
1816 case 0x4d:
1817 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
1818 break;
1819 case 0x4e:
1820 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
1821 break;
1822 case 0x4f:
1823 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
1824 break;
1825 case 0x50:
1826 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
1827 break;
1828 case 0x51:
1829 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
1830 break;
1831 case 0x52:
1832 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
1833 break;
1834 case 0x55:
1835 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
1836 break;
1837 case 0x56:
1838 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
1839 break;
1840 case 0x57:
1841 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
1842 break;
1843 case 0x59:
1844 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
1845 break;
1846 case 0x5a:
1847 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
1848 break;
1849 case 0x5b:
1850 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
1851 break;
1852 case 0x5c:
1853 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
1854 break;
1855 case 0x5d:
1856 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
1857 break;
1858 case 0x60:
1859 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1860 break;
1861 case 0x61:
1862 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
1863 break;
1864 case 0x63:
1865 printf("Data TLB: 1 GByte pages, 4-way set associative, 4 entries\n");
1866 break;
1867 case 0x66:
1868 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1869 break;
1870 case 0x67:
1871 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1872 break;
1873 case 0x68:
1874 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
1875 break;
1876 case 0x70:
1877 printf("Trace cache: 12K-uops, 8-way set associative\n");
1878 break;
1879 case 0x71:
1880 printf("Trace cache: 16K-uops, 8-way set associative\n");
1881 break;
1882 case 0x72:
1883 printf("Trace cache: 32K-uops, 8-way set associative\n");
1884 break;
1885 case 0x76:
1886 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
1887 break;
1888 case 0x78:
1889 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
1890 break;
1891 case 0x79:
1892 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1893 break;
1894 case 0x7a:
1895 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1896 break;
1897 case 0x7b:
1898 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1899 break;
1900 case 0x7c:
1901 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1902 break;
1903 case 0x7d:
1904 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
1905 break;
1906 case 0x7f:
1907 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
1908 break;
1909 case 0x80:
1910 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
1911 break;
1912 case 0x82:
1913 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
1914 break;
1915 case 0x83:
1916 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
1917 break;
1918 case 0x84:
1919 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
1920 break;
1921 case 0x85:
1922 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
1923 break;
1924 case 0x86:
1925 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
1926 break;
1927 case 0x87:
1928 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
1929 break;
1930 case 0xa0:
1931 printf("DTLB: 4k pages, fully associative, 32 entries\n");
1932 break;
1933 case 0xb0:
1934 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
1935 break;
1936 case 0xb1:
1937 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
1938 break;
1939 case 0xb2:
1940 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
1941 break;
1942 case 0xb3:
1943 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
1944 break;
1945 case 0xb4:
1946 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
1947 break;
1948 case 0xb5:
1949 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
1950 break;
1951 case 0xb6:
1952 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
1953 break;
1954 case 0xba:
1955 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
1956 break;
1957 case 0xc0:
1958 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
1959 break;
1960 case 0xc1:
1961 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
1962 break;
1963 case 0xc2:
1964 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
1965 break;
1966 case 0xc3:
1967 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
1968 break;
1969 case 0xca:
1970 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
1971 break;
1972 case 0xd0:
1973 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
1974 break;
1975 case 0xd1:
1976 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
1977 break;
1978 case 0xd2:
1979 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
1980 break;
1981 case 0xd6:
1982 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
1983 break;
1984 case 0xd7:
1985 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
1986 break;
1987 case 0xd8:
1988 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
1989 break;
1990 case 0xdc:
1991 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
1992 break;
1993 case 0xdd:
1994 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
1995 break;
1996 case 0xde:
1997 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
1998 break;
1999 case 0xe2:
2000 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2001 break;
2002 case 0xe3:
2003 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2004 break;
2005 case 0xe4:
2006 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2007 break;
2008 case 0xea:
2009 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2010 break;
2011 case 0xeb:
2012 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2013 break;
2014 case 0xec:
2015 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2016 break;
2017 case 0xf0:
2018 printf("64-Byte prefetching\n");
2019 break;
2020 case 0xf1:
2021 printf("128-Byte prefetching\n");
2022 break;
2023 }
2024 }
2025
2026 static void
2027 print_svm_info(void)
2028 {
2029 u_int features, regs[4];
2030 uint64_t msr;
2031 int comma;
2032
2033 printf("\n SVM: ");
2034 do_cpuid(0x8000000A, regs);
2035 features = regs[3];
2036
2037 msr = rdmsr(MSR_VM_CR);
2038 if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2039 printf("(disabled in BIOS) ");
2040
2041 if (!bootverbose) {
2042 comma = 0;
2043 if (features & (1 << 0)) {
2044 printf("%sNP", comma ? "," : "");
2045 comma = 1;
2046 }
2047 if (features & (1 << 3)) {
2048 printf("%sNRIP", comma ? "," : "");
2049 comma = 1;
2050 }
2051 if (features & (1 << 5)) {
2052 printf("%sVClean", comma ? "," : "");
2053 comma = 1;
2054 }
2055 if (features & (1 << 6)) {
2056 printf("%sAFlush", comma ? "," : "");
2057 comma = 1;
2058 }
2059 if (features & (1 << 7)) {
2060 printf("%sDAssist", comma ? "," : "");
2061 comma = 1;
2062 }
2063 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2064 return;
2065 }
2066
2067 printf("Features=0x%b", features,
2068 "\020"
2069 "\001NP" /* Nested paging */
2070 "\002LbrVirt" /* LBR virtualization */
2071 "\003SVML" /* SVM lock */
2072 "\004NRIPS" /* NRIP save */
2073 "\005TscRateMsr" /* MSR based TSC rate control */
2074 "\006VmcbClean" /* VMCB clean bits */
2075 "\007FlushByAsid" /* Flush by ASID */
2076 "\010DecodeAssist" /* Decode assist */
2077 "\011<b8>"
2078 "\012<b9>"
2079 "\013PauseFilter" /* PAUSE intercept filter */
2080 "\014<b11>"
2081 "\015PauseFilterThreshold" /* PAUSE filter threshold */
2082 "\016AVIC" /* virtual interrupt controller */
2083 );
2084 printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2085 }
2086
2087 #ifdef __i386__
2088 static void
2089 print_transmeta_info(void)
2090 {
2091 u_int regs[4], nreg = 0;
2092
2093 do_cpuid(0x80860000, regs);
2094 nreg = regs[0];
2095 if (nreg >= 0x80860001) {
2096 do_cpuid(0x80860001, regs);
2097 printf(" Processor revision %u.%u.%u.%u\n",
2098 (regs[1] >> 24) & 0xff,
2099 (regs[1] >> 16) & 0xff,
2100 (regs[1] >> 8) & 0xff,
2101 regs[1] & 0xff);
2102 }
2103 if (nreg >= 0x80860002) {
2104 do_cpuid(0x80860002, regs);
2105 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
2106 (regs[1] >> 24) & 0xff,
2107 (regs[1] >> 16) & 0xff,
2108 (regs[1] >> 8) & 0xff,
2109 regs[1] & 0xff,
2110 regs[2]);
2111 }
2112 if (nreg >= 0x80860006) {
2113 char info[65];
2114 do_cpuid(0x80860003, (u_int*) &info[0]);
2115 do_cpuid(0x80860004, (u_int*) &info[16]);
2116 do_cpuid(0x80860005, (u_int*) &info[32]);
2117 do_cpuid(0x80860006, (u_int*) &info[48]);
2118 info[64] = 0;
2119 printf(" %s\n", info);
2120 }
2121 }
2122 #endif
2123
2124 static void
2125 print_via_padlock_info(void)
2126 {
2127 u_int regs[4];
2128
2129 do_cpuid(0xc0000001, regs);
2130 printf("\n VIA Padlock Features=0x%b", regs[3],
2131 "\020"
2132 "\003RNG" /* RNG */
2133 "\007AES" /* ACE */
2134 "\011AES-CTR" /* ACE2 */
2135 "\013SHA1,SHA256" /* PHE */
2136 "\015RSA" /* PMM */
2137 );
2138 }
2139
2140 static uint32_t
2141 vmx_settable(uint64_t basic, int msr, int true_msr)
2142 {
2143 uint64_t val;
2144
2145 if (basic & (1ULL << 55))
2146 val = rdmsr(true_msr);
2147 else
2148 val = rdmsr(msr);
2149
2150 /* Just report the controls that can be set to 1. */
2151 return (val >> 32);
2152 }
2153
2154 static void
2155 print_vmx_info(void)
2156 {
2157 uint64_t basic, msr;
2158 uint32_t entry, exit, mask, pin, proc, proc2;
2159 int comma;
2160
2161 printf("\n VT-x: ");
2162 msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2163 if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2164 printf("(disabled in BIOS) ");
2165 basic = rdmsr(MSR_VMX_BASIC);
2166 pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2167 MSR_VMX_TRUE_PINBASED_CTLS);
2168 proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2169 MSR_VMX_TRUE_PROCBASED_CTLS);
2170 if (proc & PROCBASED_SECONDARY_CONTROLS)
2171 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2172 MSR_VMX_PROCBASED_CTLS2);
2173 else
2174 proc2 = 0;
2175 exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2176 entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2177
2178 if (!bootverbose) {
2179 comma = 0;
2180 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2181 entry & VM_ENTRY_LOAD_PAT) {
2182 printf("%sPAT", comma ? "," : "");
2183 comma = 1;
2184 }
2185 if (proc & PROCBASED_HLT_EXITING) {
2186 printf("%sHLT", comma ? "," : "");
2187 comma = 1;
2188 }
2189 if (proc & PROCBASED_MTF) {
2190 printf("%sMTF", comma ? "," : "");
2191 comma = 1;
2192 }
2193 if (proc & PROCBASED_PAUSE_EXITING) {
2194 printf("%sPAUSE", comma ? "," : "");
2195 comma = 1;
2196 }
2197 if (proc2 & PROCBASED2_ENABLE_EPT) {
2198 printf("%sEPT", comma ? "," : "");
2199 comma = 1;
2200 }
2201 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2202 printf("%sUG", comma ? "," : "");
2203 comma = 1;
2204 }
2205 if (proc2 & PROCBASED2_ENABLE_VPID) {
2206 printf("%sVPID", comma ? "," : "");
2207 comma = 1;
2208 }
2209 if (proc & PROCBASED_USE_TPR_SHADOW &&
2210 proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2211 proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2212 proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2213 proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2214 printf("%sVID", comma ? "," : "");
2215 comma = 1;
2216 if (pin & PINBASED_POSTED_INTERRUPT)
2217 printf(",PostIntr");
2218 }
2219 return;
2220 }
2221
2222 mask = basic >> 32;
2223 printf("Basic Features=0x%b", mask,
2224 "\020"
2225 "\02132PA" /* 32-bit physical addresses */
2226 "\022SMM" /* SMM dual-monitor */
2227 "\027INS/OUTS" /* VM-exit info for INS and OUTS */
2228 "\030TRUE" /* TRUE_CTLS MSRs */
2229 );
2230 printf("\n Pin-Based Controls=0x%b", pin,
2231 "\020"
2232 "\001ExtINT" /* External-interrupt exiting */
2233 "\004NMI" /* NMI exiting */
2234 "\006VNMI" /* Virtual NMIs */
2235 "\007PreTmr" /* Activate VMX-preemption timer */
2236 "\010PostIntr" /* Process posted interrupts */
2237 );
2238 printf("\n Primary Processor Controls=0x%b", proc,
2239 "\020"
2240 "\003INTWIN" /* Interrupt-window exiting */
2241 "\004TSCOff" /* Use TSC offsetting */
2242 "\010HLT" /* HLT exiting */
2243 "\012INVLPG" /* INVLPG exiting */
2244 "\013MWAIT" /* MWAIT exiting */
2245 "\014RDPMC" /* RDPMC exiting */
2246 "\015RDTSC" /* RDTSC exiting */
2247 "\020CR3-LD" /* CR3-load exiting */
2248 "\021CR3-ST" /* CR3-store exiting */
2249 "\024CR8-LD" /* CR8-load exiting */
2250 "\025CR8-ST" /* CR8-store exiting */
2251 "\026TPR" /* Use TPR shadow */
2252 "\027NMIWIN" /* NMI-window exiting */
2253 "\030MOV-DR" /* MOV-DR exiting */
2254 "\031IO" /* Unconditional I/O exiting */
2255 "\032IOmap" /* Use I/O bitmaps */
2256 "\034MTF" /* Monitor trap flag */
2257 "\035MSRmap" /* Use MSR bitmaps */
2258 "\036MONITOR" /* MONITOR exiting */
2259 "\037PAUSE" /* PAUSE exiting */
2260 );
2261 if (proc & PROCBASED_SECONDARY_CONTROLS)
2262 printf("\n Secondary Processor Controls=0x%b", proc2,
2263 "\020"
2264 "\001APIC" /* Virtualize APIC accesses */
2265 "\002EPT" /* Enable EPT */
2266 "\003DT" /* Descriptor-table exiting */
2267 "\004RDTSCP" /* Enable RDTSCP */
2268 "\005x2APIC" /* Virtualize x2APIC mode */
2269 "\006VPID" /* Enable VPID */
2270 "\007WBINVD" /* WBINVD exiting */
2271 "\010UG" /* Unrestricted guest */
2272 "\011APIC-reg" /* APIC-register virtualization */
2273 "\012VID" /* Virtual-interrupt delivery */
2274 "\013PAUSE-loop" /* PAUSE-loop exiting */
2275 "\014RDRAND" /* RDRAND exiting */
2276 "\015INVPCID" /* Enable INVPCID */
2277 "\016VMFUNC" /* Enable VM functions */
2278 "\017VMCS" /* VMCS shadowing */
2279 "\020EPT#VE" /* EPT-violation #VE */
2280 "\021XSAVES" /* Enable XSAVES/XRSTORS */
2281 );
2282 printf("\n Exit Controls=0x%b", mask,
2283 "\020"
2284 "\003DR" /* Save debug controls */
2285 /* Ignore Host address-space size */
2286 "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2287 "\020AckInt" /* Acknowledge interrupt on exit */
2288 "\023PAT-SV" /* Save MSR_PAT */
2289 "\024PAT-LD" /* Load MSR_PAT */
2290 "\025EFER-SV" /* Save MSR_EFER */
2291 "\026EFER-LD" /* Load MSR_EFER */
2292 "\027PTMR-SV" /* Save VMX-preemption timer value */
2293 );
2294 printf("\n Entry Controls=0x%b", mask,
2295 "\020"
2296 "\003DR" /* Save debug controls */
2297 /* Ignore IA-32e mode guest */
2298 /* Ignore Entry to SMM */
2299 /* Ignore Deactivate dual-monitor treatment */
2300 "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2301 "\017PAT" /* Load MSR_PAT */
2302 "\020EFER" /* Load MSR_EFER */
2303 );
2304 if (proc & PROCBASED_SECONDARY_CONTROLS &&
2305 (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2306 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2307 mask = msr;
2308 printf("\n EPT Features=0x%b", mask,
2309 "\020"
2310 "\001XO" /* Execute-only translations */
2311 "\007PW4" /* Page-walk length of 4 */
2312 "\011UC" /* EPT paging-structure mem can be UC */
2313 "\017WB" /* EPT paging-structure mem can be WB */
2314 "\0212M" /* EPT PDE can map a 2-Mbyte page */
2315 "\0221G" /* EPT PDPTE can map a 1-Gbyte page */
2316 "\025INVEPT" /* INVEPT is supported */
2317 "\026AD" /* Accessed and dirty flags for EPT */
2318 "\032single" /* INVEPT single-context type */
2319 "\033all" /* INVEPT all-context type */
2320 );
2321 mask = msr >> 32;
2322 printf("\n VPID Features=0x%b", mask,
2323 "\020"
2324 "\001INVVPID" /* INVVPID is supported */
2325 "\011individual" /* INVVPID individual-address type */
2326 "\012single" /* INVVPID single-context type */
2327 "\013all" /* INVVPID all-context type */
2328 /* INVVPID single-context-retaining-globals type */
2329 "\014single-globals"
2330 );
2331 }
2332 }
2333
2334 static void
2335 print_hypervisor_info(void)
2336 {
2337
2338 if (*hv_vendor)
2339 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2340 }
Cache object: d9eb41f3e40a4608651d5e230c391ec9
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