FreeBSD/Linux Kernel Cross Reference
sys/x86/x86/identcpu.c
1 /*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * Copyright (c) 1997 KATO Takenori.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to Berkeley by
8 * William Jolitz.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * SUCH DAMAGE.
37 *
38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
39 */
40
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD: releng/10.4/sys/x86/x86/identcpu.c 322523 2017-08-14 23:46:10Z jkim $");
43
44 #include "opt_cpu.h"
45
46 #include <sys/param.h>
47 #include <sys/bus.h>
48 #include <sys/cpu.h>
49 #include <sys/eventhandler.h>
50 #include <sys/limits.h>
51 #include <sys/systm.h>
52 #include <sys/kernel.h>
53 #include <sys/sysctl.h>
54 #include <sys/power.h>
55
56 #include <machine/asmacros.h>
57 #include <machine/clock.h>
58 #include <machine/cputypes.h>
59 #include <machine/frame.h>
60 #include <machine/intr_machdep.h>
61 #include <machine/md_var.h>
62 #include <machine/segments.h>
63 #include <machine/specialreg.h>
64
65 #include <amd64/vmm/intel/vmx_controls.h>
66 #include <x86/isa/icu.h>
67 #include <x86/vmware.h>
68
69 #ifdef __i386__
70 #define IDENTBLUE_CYRIX486 0
71 #define IDENTBLUE_IBMCPU 1
72 #define IDENTBLUE_CYRIXM2 2
73
74 static void identifycyrix(void);
75 static void print_transmeta_info(void);
76 #endif
77 static u_int find_cpu_vendor_id(void);
78 static void print_AMD_info(void);
79 static void print_INTEL_info(void);
80 static void print_INTEL_TLB(u_int data);
81 static void print_hypervisor_info(void);
82 static void print_svm_info(void);
83 static void print_via_padlock_info(void);
84 static void print_vmx_info(void);
85
86 int cpu_class;
87 char machine[] = MACHINE;
88
89 #ifdef __amd64__
90 #ifdef SCTL_MASK32
91 extern int adaptive_machine_arch;
92 #endif
93
94 static int
95 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
96 {
97 #ifdef SCTL_MASK32
98 static const char machine32[] = "i386";
99 #endif
100 int error;
101
102 #ifdef SCTL_MASK32
103 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
104 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
105 else
106 #endif
107 error = SYSCTL_OUT(req, machine, sizeof(machine));
108 return (error);
109
110 }
111 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD,
112 NULL, 0, sysctl_hw_machine, "A", "Machine class");
113 #else
114 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
115 machine, 0, "Machine class");
116 #endif
117
118 static char cpu_model[128];
119 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
120 cpu_model, 0, "Machine model");
121
122 static int hw_clockrate;
123 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
124 &hw_clockrate, 0, "CPU instruction clock rate");
125
126 u_int hv_high;
127 char hv_vendor[16];
128 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD, hv_vendor, 0,
129 "Hypervisor vendor");
130
131 static eventhandler_tag tsc_post_tag;
132
133 static char cpu_brand[48];
134
135 #ifdef __i386__
136 #define MAX_BRAND_INDEX 8
137
138 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
139 NULL, /* No brand */
140 "Intel Celeron",
141 "Intel Pentium III",
142 "Intel Pentium III Xeon",
143 NULL,
144 NULL,
145 NULL,
146 NULL,
147 "Intel Pentium 4"
148 };
149 #endif
150
151 static struct {
152 char *cpu_name;
153 int cpu_class;
154 } cpus[] = {
155 #ifdef __i386__
156 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
157 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
158 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
159 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
160 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
161 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
162 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
163 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
164 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
165 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
166 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
167 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
168 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
169 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
170 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
171 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
172 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
173 #else
174 { "Clawhammer", CPUCLASS_K8 }, /* CPU_CLAWHAMMER */
175 { "Sledgehammer", CPUCLASS_K8 }, /* CPU_SLEDGEHAMMER */
176 #endif
177 };
178
179 static struct {
180 char *vendor;
181 u_int vendor_id;
182 } cpu_vendors[] = {
183 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */
184 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */
185 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */
186 #ifdef __i386__
187 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */
188 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */
189 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
190 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */
191 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */
192 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */
193 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */
194 #if 0
195 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
196 { "TransmetaCPU", CPU_VENDOR_TRANSMETA },
197 #endif
198 #endif
199 };
200
201 void
202 printcpuinfo(void)
203 {
204 u_int regs[4], i;
205 char *brand;
206
207 cpu_class = cpus[cpu].cpu_class;
208 printf("CPU: ");
209 strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
210
211 /* Check for extended CPUID information and a processor name. */
212 if (cpu_exthigh >= 0x80000004) {
213 brand = cpu_brand;
214 for (i = 0x80000002; i < 0x80000005; i++) {
215 do_cpuid(i, regs);
216 memcpy(brand, regs, sizeof(regs));
217 brand += sizeof(regs);
218 }
219 }
220
221 switch (cpu_vendor_id) {
222 case CPU_VENDOR_INTEL:
223 #ifdef __i386__
224 if ((cpu_id & 0xf00) > 0x300) {
225 u_int brand_index;
226
227 cpu_model[0] = '\0';
228
229 switch (cpu_id & 0x3000) {
230 case 0x1000:
231 strcpy(cpu_model, "Overdrive ");
232 break;
233 case 0x2000:
234 strcpy(cpu_model, "Dual ");
235 break;
236 }
237
238 switch (cpu_id & 0xf00) {
239 case 0x400:
240 strcat(cpu_model, "i486 ");
241 /* Check the particular flavor of 486 */
242 switch (cpu_id & 0xf0) {
243 case 0x00:
244 case 0x10:
245 strcat(cpu_model, "DX");
246 break;
247 case 0x20:
248 strcat(cpu_model, "SX");
249 break;
250 case 0x30:
251 strcat(cpu_model, "DX2");
252 break;
253 case 0x40:
254 strcat(cpu_model, "SL");
255 break;
256 case 0x50:
257 strcat(cpu_model, "SX2");
258 break;
259 case 0x70:
260 strcat(cpu_model,
261 "DX2 Write-Back Enhanced");
262 break;
263 case 0x80:
264 strcat(cpu_model, "DX4");
265 break;
266 }
267 break;
268 case 0x500:
269 /* Check the particular flavor of 586 */
270 strcat(cpu_model, "Pentium");
271 switch (cpu_id & 0xf0) {
272 case 0x00:
273 strcat(cpu_model, " A-step");
274 break;
275 case 0x10:
276 strcat(cpu_model, "/P5");
277 break;
278 case 0x20:
279 strcat(cpu_model, "/P54C");
280 break;
281 case 0x30:
282 strcat(cpu_model, "/P24T");
283 break;
284 case 0x40:
285 strcat(cpu_model, "/P55C");
286 break;
287 case 0x70:
288 strcat(cpu_model, "/P54C");
289 break;
290 case 0x80:
291 strcat(cpu_model, "/P55C (quarter-micron)");
292 break;
293 default:
294 /* nothing */
295 break;
296 }
297 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
298 /*
299 * XXX - If/when Intel fixes the bug, this
300 * should also check the version of the
301 * CPU, not just that it's a Pentium.
302 */
303 has_f00f_bug = 1;
304 #endif
305 break;
306 case 0x600:
307 /* Check the particular flavor of 686 */
308 switch (cpu_id & 0xf0) {
309 case 0x00:
310 strcat(cpu_model, "Pentium Pro A-step");
311 break;
312 case 0x10:
313 strcat(cpu_model, "Pentium Pro");
314 break;
315 case 0x30:
316 case 0x50:
317 case 0x60:
318 strcat(cpu_model,
319 "Pentium II/Pentium II Xeon/Celeron");
320 cpu = CPU_PII;
321 break;
322 case 0x70:
323 case 0x80:
324 case 0xa0:
325 case 0xb0:
326 strcat(cpu_model,
327 "Pentium III/Pentium III Xeon/Celeron");
328 cpu = CPU_PIII;
329 break;
330 default:
331 strcat(cpu_model, "Unknown 80686");
332 break;
333 }
334 break;
335 case 0xf00:
336 strcat(cpu_model, "Pentium 4");
337 cpu = CPU_P4;
338 break;
339 default:
340 strcat(cpu_model, "unknown");
341 break;
342 }
343
344 /*
345 * If we didn't get a brand name from the extended
346 * CPUID, try to look it up in the brand table.
347 */
348 if (cpu_high > 0 && *cpu_brand == '\0') {
349 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
350 if (brand_index <= MAX_BRAND_INDEX &&
351 cpu_brandtable[brand_index] != NULL)
352 strcpy(cpu_brand,
353 cpu_brandtable[brand_index]);
354 }
355 }
356 #else
357 /* Please make up your mind folks! */
358 strcat(cpu_model, "EM64T");
359 #endif
360 break;
361 case CPU_VENDOR_AMD:
362 /*
363 * Values taken from AMD Processor Recognition
364 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
365 * (also describes ``Features'' encodings.
366 */
367 strcpy(cpu_model, "AMD ");
368 #ifdef __i386__
369 switch (cpu_id & 0xFF0) {
370 case 0x410:
371 strcat(cpu_model, "Standard Am486DX");
372 break;
373 case 0x430:
374 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
375 break;
376 case 0x470:
377 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
378 break;
379 case 0x480:
380 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
381 break;
382 case 0x490:
383 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
384 break;
385 case 0x4E0:
386 strcat(cpu_model, "Am5x86 Write-Through");
387 break;
388 case 0x4F0:
389 strcat(cpu_model, "Am5x86 Write-Back");
390 break;
391 case 0x500:
392 strcat(cpu_model, "K5 model 0");
393 break;
394 case 0x510:
395 strcat(cpu_model, "K5 model 1");
396 break;
397 case 0x520:
398 strcat(cpu_model, "K5 PR166 (model 2)");
399 break;
400 case 0x530:
401 strcat(cpu_model, "K5 PR200 (model 3)");
402 break;
403 case 0x560:
404 strcat(cpu_model, "K6");
405 break;
406 case 0x570:
407 strcat(cpu_model, "K6 266 (model 1)");
408 break;
409 case 0x580:
410 strcat(cpu_model, "K6-2");
411 break;
412 case 0x590:
413 strcat(cpu_model, "K6-III");
414 break;
415 case 0x5a0:
416 strcat(cpu_model, "Geode LX");
417 break;
418 default:
419 strcat(cpu_model, "Unknown");
420 break;
421 }
422 #else
423 if ((cpu_id & 0xf00) == 0xf00)
424 strcat(cpu_model, "AMD64 Processor");
425 else
426 strcat(cpu_model, "Unknown");
427 #endif
428 break;
429 #ifdef __i386__
430 case CPU_VENDOR_CYRIX:
431 strcpy(cpu_model, "Cyrix ");
432 switch (cpu_id & 0xff0) {
433 case 0x440:
434 strcat(cpu_model, "MediaGX");
435 break;
436 case 0x520:
437 strcat(cpu_model, "6x86");
438 break;
439 case 0x540:
440 cpu_class = CPUCLASS_586;
441 strcat(cpu_model, "GXm");
442 break;
443 case 0x600:
444 strcat(cpu_model, "6x86MX");
445 break;
446 default:
447 /*
448 * Even though CPU supports the cpuid
449 * instruction, it can be disabled.
450 * Therefore, this routine supports all Cyrix
451 * CPUs.
452 */
453 switch (cyrix_did & 0xf0) {
454 case 0x00:
455 switch (cyrix_did & 0x0f) {
456 case 0x00:
457 strcat(cpu_model, "486SLC");
458 break;
459 case 0x01:
460 strcat(cpu_model, "486DLC");
461 break;
462 case 0x02:
463 strcat(cpu_model, "486SLC2");
464 break;
465 case 0x03:
466 strcat(cpu_model, "486DLC2");
467 break;
468 case 0x04:
469 strcat(cpu_model, "486SRx");
470 break;
471 case 0x05:
472 strcat(cpu_model, "486DRx");
473 break;
474 case 0x06:
475 strcat(cpu_model, "486SRx2");
476 break;
477 case 0x07:
478 strcat(cpu_model, "486DRx2");
479 break;
480 case 0x08:
481 strcat(cpu_model, "486SRu");
482 break;
483 case 0x09:
484 strcat(cpu_model, "486DRu");
485 break;
486 case 0x0a:
487 strcat(cpu_model, "486SRu2");
488 break;
489 case 0x0b:
490 strcat(cpu_model, "486DRu2");
491 break;
492 default:
493 strcat(cpu_model, "Unknown");
494 break;
495 }
496 break;
497 case 0x10:
498 switch (cyrix_did & 0x0f) {
499 case 0x00:
500 strcat(cpu_model, "486S");
501 break;
502 case 0x01:
503 strcat(cpu_model, "486S2");
504 break;
505 case 0x02:
506 strcat(cpu_model, "486Se");
507 break;
508 case 0x03:
509 strcat(cpu_model, "486S2e");
510 break;
511 case 0x0a:
512 strcat(cpu_model, "486DX");
513 break;
514 case 0x0b:
515 strcat(cpu_model, "486DX2");
516 break;
517 case 0x0f:
518 strcat(cpu_model, "486DX4");
519 break;
520 default:
521 strcat(cpu_model, "Unknown");
522 break;
523 }
524 break;
525 case 0x20:
526 if ((cyrix_did & 0x0f) < 8)
527 strcat(cpu_model, "6x86"); /* Where did you get it? */
528 else
529 strcat(cpu_model, "5x86");
530 break;
531 case 0x30:
532 strcat(cpu_model, "6x86");
533 break;
534 case 0x40:
535 if ((cyrix_did & 0xf000) == 0x3000) {
536 cpu_class = CPUCLASS_586;
537 strcat(cpu_model, "GXm");
538 } else
539 strcat(cpu_model, "MediaGX");
540 break;
541 case 0x50:
542 strcat(cpu_model, "6x86MX");
543 break;
544 case 0xf0:
545 switch (cyrix_did & 0x0f) {
546 case 0x0d:
547 strcat(cpu_model, "Overdrive CPU");
548 break;
549 case 0x0e:
550 strcpy(cpu_model, "Texas Instruments 486SXL");
551 break;
552 case 0x0f:
553 strcat(cpu_model, "486SLC/DLC");
554 break;
555 default:
556 strcat(cpu_model, "Unknown");
557 break;
558 }
559 break;
560 default:
561 strcat(cpu_model, "Unknown");
562 break;
563 }
564 break;
565 }
566 break;
567 case CPU_VENDOR_RISE:
568 strcpy(cpu_model, "Rise ");
569 switch (cpu_id & 0xff0) {
570 case 0x500: /* 6401 and 6441 (Kirin) */
571 case 0x520: /* 6510 (Lynx) */
572 strcat(cpu_model, "mP6");
573 break;
574 default:
575 strcat(cpu_model, "Unknown");
576 }
577 break;
578 #endif
579 case CPU_VENDOR_CENTAUR:
580 #ifdef __i386__
581 switch (cpu_id & 0xff0) {
582 case 0x540:
583 strcpy(cpu_model, "IDT WinChip C6");
584 break;
585 case 0x580:
586 strcpy(cpu_model, "IDT WinChip 2");
587 break;
588 case 0x590:
589 strcpy(cpu_model, "IDT WinChip 3");
590 break;
591 case 0x660:
592 strcpy(cpu_model, "VIA C3 Samuel");
593 break;
594 case 0x670:
595 if (cpu_id & 0x8)
596 strcpy(cpu_model, "VIA C3 Ezra");
597 else
598 strcpy(cpu_model, "VIA C3 Samuel 2");
599 break;
600 case 0x680:
601 strcpy(cpu_model, "VIA C3 Ezra-T");
602 break;
603 case 0x690:
604 strcpy(cpu_model, "VIA C3 Nehemiah");
605 break;
606 case 0x6a0:
607 case 0x6d0:
608 strcpy(cpu_model, "VIA C7 Esther");
609 break;
610 case 0x6f0:
611 strcpy(cpu_model, "VIA Nano");
612 break;
613 default:
614 strcpy(cpu_model, "VIA/IDT Unknown");
615 }
616 #else
617 strcpy(cpu_model, "VIA ");
618 if ((cpu_id & 0xff0) == 0x6f0)
619 strcat(cpu_model, "Nano Processor");
620 else
621 strcat(cpu_model, "Unknown");
622 #endif
623 break;
624 #ifdef __i386__
625 case CPU_VENDOR_IBM:
626 strcpy(cpu_model, "Blue Lightning CPU");
627 break;
628 case CPU_VENDOR_NSC:
629 switch (cpu_id & 0xff0) {
630 case 0x540:
631 strcpy(cpu_model, "Geode SC1100");
632 cpu = CPU_GEODE1100;
633 break;
634 default:
635 strcpy(cpu_model, "Geode/NSC unknown");
636 break;
637 }
638 break;
639 #endif
640 default:
641 strcat(cpu_model, "Unknown");
642 break;
643 }
644
645 /*
646 * Replace cpu_model with cpu_brand minus leading spaces if
647 * we have one.
648 */
649 brand = cpu_brand;
650 while (*brand == ' ')
651 ++brand;
652 if (*brand != '\0')
653 strcpy(cpu_model, brand);
654
655 printf("%s (", cpu_model);
656 if (tsc_freq != 0) {
657 hw_clockrate = (tsc_freq + 5000) / 1000000;
658 printf("%jd.%02d-MHz ",
659 (intmax_t)(tsc_freq + 4999) / 1000000,
660 (u_int)((tsc_freq + 4999) / 10000) % 100);
661 }
662 switch(cpu_class) {
663 #ifdef __i386__
664 case CPUCLASS_286:
665 printf("286");
666 break;
667 case CPUCLASS_386:
668 printf("386");
669 break;
670 #if defined(I486_CPU)
671 case CPUCLASS_486:
672 printf("486");
673 break;
674 #endif
675 #if defined(I586_CPU)
676 case CPUCLASS_586:
677 printf("586");
678 break;
679 #endif
680 #if defined(I686_CPU)
681 case CPUCLASS_686:
682 printf("686");
683 break;
684 #endif
685 #else
686 case CPUCLASS_K8:
687 printf("K8");
688 break;
689 #endif
690 default:
691 printf("Unknown"); /* will panic below... */
692 }
693 printf("-class CPU)\n");
694 if (*cpu_vendor)
695 printf(" Origin=\"%s\"", cpu_vendor);
696 if (cpu_id)
697 printf(" Id=0x%x", cpu_id);
698
699 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
700 cpu_vendor_id == CPU_VENDOR_AMD ||
701 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
702 #ifdef __i386__
703 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
704 cpu_vendor_id == CPU_VENDOR_RISE ||
705 cpu_vendor_id == CPU_VENDOR_NSC ||
706 (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
707 #endif
708 0) {
709 printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id));
710 printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id));
711 printf(" Stepping=%u", cpu_id & CPUID_STEPPING);
712 #ifdef __i386__
713 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
714 printf("\n DIR=0x%04x", cyrix_did);
715 #endif
716
717 /*
718 * AMD CPUID Specification
719 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
720 *
721 * Intel Processor Identification and CPUID Instruction
722 * http://www.intel.com/assets/pdf/appnote/241618.pdf
723 */
724 if (cpu_high > 0) {
725
726 /*
727 * Here we should probably set up flags indicating
728 * whether or not various features are available.
729 * The interesting ones are probably VME, PSE, PAE,
730 * and PGE. The code already assumes without bothering
731 * to check that all CPUs >= Pentium have a TSC and
732 * MSRs.
733 */
734 printf("\n Features=0x%b", cpu_feature,
735 "\020"
736 "\001FPU" /* Integral FPU */
737 "\002VME" /* Extended VM86 mode support */
738 "\003DE" /* Debugging Extensions (CR4.DE) */
739 "\004PSE" /* 4MByte page tables */
740 "\005TSC" /* Timestamp counter */
741 "\006MSR" /* Machine specific registers */
742 "\007PAE" /* Physical address extension */
743 "\010MCE" /* Machine Check support */
744 "\011CX8" /* CMPEXCH8 instruction */
745 "\012APIC" /* SMP local APIC */
746 "\013oldMTRR" /* Previous implementation of MTRR */
747 "\014SEP" /* Fast System Call */
748 "\015MTRR" /* Memory Type Range Registers */
749 "\016PGE" /* PG_G (global bit) support */
750 "\017MCA" /* Machine Check Architecture */
751 "\020CMOV" /* CMOV instruction */
752 "\021PAT" /* Page attributes table */
753 "\022PSE36" /* 36 bit address space support */
754 "\023PN" /* Processor Serial number */
755 "\024CLFLUSH" /* Has the CLFLUSH instruction */
756 "\025<b20>"
757 "\026DTS" /* Debug Trace Store */
758 "\027ACPI" /* ACPI support */
759 "\030MMX" /* MMX instructions */
760 "\031FXSR" /* FXSAVE/FXRSTOR */
761 "\032SSE" /* Streaming SIMD Extensions */
762 "\033SSE2" /* Streaming SIMD Extensions #2 */
763 "\034SS" /* Self snoop */
764 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
765 "\036TM" /* Thermal Monitor clock slowdown */
766 "\037IA64" /* CPU can execute IA64 instructions */
767 "\040PBE" /* Pending Break Enable */
768 );
769
770 if (cpu_feature2 != 0) {
771 printf("\n Features2=0x%b", cpu_feature2,
772 "\020"
773 "\001SSE3" /* SSE3 */
774 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
775 "\003DTES64" /* 64-bit Debug Trace */
776 "\004MON" /* MONITOR/MWAIT Instructions */
777 "\005DS_CPL" /* CPL Qualified Debug Store */
778 "\006VMX" /* Virtual Machine Extensions */
779 "\007SMX" /* Safer Mode Extensions */
780 "\010EST" /* Enhanced SpeedStep */
781 "\011TM2" /* Thermal Monitor 2 */
782 "\012SSSE3" /* SSSE3 */
783 "\013CNXT-ID" /* L1 context ID available */
784 "\014SDBG" /* IA32 silicon debug */
785 "\015FMA" /* Fused Multiply Add */
786 "\016CX16" /* CMPXCHG16B Instruction */
787 "\017xTPR" /* Send Task Priority Messages*/
788 "\020PDCM" /* Perf/Debug Capability MSR */
789 "\021<b16>"
790 "\022PCID" /* Process-context Identifiers*/
791 "\023DCA" /* Direct Cache Access */
792 "\024SSE4.1" /* SSE 4.1 */
793 "\025SSE4.2" /* SSE 4.2 */
794 "\026x2APIC" /* xAPIC Extensions */
795 "\027MOVBE" /* MOVBE Instruction */
796 "\030POPCNT" /* POPCNT Instruction */
797 "\031TSCDLT" /* TSC-Deadline Timer */
798 "\032AESNI" /* AES Crypto */
799 "\033XSAVE" /* XSAVE/XRSTOR States */
800 "\034OSXSAVE" /* OS-Enabled State Management*/
801 "\035AVX" /* Advanced Vector Extensions */
802 "\036F16C" /* Half-precision conversions */
803 "\037RDRAND" /* RDRAND Instruction */
804 "\040HV" /* Hypervisor */
805 );
806 }
807
808 if (amd_feature != 0) {
809 printf("\n AMD Features=0x%b", amd_feature,
810 "\020" /* in hex */
811 "\001<s0>" /* Same */
812 "\002<s1>" /* Same */
813 "\003<s2>" /* Same */
814 "\004<s3>" /* Same */
815 "\005<s4>" /* Same */
816 "\006<s5>" /* Same */
817 "\007<s6>" /* Same */
818 "\010<s7>" /* Same */
819 "\011<s8>" /* Same */
820 "\012<s9>" /* Same */
821 "\013<b10>" /* Undefined */
822 "\014SYSCALL" /* Have SYSCALL/SYSRET */
823 "\015<s12>" /* Same */
824 "\016<s13>" /* Same */
825 "\017<s14>" /* Same */
826 "\020<s15>" /* Same */
827 "\021<s16>" /* Same */
828 "\022<s17>" /* Same */
829 "\023<b18>" /* Reserved, unknown */
830 "\024MP" /* Multiprocessor Capable */
831 "\025NX" /* Has EFER.NXE, NX */
832 "\026<b21>" /* Undefined */
833 "\027MMX+" /* AMD MMX Extensions */
834 "\030<s23>" /* Same */
835 "\031<s24>" /* Same */
836 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */
837 "\033Page1GB" /* 1-GB large page support */
838 "\034RDTSCP" /* RDTSCP */
839 "\035<b28>" /* Undefined */
840 "\036LM" /* 64 bit long mode */
841 "\0373DNow!+" /* AMD 3DNow! Extensions */
842 "\0403DNow!" /* AMD 3DNow! */
843 );
844 }
845
846 if (amd_feature2 != 0) {
847 printf("\n AMD Features2=0x%b", amd_feature2,
848 "\020"
849 "\001LAHF" /* LAHF/SAHF in long mode */
850 "\002CMP" /* CMP legacy */
851 "\003SVM" /* Secure Virtual Mode */
852 "\004ExtAPIC" /* Extended APIC register */
853 "\005CR8" /* CR8 in legacy mode */
854 "\006ABM" /* LZCNT instruction */
855 "\007SSE4A" /* SSE4A */
856 "\010MAS" /* Misaligned SSE mode */
857 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
858 "\012OSVW" /* OS visible workaround */
859 "\013IBS" /* Instruction based sampling */
860 "\014XOP" /* XOP extended instructions */
861 "\015SKINIT" /* SKINIT/STGI */
862 "\016WDT" /* Watchdog timer */
863 "\017<b14>"
864 "\020LWP" /* Lightweight Profiling */
865 "\021FMA4" /* 4-operand FMA instructions */
866 "\022TCE" /* Translation Cache Extension */
867 "\023<b18>"
868 "\024NodeId" /* NodeId MSR support */
869 "\025<b20>"
870 "\026TBM" /* Trailing Bit Manipulation */
871 "\027Topology" /* Topology Extensions */
872 "\030PCXC" /* Core perf count */
873 "\031PNXC" /* NB perf count */
874 "\032<b25>"
875 "\033DBE" /* Data Breakpoint extension */
876 "\034PTSC" /* Performance TSC */
877 "\035PL2I" /* L2I perf count */
878 "\036MWAITX" /* MONITORX/MWAITX instructions */
879 "\037<b30>"
880 "\040<b31>"
881 );
882 }
883
884 if (cpu_stdext_feature != 0) {
885 printf("\n Structured Extended Features=0x%b",
886 cpu_stdext_feature,
887 "\020"
888 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
889 "\001FSGSBASE"
890 "\002TSCADJ"
891 "\003SGX"
892 /* Bit Manipulation Instructions */
893 "\004BMI1"
894 /* Hardware Lock Elision */
895 "\005HLE"
896 /* Advanced Vector Instructions 2 */
897 "\006AVX2"
898 /* FDP_EXCPTN_ONLY */
899 "\007FDPEXC"
900 /* Supervisor Mode Execution Prot. */
901 "\010SMEP"
902 /* Bit Manipulation Instructions */
903 "\011BMI2"
904 "\012ERMS"
905 /* Invalidate Processor Context ID */
906 "\013INVPCID"
907 /* Restricted Transactional Memory */
908 "\014RTM"
909 "\015PQM"
910 "\016NFPUSG"
911 /* Intel Memory Protection Extensions */
912 "\017MPX"
913 "\020PQE"
914 /* AVX512 Foundation */
915 "\021AVX512F"
916 /* Enhanced NRBG */
917 "\023RDSEED"
918 /* ADCX + ADOX */
919 "\024ADX"
920 /* Supervisor Mode Access Prevention */
921 "\025SMAP"
922 "\030CLFLUSHOPT"
923 "\032PROCTRACE"
924 "\033AVX512PF"
925 "\034AVX512ER"
926 "\035AVX512CD"
927 "\036SHA"
928 );
929 }
930
931 if (cpu_stdext_feature2 != 0) {
932 printf("\n Structured Extended Features2=0x%b",
933 cpu_stdext_feature2,
934 "\020"
935 "\001PREFETCHWT1"
936 "\003UMIP"
937 "\004PKU"
938 "\005OSPKE"
939 "\027RDPID"
940 "\037SGXLC"
941 );
942 }
943
944 if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
945 cpuid_count(0xd, 0x1, regs);
946 if (regs[0] != 0) {
947 printf("\n XSAVE Features=0x%b",
948 regs[0],
949 "\020"
950 "\001XSAVEOPT"
951 "\002XSAVEC"
952 "\003XINUSE"
953 "\004XSAVES");
954 }
955 }
956
957 if (via_feature_rng != 0 || via_feature_xcrypt != 0)
958 print_via_padlock_info();
959
960 if (cpu_feature2 & CPUID2_VMX)
961 print_vmx_info();
962
963 if (amd_feature2 & AMDID2_SVM)
964 print_svm_info();
965
966 if ((cpu_feature & CPUID_HTT) &&
967 cpu_vendor_id == CPU_VENDOR_AMD)
968 cpu_feature &= ~CPUID_HTT;
969
970 /*
971 * If this CPU supports P-state invariant TSC then
972 * mention the capability.
973 */
974 if (tsc_is_invariant) {
975 printf("\n TSC: P-state invariant");
976 if (tsc_perf_stat)
977 printf(", performance statistics");
978 }
979 }
980 #ifdef __i386__
981 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
982 printf(" DIR=0x%04x", cyrix_did);
983 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
984 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
985 #ifndef CYRIX_CACHE_REALLY_WORKS
986 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
987 printf("\n CPU cache: write-through mode");
988 #endif
989 #endif
990 }
991
992 /* Avoid ugly blank lines: only print newline when we have to. */
993 if (*cpu_vendor || cpu_id)
994 printf("\n");
995
996 if (bootverbose) {
997 if (cpu_vendor_id == CPU_VENDOR_AMD)
998 print_AMD_info();
999 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1000 print_INTEL_info();
1001 #ifdef __i386__
1002 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1003 print_transmeta_info();
1004 #endif
1005 }
1006
1007 print_hypervisor_info();
1008 }
1009
1010 void
1011 panicifcpuunsupported(void)
1012 {
1013
1014 #ifdef __i386__
1015 #if !defined(lint)
1016 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1017 #error This kernel is not configured for one of the supported CPUs
1018 #endif
1019 #else /* lint */
1020 #endif /* lint */
1021 #else /* __amd64__ */
1022 #ifndef HAMMER
1023 #error "You need to specify a cpu type"
1024 #endif
1025 #endif
1026 /*
1027 * Now that we have told the user what they have,
1028 * let them know if that machine type isn't configured.
1029 */
1030 switch (cpu_class) {
1031 #ifdef __i386__
1032 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
1033 case CPUCLASS_386:
1034 #if !defined(I486_CPU)
1035 case CPUCLASS_486:
1036 #endif
1037 #if !defined(I586_CPU)
1038 case CPUCLASS_586:
1039 #endif
1040 #if !defined(I686_CPU)
1041 case CPUCLASS_686:
1042 #endif
1043 #else /* __amd64__ */
1044 case CPUCLASS_X86:
1045 #ifndef HAMMER
1046 case CPUCLASS_K8:
1047 #endif
1048 #endif
1049 panic("CPU class not configured");
1050 default:
1051 break;
1052 }
1053 }
1054
1055 #ifdef __i386__
1056 static volatile u_int trap_by_rdmsr;
1057
1058 /*
1059 * Special exception 6 handler.
1060 * The rdmsr instruction generates invalid opcodes fault on 486-class
1061 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
1062 * function identblue() when this handler is called. Stacked eip should
1063 * be advanced.
1064 */
1065 inthand_t bluetrap6;
1066 #ifdef __GNUCLIKE_ASM
1067 __asm
1068 (" \n\
1069 .text \n\
1070 .p2align 2,0x90 \n\
1071 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\
1072 " __XSTRING(CNAME(bluetrap6)) ": \n\
1073 ss \n\
1074 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1075 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1076 iret \n\
1077 ");
1078 #endif
1079
1080 /*
1081 * Special exception 13 handler.
1082 * Accessing non-existent MSR generates general protection fault.
1083 */
1084 inthand_t bluetrap13;
1085 #ifdef __GNUCLIKE_ASM
1086 __asm
1087 (" \n\
1088 .text \n\
1089 .p2align 2,0x90 \n\
1090 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\
1091 " __XSTRING(CNAME(bluetrap13)) ": \n\
1092 ss \n\
1093 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1094 popl %eax /* discard error code */ \n\
1095 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1096 iret \n\
1097 ");
1098 #endif
1099
1100 /*
1101 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1102 * support cpuid instruction. This function should be called after
1103 * loading interrupt descriptor table register.
1104 *
1105 * I don't like this method that handles fault, but I couldn't get
1106 * information for any other methods. Does blue giant know?
1107 */
1108 static int
1109 identblue(void)
1110 {
1111
1112 trap_by_rdmsr = 0;
1113
1114 /*
1115 * Cyrix 486-class CPU does not support rdmsr instruction.
1116 * The rdmsr instruction generates invalid opcode fault, and exception
1117 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
1118 * bluetrap6() set the magic number to trap_by_rdmsr.
1119 */
1120 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1121 GSEL(GCODE_SEL, SEL_KPL));
1122
1123 /*
1124 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1125 * In this case, rdmsr generates general protection fault, and
1126 * exception will be trapped by bluetrap13().
1127 */
1128 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1129 GSEL(GCODE_SEL, SEL_KPL));
1130
1131 rdmsr(0x1002); /* Cyrix CPU generates fault. */
1132
1133 if (trap_by_rdmsr == 0xa8c1d)
1134 return IDENTBLUE_CYRIX486;
1135 else if (trap_by_rdmsr == 0xa89c4)
1136 return IDENTBLUE_CYRIXM2;
1137 return IDENTBLUE_IBMCPU;
1138 }
1139
1140
1141 /*
1142 * identifycyrix() set lower 16 bits of cyrix_did as follows:
1143 *
1144 * F E D C B A 9 8 7 6 5 4 3 2 1 0
1145 * +-------+-------+---------------+
1146 * | SID | RID | Device ID |
1147 * | (DIR 1) | (DIR 0) |
1148 * +-------+-------+---------------+
1149 */
1150 static void
1151 identifycyrix(void)
1152 {
1153 register_t saveintr;
1154 int ccr2_test = 0, dir_test = 0;
1155 u_char ccr2, ccr3;
1156
1157 saveintr = intr_disable();
1158
1159 ccr2 = read_cyrix_reg(CCR2);
1160 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1161 read_cyrix_reg(CCR2);
1162 if (read_cyrix_reg(CCR2) != ccr2)
1163 ccr2_test = 1;
1164 write_cyrix_reg(CCR2, ccr2);
1165
1166 ccr3 = read_cyrix_reg(CCR3);
1167 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1168 read_cyrix_reg(CCR3);
1169 if (read_cyrix_reg(CCR3) != ccr3)
1170 dir_test = 1; /* CPU supports DIRs. */
1171 write_cyrix_reg(CCR3, ccr3);
1172
1173 if (dir_test) {
1174 /* Device ID registers are available. */
1175 cyrix_did = read_cyrix_reg(DIR1) << 8;
1176 cyrix_did += read_cyrix_reg(DIR0);
1177 } else if (ccr2_test)
1178 cyrix_did = 0x0010; /* 486S A-step */
1179 else
1180 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
1181
1182 intr_restore(saveintr);
1183 }
1184 #endif
1185
1186 /* Update TSC freq with the value indicated by the caller. */
1187 static void
1188 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1189 {
1190
1191 /* If there was an error during the transition, don't do anything. */
1192 if (status != 0)
1193 return;
1194
1195 /* Total setting for this level gives the new frequency in MHz. */
1196 hw_clockrate = level->total_set.freq;
1197 }
1198
1199 static void
1200 hook_tsc_freq(void *arg __unused)
1201 {
1202
1203 if (tsc_is_invariant)
1204 return;
1205
1206 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1207 tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1208 }
1209
1210 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1211
1212 #ifndef XEN
1213 static const char *const vm_bnames[] = {
1214 "QEMU", /* QEMU */
1215 "Plex86", /* Plex86 */
1216 "Bochs", /* Bochs */
1217 "Xen", /* Xen */
1218 "BHYVE", /* bhyve */
1219 "Seabios", /* KVM */
1220 NULL
1221 };
1222
1223 static const char *const vm_pnames[] = {
1224 "VMware Virtual Platform", /* VMWare VM */
1225 "Virtual Machine", /* Microsoft VirtualPC */
1226 "VirtualBox", /* Sun xVM VirtualBox */
1227 "Parallels Virtual Platform", /* Parallels VM */
1228 "KVM", /* KVM */
1229 NULL
1230 };
1231
1232 void
1233 identify_hypervisor(void)
1234 {
1235 u_int regs[4];
1236 char *p;
1237 int i;
1238
1239 /*
1240 * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1241 * http://lkml.org/lkml/2008/10/1/246
1242 *
1243 * KB1009458: Mechanisms to determine if software is running in
1244 * a VMware virtual machine
1245 * http://kb.vmware.com/kb/1009458
1246 */
1247 if (cpu_feature2 & CPUID2_HV) {
1248 vm_guest = VM_GUEST_VM;
1249 do_cpuid(0x40000000, regs);
1250 if (regs[0] >= 0x40000000) {
1251 hv_high = regs[0];
1252 ((u_int *)&hv_vendor)[0] = regs[1];
1253 ((u_int *)&hv_vendor)[1] = regs[2];
1254 ((u_int *)&hv_vendor)[2] = regs[3];
1255 hv_vendor[12] = '\0';
1256 if (strcmp(hv_vendor, "VMwareVMware") == 0)
1257 vm_guest = VM_GUEST_VMWARE;
1258 else if (strcmp(hv_vendor, "Microsoft Hv") == 0)
1259 vm_guest = VM_GUEST_HV;
1260 }
1261 return;
1262 }
1263
1264 /*
1265 * Examine SMBIOS strings for older hypervisors.
1266 */
1267 p = getenv("smbios.system.serial");
1268 if (p != NULL) {
1269 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1270 vmware_hvcall(VMW_HVCMD_GETVERSION, regs);
1271 if (regs[1] == VMW_HVMAGIC) {
1272 vm_guest = VM_GUEST_VMWARE;
1273 freeenv(p);
1274 return;
1275 }
1276 }
1277 freeenv(p);
1278 }
1279
1280 /*
1281 * XXX: Some of these entries may not be needed since they were
1282 * added to FreeBSD before the checks above.
1283 */
1284 p = getenv("smbios.bios.vendor");
1285 if (p != NULL) {
1286 for (i = 0; vm_bnames[i] != NULL; i++)
1287 if (strcmp(p, vm_bnames[i]) == 0) {
1288 vm_guest = VM_GUEST_VM;
1289 freeenv(p);
1290 return;
1291 }
1292 freeenv(p);
1293 }
1294 p = getenv("smbios.system.product");
1295 if (p != NULL) {
1296 for (i = 0; vm_pnames[i] != NULL; i++)
1297 if (strcmp(p, vm_pnames[i]) == 0) {
1298 vm_guest = VM_GUEST_VM;
1299 freeenv(p);
1300 return;
1301 }
1302 freeenv(p);
1303 }
1304 }
1305 #endif
1306
1307 bool
1308 fix_cpuid(void)
1309 {
1310 uint64_t msr;
1311
1312 /*
1313 * Clear "Limit CPUID Maxval" bit and return true if the caller should
1314 * get the largest standard CPUID function number again if it is set
1315 * from BIOS. It is necessary for probing correct CPU topology later
1316 * and for the correct operation of the AVX-aware userspace.
1317 */
1318 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1319 ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1320 CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1321 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1322 CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1323 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1324 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1325 msr &= ~IA32_MISC_EN_LIMCPUID;
1326 wrmsr(MSR_IA32_MISC_ENABLE, msr);
1327 return (true);
1328 }
1329 }
1330
1331 /*
1332 * Re-enable AMD Topology Extension that could be disabled by BIOS
1333 * on some notebook processors. Without the extension it's really
1334 * hard to determine the correct CPU cache topology.
1335 * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h
1336 * Models 60h-6Fh Processors, Publication # 50742.
1337 */
1338 if (cpu_vendor_id == CPU_VENDOR_AMD && CPUID_TO_FAMILY(cpu_id) == 0x15) {
1339 msr = rdmsr(MSR_EXTFEATURES);
1340 if ((msr & ((uint64_t)1 << 54)) == 0) {
1341 msr |= (uint64_t)1 << 54;
1342 wrmsr(MSR_EXTFEATURES, msr);
1343 return (true);
1344 }
1345 }
1346 return (false);
1347 }
1348
1349 #ifdef __amd64__
1350 void
1351 identify_cpu(void)
1352 {
1353 u_int regs[4];
1354
1355 do_cpuid(0, regs);
1356 cpu_high = regs[0];
1357 ((u_int *)&cpu_vendor)[0] = regs[1];
1358 ((u_int *)&cpu_vendor)[1] = regs[3];
1359 ((u_int *)&cpu_vendor)[2] = regs[2];
1360 cpu_vendor[12] = '\0';
1361
1362 do_cpuid(1, regs);
1363 cpu_id = regs[0];
1364 cpu_procinfo = regs[1];
1365 cpu_feature = regs[3];
1366 cpu_feature2 = regs[2];
1367 }
1368 #endif
1369
1370 /*
1371 * Final stage of CPU identification.
1372 */
1373 void
1374 finishidentcpu(void)
1375 {
1376 u_int regs[4], cpu_stdext_disable;
1377 #ifdef __i386__
1378 u_char ccr3;
1379 #endif
1380
1381 cpu_vendor_id = find_cpu_vendor_id();
1382
1383 if (fix_cpuid()) {
1384 do_cpuid(0, regs);
1385 cpu_high = regs[0];
1386 }
1387
1388 if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1389 do_cpuid(5, regs);
1390 cpu_mon_mwait_flags = regs[2];
1391 cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE;
1392 cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE;
1393 }
1394
1395 if (cpu_high >= 7) {
1396 cpuid_count(7, 0, regs);
1397 cpu_stdext_feature = regs[1];
1398
1399 /*
1400 * Some hypervisors fail to filter out unsupported
1401 * extended features. For now, disable the
1402 * extensions, activation of which requires setting a
1403 * bit in CR4, and which VM monitors do not support.
1404 */
1405 if (cpu_feature2 & CPUID2_HV) {
1406 cpu_stdext_disable = CPUID_STDEXT_FSGSBASE |
1407 CPUID_STDEXT_SMEP;
1408 } else
1409 cpu_stdext_disable = 0;
1410 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1411 cpu_stdext_feature &= ~cpu_stdext_disable;
1412 cpu_stdext_feature2 = regs[2];
1413 }
1414
1415 #ifdef __i386__
1416 if (cpu_high > 0 &&
1417 (cpu_vendor_id == CPU_VENDOR_INTEL ||
1418 cpu_vendor_id == CPU_VENDOR_AMD ||
1419 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1420 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1421 cpu_vendor_id == CPU_VENDOR_NSC)) {
1422 do_cpuid(0x80000000, regs);
1423 if (regs[0] >= 0x80000000)
1424 cpu_exthigh = regs[0];
1425 }
1426 #else
1427 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1428 cpu_vendor_id == CPU_VENDOR_AMD ||
1429 cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1430 do_cpuid(0x80000000, regs);
1431 cpu_exthigh = regs[0];
1432 }
1433 #endif
1434 if (cpu_exthigh >= 0x80000001) {
1435 do_cpuid(0x80000001, regs);
1436 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1437 amd_feature2 = regs[2];
1438 }
1439 if (cpu_exthigh >= 0x80000007) {
1440 do_cpuid(0x80000007, regs);
1441 amd_pminfo = regs[3];
1442 }
1443 if (cpu_exthigh >= 0x80000008) {
1444 do_cpuid(0x80000008, regs);
1445 cpu_maxphyaddr = regs[0] & 0xff;
1446 cpu_procinfo2 = regs[2];
1447 } else {
1448 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1449 }
1450
1451 #ifdef __i386__
1452 if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1453 if (cpu == CPU_486) {
1454 /*
1455 * These conditions are equivalent to:
1456 * - CPU does not support cpuid instruction.
1457 * - Cyrix/IBM CPU is detected.
1458 */
1459 if (identblue() == IDENTBLUE_IBMCPU) {
1460 strcpy(cpu_vendor, "IBM");
1461 cpu_vendor_id = CPU_VENDOR_IBM;
1462 cpu = CPU_BLUE;
1463 return;
1464 }
1465 }
1466 switch (cpu_id & 0xf00) {
1467 case 0x600:
1468 /*
1469 * Cyrix's datasheet does not describe DIRs.
1470 * Therefor, I assume it does not have them
1471 * and use the result of the cpuid instruction.
1472 * XXX they seem to have it for now at least. -Peter
1473 */
1474 identifycyrix();
1475 cpu = CPU_M2;
1476 break;
1477 default:
1478 identifycyrix();
1479 /*
1480 * This routine contains a trick.
1481 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1482 */
1483 switch (cyrix_did & 0x00f0) {
1484 case 0x00:
1485 case 0xf0:
1486 cpu = CPU_486DLC;
1487 break;
1488 case 0x10:
1489 cpu = CPU_CY486DX;
1490 break;
1491 case 0x20:
1492 if ((cyrix_did & 0x000f) < 8)
1493 cpu = CPU_M1;
1494 else
1495 cpu = CPU_M1SC;
1496 break;
1497 case 0x30:
1498 cpu = CPU_M1;
1499 break;
1500 case 0x40:
1501 /* MediaGX CPU */
1502 cpu = CPU_M1SC;
1503 break;
1504 default:
1505 /* M2 and later CPUs are treated as M2. */
1506 cpu = CPU_M2;
1507
1508 /*
1509 * enable cpuid instruction.
1510 */
1511 ccr3 = read_cyrix_reg(CCR3);
1512 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1513 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1514 write_cyrix_reg(CCR3, ccr3);
1515
1516 do_cpuid(0, regs);
1517 cpu_high = regs[0]; /* eax */
1518 do_cpuid(1, regs);
1519 cpu_id = regs[0]; /* eax */
1520 cpu_feature = regs[3]; /* edx */
1521 break;
1522 }
1523 }
1524 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1525 /*
1526 * There are BlueLightning CPUs that do not change
1527 * undefined flags by dividing 5 by 2. In this case,
1528 * the CPU identification routine in locore.s leaves
1529 * cpu_vendor null string and puts CPU_486 into the
1530 * cpu.
1531 */
1532 if (identblue() == IDENTBLUE_IBMCPU) {
1533 strcpy(cpu_vendor, "IBM");
1534 cpu_vendor_id = CPU_VENDOR_IBM;
1535 cpu = CPU_BLUE;
1536 return;
1537 }
1538 }
1539 #else
1540 /* XXX */
1541 cpu = CPU_CLAWHAMMER;
1542 #endif
1543 }
1544
1545 static u_int
1546 find_cpu_vendor_id(void)
1547 {
1548 int i;
1549
1550 for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++)
1551 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1552 return (cpu_vendors[i].vendor_id);
1553 return (0);
1554 }
1555
1556 static void
1557 print_AMD_assoc(int i)
1558 {
1559 if (i == 255)
1560 printf(", fully associative\n");
1561 else
1562 printf(", %d-way associative\n", i);
1563 }
1564
1565 static void
1566 print_AMD_l2_assoc(int i)
1567 {
1568 switch (i & 0x0f) {
1569 case 0: printf(", disabled/not present\n"); break;
1570 case 1: printf(", direct mapped\n"); break;
1571 case 2: printf(", 2-way associative\n"); break;
1572 case 4: printf(", 4-way associative\n"); break;
1573 case 6: printf(", 8-way associative\n"); break;
1574 case 8: printf(", 16-way associative\n"); break;
1575 case 15: printf(", fully associative\n"); break;
1576 default: printf(", reserved configuration\n"); break;
1577 }
1578 }
1579
1580 static void
1581 print_AMD_info(void)
1582 {
1583 #ifdef __i386__
1584 uint64_t amd_whcr;
1585 #endif
1586 u_int regs[4];
1587
1588 if (cpu_exthigh >= 0x80000005) {
1589 do_cpuid(0x80000005, regs);
1590 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1591 print_AMD_assoc(regs[0] >> 24);
1592
1593 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1594 print_AMD_assoc((regs[0] >> 8) & 0xff);
1595
1596 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1597 print_AMD_assoc(regs[1] >> 24);
1598
1599 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1600 print_AMD_assoc((regs[1] >> 8) & 0xff);
1601
1602 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1603 printf(", %d bytes/line", regs[2] & 0xff);
1604 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1605 print_AMD_assoc((regs[2] >> 16) & 0xff);
1606
1607 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1608 printf(", %d bytes/line", regs[3] & 0xff);
1609 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1610 print_AMD_assoc((regs[3] >> 16) & 0xff);
1611 }
1612
1613 if (cpu_exthigh >= 0x80000006) {
1614 do_cpuid(0x80000006, regs);
1615 if ((regs[0] >> 16) != 0) {
1616 printf("L2 2MB data TLB: %d entries",
1617 (regs[0] >> 16) & 0xfff);
1618 print_AMD_l2_assoc(regs[0] >> 28);
1619 printf("L2 2MB instruction TLB: %d entries",
1620 regs[0] & 0xfff);
1621 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1622 } else {
1623 printf("L2 2MB unified TLB: %d entries",
1624 regs[0] & 0xfff);
1625 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1626 }
1627 if ((regs[1] >> 16) != 0) {
1628 printf("L2 4KB data TLB: %d entries",
1629 (regs[1] >> 16) & 0xfff);
1630 print_AMD_l2_assoc(regs[1] >> 28);
1631
1632 printf("L2 4KB instruction TLB: %d entries",
1633 (regs[1] >> 16) & 0xfff);
1634 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1635 } else {
1636 printf("L2 4KB unified TLB: %d entries",
1637 (regs[1] >> 16) & 0xfff);
1638 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1639 }
1640 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1641 printf(", %d bytes/line", regs[2] & 0xff);
1642 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1643 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1644 }
1645
1646 #ifdef __i386__
1647 if (((cpu_id & 0xf00) == 0x500)
1648 && (((cpu_id & 0x0f0) > 0x80)
1649 || (((cpu_id & 0x0f0) == 0x80)
1650 && (cpu_id & 0x00f) > 0x07))) {
1651 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1652 amd_whcr = rdmsr(0xc0000082);
1653 if (!(amd_whcr & (0x3ff << 22))) {
1654 printf("Write Allocate Disable\n");
1655 } else {
1656 printf("Write Allocate Enable Limit: %dM bytes\n",
1657 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1658 printf("Write Allocate 15-16M bytes: %s\n",
1659 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1660 }
1661 } else if (((cpu_id & 0xf00) == 0x500)
1662 && ((cpu_id & 0x0f0) > 0x50)) {
1663 /* K6, K6-2(old core) */
1664 amd_whcr = rdmsr(0xc0000082);
1665 if (!(amd_whcr & (0x7f << 1))) {
1666 printf("Write Allocate Disable\n");
1667 } else {
1668 printf("Write Allocate Enable Limit: %dM bytes\n",
1669 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1670 printf("Write Allocate 15-16M bytes: %s\n",
1671 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1672 printf("Hardware Write Allocate Control: %s\n",
1673 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1674 }
1675 }
1676 #endif
1677 /*
1678 * Opteron Rev E shows a bug as in very rare occasions a read memory
1679 * barrier is not performed as expected if it is followed by a
1680 * non-atomic read-modify-write instruction.
1681 * As long as that bug pops up very rarely (intensive machine usage
1682 * on other operating systems generally generates one unexplainable
1683 * crash any 2 months) and as long as a model specific fix would be
1684 * impractical at this stage, print out a warning string if the broken
1685 * model and family are identified.
1686 */
1687 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1688 CPUID_TO_MODEL(cpu_id) <= 0x3f)
1689 printf("WARNING: This architecture revision has known SMP "
1690 "hardware bugs which may cause random instability\n");
1691 }
1692
1693 static void
1694 print_INTEL_info(void)
1695 {
1696 u_int regs[4];
1697 u_int rounds, regnum;
1698 u_int nwaycode, nway;
1699
1700 if (cpu_high >= 2) {
1701 rounds = 0;
1702 do {
1703 do_cpuid(0x2, regs);
1704 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1705 break; /* we have a buggy CPU */
1706
1707 for (regnum = 0; regnum <= 3; ++regnum) {
1708 if (regs[regnum] & (1<<31))
1709 continue;
1710 if (regnum != 0)
1711 print_INTEL_TLB(regs[regnum] & 0xff);
1712 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1713 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1714 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1715 }
1716 } while (--rounds > 0);
1717 }
1718
1719 if (cpu_exthigh >= 0x80000006) {
1720 do_cpuid(0x80000006, regs);
1721 nwaycode = (regs[2] >> 12) & 0x0f;
1722 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1723 nway = 1 << (nwaycode / 2);
1724 else
1725 nway = 0;
1726 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1727 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1728 }
1729 }
1730
1731 static void
1732 print_INTEL_TLB(u_int data)
1733 {
1734 switch (data) {
1735 case 0x0:
1736 case 0x40:
1737 default:
1738 break;
1739 case 0x1:
1740 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1741 break;
1742 case 0x2:
1743 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1744 break;
1745 case 0x3:
1746 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1747 break;
1748 case 0x4:
1749 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1750 break;
1751 case 0x6:
1752 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1753 break;
1754 case 0x8:
1755 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
1756 break;
1757 case 0x9:
1758 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
1759 break;
1760 case 0xa:
1761 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
1762 break;
1763 case 0xb:
1764 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
1765 break;
1766 case 0xc:
1767 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
1768 break;
1769 case 0xd:
1770 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
1771 break;
1772 case 0xe:
1773 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
1774 break;
1775 case 0x1d:
1776 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
1777 break;
1778 case 0x21:
1779 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
1780 break;
1781 case 0x22:
1782 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1783 break;
1784 case 0x23:
1785 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1786 break;
1787 case 0x24:
1788 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
1789 break;
1790 case 0x25:
1791 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1792 break;
1793 case 0x29:
1794 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1795 break;
1796 case 0x2c:
1797 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
1798 break;
1799 case 0x30:
1800 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
1801 break;
1802 case 0x39: /* De-listed in SDM rev. 54 */
1803 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1804 break;
1805 case 0x3b: /* De-listed in SDM rev. 54 */
1806 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
1807 break;
1808 case 0x3c: /* De-listed in SDM rev. 54 */
1809 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1810 break;
1811 case 0x41:
1812 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
1813 break;
1814 case 0x42:
1815 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
1816 break;
1817 case 0x43:
1818 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
1819 break;
1820 case 0x44:
1821 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
1822 break;
1823 case 0x45:
1824 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
1825 break;
1826 case 0x46:
1827 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
1828 break;
1829 case 0x47:
1830 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
1831 break;
1832 case 0x48:
1833 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
1834 break;
1835 case 0x49:
1836 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
1837 CPUID_TO_MODEL(cpu_id) == 0x6)
1838 printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
1839 else
1840 printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
1841 break;
1842 case 0x4a:
1843 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
1844 break;
1845 case 0x4b:
1846 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
1847 break;
1848 case 0x4c:
1849 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
1850 break;
1851 case 0x4d:
1852 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
1853 break;
1854 case 0x4e:
1855 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
1856 break;
1857 case 0x4f:
1858 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
1859 break;
1860 case 0x50:
1861 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
1862 break;
1863 case 0x51:
1864 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
1865 break;
1866 case 0x52:
1867 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
1868 break;
1869 case 0x55:
1870 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
1871 break;
1872 case 0x56:
1873 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
1874 break;
1875 case 0x57:
1876 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
1877 break;
1878 case 0x59:
1879 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
1880 break;
1881 case 0x5a:
1882 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
1883 break;
1884 case 0x5b:
1885 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
1886 break;
1887 case 0x5c:
1888 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
1889 break;
1890 case 0x5d:
1891 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
1892 break;
1893 case 0x60:
1894 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1895 break;
1896 case 0x61:
1897 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
1898 break;
1899 case 0x63:
1900 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n");
1901 break;
1902 case 0x64:
1903 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n");
1904 break;
1905 case 0x66:
1906 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1907 break;
1908 case 0x67:
1909 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1910 break;
1911 case 0x68:
1912 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
1913 break;
1914 case 0x6a:
1915 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
1916 break;
1917 case 0x6b:
1918 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
1919 break;
1920 case 0x6c:
1921 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
1922 break;
1923 case 0x6d:
1924 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
1925 break;
1926 case 0x70:
1927 printf("Trace cache: 12K-uops, 8-way set associative\n");
1928 break;
1929 case 0x71:
1930 printf("Trace cache: 16K-uops, 8-way set associative\n");
1931 break;
1932 case 0x72:
1933 printf("Trace cache: 32K-uops, 8-way set associative\n");
1934 break;
1935 case 0x76:
1936 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
1937 break;
1938 case 0x78:
1939 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
1940 break;
1941 case 0x79:
1942 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1943 break;
1944 case 0x7a:
1945 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1946 break;
1947 case 0x7b:
1948 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1949 break;
1950 case 0x7c:
1951 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1952 break;
1953 case 0x7d:
1954 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
1955 break;
1956 case 0x7f:
1957 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
1958 break;
1959 case 0x80:
1960 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
1961 break;
1962 case 0x82:
1963 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
1964 break;
1965 case 0x83:
1966 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
1967 break;
1968 case 0x84:
1969 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
1970 break;
1971 case 0x85:
1972 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
1973 break;
1974 case 0x86:
1975 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
1976 break;
1977 case 0x87:
1978 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
1979 break;
1980 case 0xa0:
1981 printf("DTLB: 4k pages, fully associative, 32 entries\n");
1982 break;
1983 case 0xb0:
1984 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
1985 break;
1986 case 0xb1:
1987 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
1988 break;
1989 case 0xb2:
1990 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
1991 break;
1992 case 0xb3:
1993 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
1994 break;
1995 case 0xb4:
1996 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
1997 break;
1998 case 0xb5:
1999 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2000 break;
2001 case 0xb6:
2002 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2003 break;
2004 case 0xba:
2005 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2006 break;
2007 case 0xc0:
2008 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2009 break;
2010 case 0xc1:
2011 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2012 break;
2013 case 0xc2:
2014 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2015 break;
2016 case 0xc3:
2017 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2018 break;
2019 case 0xc4:
2020 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n");
2021 break;
2022 case 0xca:
2023 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2024 break;
2025 case 0xd0:
2026 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2027 break;
2028 case 0xd1:
2029 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2030 break;
2031 case 0xd2:
2032 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2033 break;
2034 case 0xd6:
2035 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2036 break;
2037 case 0xd7:
2038 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2039 break;
2040 case 0xd8:
2041 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2042 break;
2043 case 0xdc:
2044 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2045 break;
2046 case 0xdd:
2047 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2048 break;
2049 case 0xde:
2050 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2051 break;
2052 case 0xe2:
2053 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2054 break;
2055 case 0xe3:
2056 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2057 break;
2058 case 0xe4:
2059 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2060 break;
2061 case 0xea:
2062 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2063 break;
2064 case 0xeb:
2065 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2066 break;
2067 case 0xec:
2068 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2069 break;
2070 case 0xf0:
2071 printf("64-Byte prefetching\n");
2072 break;
2073 case 0xf1:
2074 printf("128-Byte prefetching\n");
2075 break;
2076 }
2077 }
2078
2079 static void
2080 print_svm_info(void)
2081 {
2082 u_int features, regs[4];
2083 uint64_t msr;
2084 int comma;
2085
2086 printf("\n SVM: ");
2087 do_cpuid(0x8000000A, regs);
2088 features = regs[3];
2089
2090 msr = rdmsr(MSR_VM_CR);
2091 if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2092 printf("(disabled in BIOS) ");
2093
2094 if (!bootverbose) {
2095 comma = 0;
2096 if (features & (1 << 0)) {
2097 printf("%sNP", comma ? "," : "");
2098 comma = 1;
2099 }
2100 if (features & (1 << 3)) {
2101 printf("%sNRIP", comma ? "," : "");
2102 comma = 1;
2103 }
2104 if (features & (1 << 5)) {
2105 printf("%sVClean", comma ? "," : "");
2106 comma = 1;
2107 }
2108 if (features & (1 << 6)) {
2109 printf("%sAFlush", comma ? "," : "");
2110 comma = 1;
2111 }
2112 if (features & (1 << 7)) {
2113 printf("%sDAssist", comma ? "," : "");
2114 comma = 1;
2115 }
2116 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2117 return;
2118 }
2119
2120 printf("Features=0x%b", features,
2121 "\020"
2122 "\001NP" /* Nested paging */
2123 "\002LbrVirt" /* LBR virtualization */
2124 "\003SVML" /* SVM lock */
2125 "\004NRIPS" /* NRIP save */
2126 "\005TscRateMsr" /* MSR based TSC rate control */
2127 "\006VmcbClean" /* VMCB clean bits */
2128 "\007FlushByAsid" /* Flush by ASID */
2129 "\010DecodeAssist" /* Decode assist */
2130 "\011<b8>"
2131 "\012<b9>"
2132 "\013PauseFilter" /* PAUSE intercept filter */
2133 "\014<b11>"
2134 "\015PauseFilterThreshold" /* PAUSE filter threshold */
2135 "\016AVIC" /* virtual interrupt controller */
2136 );
2137 printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2138 }
2139
2140 #ifdef __i386__
2141 static void
2142 print_transmeta_info(void)
2143 {
2144 u_int regs[4], nreg = 0;
2145
2146 do_cpuid(0x80860000, regs);
2147 nreg = regs[0];
2148 if (nreg >= 0x80860001) {
2149 do_cpuid(0x80860001, regs);
2150 printf(" Processor revision %u.%u.%u.%u\n",
2151 (regs[1] >> 24) & 0xff,
2152 (regs[1] >> 16) & 0xff,
2153 (regs[1] >> 8) & 0xff,
2154 regs[1] & 0xff);
2155 }
2156 if (nreg >= 0x80860002) {
2157 do_cpuid(0x80860002, regs);
2158 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
2159 (regs[1] >> 24) & 0xff,
2160 (regs[1] >> 16) & 0xff,
2161 (regs[1] >> 8) & 0xff,
2162 regs[1] & 0xff,
2163 regs[2]);
2164 }
2165 if (nreg >= 0x80860006) {
2166 char info[65];
2167 do_cpuid(0x80860003, (u_int*) &info[0]);
2168 do_cpuid(0x80860004, (u_int*) &info[16]);
2169 do_cpuid(0x80860005, (u_int*) &info[32]);
2170 do_cpuid(0x80860006, (u_int*) &info[48]);
2171 info[64] = 0;
2172 printf(" %s\n", info);
2173 }
2174 }
2175 #endif
2176
2177 static void
2178 print_via_padlock_info(void)
2179 {
2180 u_int regs[4];
2181
2182 do_cpuid(0xc0000001, regs);
2183 printf("\n VIA Padlock Features=0x%b", regs[3],
2184 "\020"
2185 "\003RNG" /* RNG */
2186 "\007AES" /* ACE */
2187 "\011AES-CTR" /* ACE2 */
2188 "\013SHA1,SHA256" /* PHE */
2189 "\015RSA" /* PMM */
2190 );
2191 }
2192
2193 static uint32_t
2194 vmx_settable(uint64_t basic, int msr, int true_msr)
2195 {
2196 uint64_t val;
2197
2198 if (basic & (1ULL << 55))
2199 val = rdmsr(true_msr);
2200 else
2201 val = rdmsr(msr);
2202
2203 /* Just report the controls that can be set to 1. */
2204 return (val >> 32);
2205 }
2206
2207 static void
2208 print_vmx_info(void)
2209 {
2210 uint64_t basic, msr;
2211 uint32_t entry, exit, mask, pin, proc, proc2;
2212 int comma;
2213
2214 printf("\n VT-x: ");
2215 msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2216 if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2217 printf("(disabled in BIOS) ");
2218 basic = rdmsr(MSR_VMX_BASIC);
2219 pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2220 MSR_VMX_TRUE_PINBASED_CTLS);
2221 proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2222 MSR_VMX_TRUE_PROCBASED_CTLS);
2223 if (proc & PROCBASED_SECONDARY_CONTROLS)
2224 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2225 MSR_VMX_PROCBASED_CTLS2);
2226 else
2227 proc2 = 0;
2228 exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2229 entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2230
2231 if (!bootverbose) {
2232 comma = 0;
2233 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2234 entry & VM_ENTRY_LOAD_PAT) {
2235 printf("%sPAT", comma ? "," : "");
2236 comma = 1;
2237 }
2238 if (proc & PROCBASED_HLT_EXITING) {
2239 printf("%sHLT", comma ? "," : "");
2240 comma = 1;
2241 }
2242 if (proc & PROCBASED_MTF) {
2243 printf("%sMTF", comma ? "," : "");
2244 comma = 1;
2245 }
2246 if (proc & PROCBASED_PAUSE_EXITING) {
2247 printf("%sPAUSE", comma ? "," : "");
2248 comma = 1;
2249 }
2250 if (proc2 & PROCBASED2_ENABLE_EPT) {
2251 printf("%sEPT", comma ? "," : "");
2252 comma = 1;
2253 }
2254 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2255 printf("%sUG", comma ? "," : "");
2256 comma = 1;
2257 }
2258 if (proc2 & PROCBASED2_ENABLE_VPID) {
2259 printf("%sVPID", comma ? "," : "");
2260 comma = 1;
2261 }
2262 if (proc & PROCBASED_USE_TPR_SHADOW &&
2263 proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2264 proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2265 proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2266 proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2267 printf("%sVID", comma ? "," : "");
2268 comma = 1;
2269 if (pin & PINBASED_POSTED_INTERRUPT)
2270 printf(",PostIntr");
2271 }
2272 return;
2273 }
2274
2275 mask = basic >> 32;
2276 printf("Basic Features=0x%b", mask,
2277 "\020"
2278 "\02132PA" /* 32-bit physical addresses */
2279 "\022SMM" /* SMM dual-monitor */
2280 "\027INS/OUTS" /* VM-exit info for INS and OUTS */
2281 "\030TRUE" /* TRUE_CTLS MSRs */
2282 );
2283 printf("\n Pin-Based Controls=0x%b", pin,
2284 "\020"
2285 "\001ExtINT" /* External-interrupt exiting */
2286 "\004NMI" /* NMI exiting */
2287 "\006VNMI" /* Virtual NMIs */
2288 "\007PreTmr" /* Activate VMX-preemption timer */
2289 "\010PostIntr" /* Process posted interrupts */
2290 );
2291 printf("\n Primary Processor Controls=0x%b", proc,
2292 "\020"
2293 "\003INTWIN" /* Interrupt-window exiting */
2294 "\004TSCOff" /* Use TSC offsetting */
2295 "\010HLT" /* HLT exiting */
2296 "\012INVLPG" /* INVLPG exiting */
2297 "\013MWAIT" /* MWAIT exiting */
2298 "\014RDPMC" /* RDPMC exiting */
2299 "\015RDTSC" /* RDTSC exiting */
2300 "\020CR3-LD" /* CR3-load exiting */
2301 "\021CR3-ST" /* CR3-store exiting */
2302 "\024CR8-LD" /* CR8-load exiting */
2303 "\025CR8-ST" /* CR8-store exiting */
2304 "\026TPR" /* Use TPR shadow */
2305 "\027NMIWIN" /* NMI-window exiting */
2306 "\030MOV-DR" /* MOV-DR exiting */
2307 "\031IO" /* Unconditional I/O exiting */
2308 "\032IOmap" /* Use I/O bitmaps */
2309 "\034MTF" /* Monitor trap flag */
2310 "\035MSRmap" /* Use MSR bitmaps */
2311 "\036MONITOR" /* MONITOR exiting */
2312 "\037PAUSE" /* PAUSE exiting */
2313 );
2314 if (proc & PROCBASED_SECONDARY_CONTROLS)
2315 printf("\n Secondary Processor Controls=0x%b", proc2,
2316 "\020"
2317 "\001APIC" /* Virtualize APIC accesses */
2318 "\002EPT" /* Enable EPT */
2319 "\003DT" /* Descriptor-table exiting */
2320 "\004RDTSCP" /* Enable RDTSCP */
2321 "\005x2APIC" /* Virtualize x2APIC mode */
2322 "\006VPID" /* Enable VPID */
2323 "\007WBINVD" /* WBINVD exiting */
2324 "\010UG" /* Unrestricted guest */
2325 "\011APIC-reg" /* APIC-register virtualization */
2326 "\012VID" /* Virtual-interrupt delivery */
2327 "\013PAUSE-loop" /* PAUSE-loop exiting */
2328 "\014RDRAND" /* RDRAND exiting */
2329 "\015INVPCID" /* Enable INVPCID */
2330 "\016VMFUNC" /* Enable VM functions */
2331 "\017VMCS" /* VMCS shadowing */
2332 "\020EPT#VE" /* EPT-violation #VE */
2333 "\021XSAVES" /* Enable XSAVES/XRSTORS */
2334 );
2335 printf("\n Exit Controls=0x%b", mask,
2336 "\020"
2337 "\003DR" /* Save debug controls */
2338 /* Ignore Host address-space size */
2339 "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2340 "\020AckInt" /* Acknowledge interrupt on exit */
2341 "\023PAT-SV" /* Save MSR_PAT */
2342 "\024PAT-LD" /* Load MSR_PAT */
2343 "\025EFER-SV" /* Save MSR_EFER */
2344 "\026EFER-LD" /* Load MSR_EFER */
2345 "\027PTMR-SV" /* Save VMX-preemption timer value */
2346 );
2347 printf("\n Entry Controls=0x%b", mask,
2348 "\020"
2349 "\003DR" /* Save debug controls */
2350 /* Ignore IA-32e mode guest */
2351 /* Ignore Entry to SMM */
2352 /* Ignore Deactivate dual-monitor treatment */
2353 "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2354 "\017PAT" /* Load MSR_PAT */
2355 "\020EFER" /* Load MSR_EFER */
2356 );
2357 if (proc & PROCBASED_SECONDARY_CONTROLS &&
2358 (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2359 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2360 mask = msr;
2361 printf("\n EPT Features=0x%b", mask,
2362 "\020"
2363 "\001XO" /* Execute-only translations */
2364 "\007PW4" /* Page-walk length of 4 */
2365 "\011UC" /* EPT paging-structure mem can be UC */
2366 "\017WB" /* EPT paging-structure mem can be WB */
2367 "\0212M" /* EPT PDE can map a 2-Mbyte page */
2368 "\0221G" /* EPT PDPTE can map a 1-Gbyte page */
2369 "\025INVEPT" /* INVEPT is supported */
2370 "\026AD" /* Accessed and dirty flags for EPT */
2371 "\032single" /* INVEPT single-context type */
2372 "\033all" /* INVEPT all-context type */
2373 );
2374 mask = msr >> 32;
2375 printf("\n VPID Features=0x%b", mask,
2376 "\020"
2377 "\001INVVPID" /* INVVPID is supported */
2378 "\011individual" /* INVVPID individual-address type */
2379 "\012single" /* INVVPID single-context type */
2380 "\013all" /* INVVPID all-context type */
2381 /* INVVPID single-context-retaining-globals type */
2382 "\014single-globals"
2383 );
2384 }
2385 }
2386
2387 static void
2388 print_hypervisor_info(void)
2389 {
2390
2391 if (*hv_vendor)
2392 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2393 }
Cache object: af298cd041b3aa3de6cce2cf97c83201
|