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sys/x86/x86/mca.c
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1 /*- 2 * Copyright (c) 2009 Hudson River Trading LLC 3 * Written by: John H. Baldwin <jhb@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * Support for x86 machine check architecture. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #ifdef __amd64__ 36 #define DEV_APIC 37 #else 38 #include "opt_apic.h" 39 #endif 40 41 #include <sys/param.h> 42 #include <sys/bus.h> 43 #include <sys/interrupt.h> 44 #include <sys/kernel.h> 45 #include <sys/lock.h> 46 #include <sys/malloc.h> 47 #include <sys/mutex.h> 48 #include <sys/proc.h> 49 #include <sys/sched.h> 50 #include <sys/smp.h> 51 #include <sys/sysctl.h> 52 #include <sys/systm.h> 53 #include <sys/taskqueue.h> 54 #include <machine/intr_machdep.h> 55 #include <machine/apicvar.h> 56 #include <machine/cpu.h> 57 #include <machine/cputypes.h> 58 #include <machine/mca.h> 59 #include <machine/md_var.h> 60 #include <machine/specialreg.h> 61 62 /* Modes for mca_scan() */ 63 enum scan_mode { 64 POLLED, 65 MCE, 66 CMCI, 67 }; 68 69 #ifdef DEV_APIC 70 /* 71 * State maintained for each monitored MCx bank to control the 72 * corrected machine check interrupt threshold. 73 */ 74 struct cmc_state { 75 int max_threshold; 76 int last_intr; 77 }; 78 #endif 79 80 struct mca_internal { 81 struct mca_record rec; 82 int logged; 83 STAILQ_ENTRY(mca_internal) link; 84 }; 85 86 static MALLOC_DEFINE(M_MCA, "MCA", "Machine Check Architecture"); 87 88 static volatile int mca_count; /* Number of records stored. */ 89 static int mca_banks; /* Number of per-CPU register banks. */ 90 91 SYSCTL_NODE(_hw, OID_AUTO, mca, CTLFLAG_RD, NULL, "Machine Check Architecture"); 92 93 static int mca_enabled = 1; 94 TUNABLE_INT("hw.mca.enabled", &mca_enabled); 95 SYSCTL_INT(_hw_mca, OID_AUTO, enabled, CTLFLAG_RDTUN, &mca_enabled, 0, 96 "Administrative toggle for machine check support"); 97 98 static int amd10h_L1TP = 1; 99 TUNABLE_INT("hw.mca.amd10h_L1TP", &amd10h_L1TP); 100 SYSCTL_INT(_hw_mca, OID_AUTO, amd10h_L1TP, CTLFLAG_RDTUN, &amd10h_L1TP, 0, 101 "Administrative toggle for logging of level one TLB parity (L1TP) errors"); 102 103 static int intel6h_HSD131; 104 TUNABLE_INT("hw.mca.intel6h_hsd131", &intel6h_HSD131); 105 SYSCTL_INT(_hw_mca, OID_AUTO, intel6h_HSD131, CTLFLAG_RDTUN, &intel6h_HSD131, 0, 106 "Administrative toggle for logging of spurious corrected errors"); 107 108 int workaround_erratum383; 109 SYSCTL_INT(_hw_mca, OID_AUTO, erratum383, CTLFLAG_RD, &workaround_erratum383, 0, 110 "Is the workaround for Erratum 383 on AMD Family 10h processors enabled?"); 111 112 static STAILQ_HEAD(, mca_internal) mca_freelist; 113 static int mca_freecount; 114 static STAILQ_HEAD(, mca_internal) mca_records; 115 static struct callout mca_timer; 116 static int mca_ticks = 3600; /* Check hourly by default. */ 117 static struct taskqueue *mca_tq; 118 static struct task mca_refill_task, mca_scan_task; 119 static struct mtx mca_lock; 120 121 #ifdef DEV_APIC 122 static struct cmc_state **cmc_state; /* Indexed by cpuid, bank */ 123 static int cmc_throttle = 60; /* Time in seconds to throttle CMCI. */ 124 #endif 125 126 static int 127 sysctl_positive_int(SYSCTL_HANDLER_ARGS) 128 { 129 int error, value; 130 131 value = *(int *)arg1; 132 error = sysctl_handle_int(oidp, &value, 0, req); 133 if (error || req->newptr == NULL) 134 return (error); 135 if (value <= 0) 136 return (EINVAL); 137 *(int *)arg1 = value; 138 return (0); 139 } 140 141 static int 142 sysctl_mca_records(SYSCTL_HANDLER_ARGS) 143 { 144 int *name = (int *)arg1; 145 u_int namelen = arg2; 146 struct mca_record record; 147 struct mca_internal *rec; 148 int i; 149 150 if (namelen != 1) 151 return (EINVAL); 152 153 if (name[0] < 0 || name[0] >= mca_count) 154 return (EINVAL); 155 156 mtx_lock_spin(&mca_lock); 157 if (name[0] >= mca_count) { 158 mtx_unlock_spin(&mca_lock); 159 return (EINVAL); 160 } 161 i = 0; 162 STAILQ_FOREACH(rec, &mca_records, link) { 163 if (i == name[0]) { 164 record = rec->rec; 165 break; 166 } 167 i++; 168 } 169 mtx_unlock_spin(&mca_lock); 170 return (SYSCTL_OUT(req, &record, sizeof(record))); 171 } 172 173 static const char * 174 mca_error_ttype(uint16_t mca_error) 175 { 176 177 switch ((mca_error & 0x000c) >> 2) { 178 case 0: 179 return ("I"); 180 case 1: 181 return ("D"); 182 case 2: 183 return ("G"); 184 } 185 return ("?"); 186 } 187 188 static const char * 189 mca_error_level(uint16_t mca_error) 190 { 191 192 switch (mca_error & 0x0003) { 193 case 0: 194 return ("L0"); 195 case 1: 196 return ("L1"); 197 case 2: 198 return ("L2"); 199 case 3: 200 return ("LG"); 201 } 202 return ("L?"); 203 } 204 205 static const char * 206 mca_error_request(uint16_t mca_error) 207 { 208 209 switch ((mca_error & 0x00f0) >> 4) { 210 case 0x0: 211 return ("ERR"); 212 case 0x1: 213 return ("RD"); 214 case 0x2: 215 return ("WR"); 216 case 0x3: 217 return ("DRD"); 218 case 0x4: 219 return ("DWR"); 220 case 0x5: 221 return ("IRD"); 222 case 0x6: 223 return ("PREFETCH"); 224 case 0x7: 225 return ("EVICT"); 226 case 0x8: 227 return ("SNOOP"); 228 } 229 return ("???"); 230 } 231 232 static const char * 233 mca_error_mmtype(uint16_t mca_error) 234 { 235 236 switch ((mca_error & 0x70) >> 4) { 237 case 0x0: 238 return ("GEN"); 239 case 0x1: 240 return ("RD"); 241 case 0x2: 242 return ("WR"); 243 case 0x3: 244 return ("AC"); 245 case 0x4: 246 return ("MS"); 247 } 248 return ("???"); 249 } 250 251 static int __nonnull(1) 252 mca_mute(const struct mca_record *rec) 253 { 254 255 /* 256 * Skip spurious corrected parity errors generated by Intel Haswell- 257 * and Broadwell-based CPUs (see HSD131, HSM142, HSW131 and BDM48 258 * erratum respectively), unless reporting is enabled. 259 * Note that these errors also have been observed with the D0-stepping 260 * of Haswell, while at least initially the CPU specification updates 261 * suggested only the C0-stepping to be affected. Similarly, Celeron 262 * 2955U with a CPU ID of 0x45 apparently are also concerned with the 263 * same problem, with HSM142 only referring to 0x3c and 0x46. 264 */ 265 if (cpu_vendor_id == CPU_VENDOR_INTEL && 266 CPUID_TO_FAMILY(cpu_id) == 0x6 && 267 (CPUID_TO_MODEL(cpu_id) == 0x3c || /* HSD131, HSM142, HSW131 */ 268 CPUID_TO_MODEL(cpu_id) == 0x3d || /* BDM48 */ 269 CPUID_TO_MODEL(cpu_id) == 0x45 || 270 CPUID_TO_MODEL(cpu_id) == 0x46) && /* HSM142 */ 271 rec->mr_bank == 0 && 272 (rec->mr_status & 0xa0000000ffffffff) == 0x80000000000f0005 && 273 !intel6h_HSD131) 274 return (1); 275 276 return (0); 277 } 278 279 /* Dump details about a single machine check. */ 280 static void __nonnull(1) 281 mca_log(const struct mca_record *rec) 282 { 283 uint16_t mca_error; 284 285 if (mca_mute(rec)) 286 return; 287 288 printf("MCA: Bank %d, Status 0x%016llx\n", rec->mr_bank, 289 (long long)rec->mr_status); 290 printf("MCA: Global Cap 0x%016llx, Status 0x%016llx\n", 291 (long long)rec->mr_mcg_cap, (long long)rec->mr_mcg_status); 292 printf("MCA: Vendor \"%s\", ID 0x%x, APIC ID %d\n", cpu_vendor, 293 rec->mr_cpu_id, rec->mr_apic_id); 294 printf("MCA: CPU %d ", rec->mr_cpu); 295 if (rec->mr_status & MC_STATUS_UC) 296 printf("UNCOR "); 297 else { 298 printf("COR "); 299 if (rec->mr_mcg_cap & MCG_CAP_CMCI_P) 300 printf("(%lld) ", ((long long)rec->mr_status & 301 MC_STATUS_COR_COUNT) >> 38); 302 } 303 if (rec->mr_status & MC_STATUS_PCC) 304 printf("PCC "); 305 if (rec->mr_status & MC_STATUS_OVER) 306 printf("OVER "); 307 mca_error = rec->mr_status & MC_STATUS_MCA_ERROR; 308 switch (mca_error) { 309 /* Simple error codes. */ 310 case 0x0000: 311 printf("no error"); 312 break; 313 case 0x0001: 314 printf("unclassified error"); 315 break; 316 case 0x0002: 317 printf("ucode ROM parity error"); 318 break; 319 case 0x0003: 320 printf("external error"); 321 break; 322 case 0x0004: 323 printf("FRC error"); 324 break; 325 case 0x0005: 326 printf("internal parity error"); 327 break; 328 case 0x0400: 329 printf("internal timer error"); 330 break; 331 default: 332 if ((mca_error & 0xfc00) == 0x0400) { 333 printf("internal error %x", mca_error & 0x03ff); 334 break; 335 } 336 337 /* Compound error codes. */ 338 339 /* Memory hierarchy error. */ 340 if ((mca_error & 0xeffc) == 0x000c) { 341 printf("%s memory error", mca_error_level(mca_error)); 342 break; 343 } 344 345 /* TLB error. */ 346 if ((mca_error & 0xeff0) == 0x0010) { 347 printf("%sTLB %s error", mca_error_ttype(mca_error), 348 mca_error_level(mca_error)); 349 break; 350 } 351 352 /* Memory controller error. */ 353 if ((mca_error & 0xef80) == 0x0080) { 354 printf("%s channel ", mca_error_mmtype(mca_error)); 355 if ((mca_error & 0x000f) != 0x000f) 356 printf("%d", mca_error & 0x000f); 357 else 358 printf("??"); 359 printf(" memory error"); 360 break; 361 } 362 363 /* Cache error. */ 364 if ((mca_error & 0xef00) == 0x0100) { 365 printf("%sCACHE %s %s error", 366 mca_error_ttype(mca_error), 367 mca_error_level(mca_error), 368 mca_error_request(mca_error)); 369 break; 370 } 371 372 /* Bus and/or Interconnect error. */ 373 if ((mca_error & 0xe800) == 0x0800) { 374 printf("BUS%s ", mca_error_level(mca_error)); 375 switch ((mca_error & 0x0600) >> 9) { 376 case 0: 377 printf("Source"); 378 break; 379 case 1: 380 printf("Responder"); 381 break; 382 case 2: 383 printf("Observer"); 384 break; 385 default: 386 printf("???"); 387 break; 388 } 389 printf(" %s ", mca_error_request(mca_error)); 390 switch ((mca_error & 0x000c) >> 2) { 391 case 0: 392 printf("Memory"); 393 break; 394 case 2: 395 printf("I/O"); 396 break; 397 case 3: 398 printf("Other"); 399 break; 400 default: 401 printf("???"); 402 break; 403 } 404 if (mca_error & 0x0100) 405 printf(" timed out"); 406 break; 407 } 408 409 printf("unknown error %x", mca_error); 410 break; 411 } 412 printf("\n"); 413 if (rec->mr_status & MC_STATUS_ADDRV) 414 printf("MCA: Address 0x%llx\n", (long long)rec->mr_addr); 415 if (rec->mr_status & MC_STATUS_MISCV) 416 printf("MCA: Misc 0x%llx\n", (long long)rec->mr_misc); 417 } 418 419 static int __nonnull(2) 420 mca_check_status(int bank, struct mca_record *rec) 421 { 422 uint64_t status; 423 u_int p[4]; 424 425 status = rdmsr(MSR_MC_STATUS(bank)); 426 if (!(status & MC_STATUS_VAL)) 427 return (0); 428 429 /* Save exception information. */ 430 rec->mr_status = status; 431 rec->mr_bank = bank; 432 rec->mr_addr = 0; 433 if (status & MC_STATUS_ADDRV) 434 rec->mr_addr = rdmsr(MSR_MC_ADDR(bank)); 435 rec->mr_misc = 0; 436 if (status & MC_STATUS_MISCV) 437 rec->mr_misc = rdmsr(MSR_MC_MISC(bank)); 438 rec->mr_tsc = rdtsc(); 439 rec->mr_apic_id = PCPU_GET(apic_id); 440 rec->mr_mcg_cap = rdmsr(MSR_MCG_CAP); 441 rec->mr_mcg_status = rdmsr(MSR_MCG_STATUS); 442 rec->mr_cpu_id = cpu_id; 443 rec->mr_cpu_vendor_id = cpu_vendor_id; 444 rec->mr_cpu = PCPU_GET(cpuid); 445 446 /* 447 * Clear machine check. Don't do this for uncorrectable 448 * errors so that the BIOS can see them. 449 */ 450 if (!(rec->mr_status & (MC_STATUS_PCC | MC_STATUS_UC))) { 451 wrmsr(MSR_MC_STATUS(bank), 0); 452 do_cpuid(0, p); 453 } 454 return (1); 455 } 456 457 static void 458 mca_fill_freelist(void) 459 { 460 struct mca_internal *rec; 461 int desired; 462 463 /* 464 * Ensure we have at least one record for each bank and one 465 * record per CPU. 466 */ 467 desired = imax(mp_ncpus, mca_banks); 468 mtx_lock_spin(&mca_lock); 469 while (mca_freecount < desired) { 470 mtx_unlock_spin(&mca_lock); 471 rec = malloc(sizeof(*rec), M_MCA, M_WAITOK); 472 mtx_lock_spin(&mca_lock); 473 STAILQ_INSERT_TAIL(&mca_freelist, rec, link); 474 mca_freecount++; 475 } 476 mtx_unlock_spin(&mca_lock); 477 } 478 479 static void 480 mca_refill(void *context, int pending) 481 { 482 483 mca_fill_freelist(); 484 } 485 486 static void __nonnull(2) 487 mca_record_entry(enum scan_mode mode, const struct mca_record *record) 488 { 489 struct mca_internal *rec; 490 491 if (mode == POLLED) { 492 rec = malloc(sizeof(*rec), M_MCA, M_WAITOK); 493 mtx_lock_spin(&mca_lock); 494 } else { 495 mtx_lock_spin(&mca_lock); 496 rec = STAILQ_FIRST(&mca_freelist); 497 if (rec == NULL) { 498 printf("MCA: Unable to allocate space for an event.\n"); 499 mca_log(record); 500 mtx_unlock_spin(&mca_lock); 501 return; 502 } 503 STAILQ_REMOVE_HEAD(&mca_freelist, link); 504 mca_freecount--; 505 } 506 507 rec->rec = *record; 508 rec->logged = 0; 509 STAILQ_INSERT_TAIL(&mca_records, rec, link); 510 mca_count++; 511 mtx_unlock_spin(&mca_lock); 512 if (mode == CMCI) 513 taskqueue_enqueue_fast(mca_tq, &mca_refill_task); 514 } 515 516 #ifdef DEV_APIC 517 /* 518 * Update the interrupt threshold for a CMCI. The strategy is to use 519 * a low trigger that interrupts as soon as the first event occurs. 520 * However, if a steady stream of events arrive, the threshold is 521 * increased until the interrupts are throttled to once every 522 * cmc_throttle seconds or the periodic scan. If a periodic scan 523 * finds that the threshold is too high, it is lowered. 524 */ 525 static void 526 cmci_update(enum scan_mode mode, int bank, int valid, struct mca_record *rec) 527 { 528 struct cmc_state *cc; 529 uint64_t ctl; 530 u_int delta; 531 int count, limit; 532 533 /* Fetch the current limit for this bank. */ 534 cc = &cmc_state[PCPU_GET(cpuid)][bank]; 535 ctl = rdmsr(MSR_MC_CTL2(bank)); 536 count = (rec->mr_status & MC_STATUS_COR_COUNT) >> 38; 537 delta = (u_int)(ticks - cc->last_intr); 538 539 /* 540 * If an interrupt was received less than cmc_throttle seconds 541 * since the previous interrupt and the count from the current 542 * event is greater than or equal to the current threshold, 543 * double the threshold up to the max. 544 */ 545 if (mode == CMCI && valid) { 546 limit = ctl & MC_CTL2_THRESHOLD; 547 if (delta < cmc_throttle && count >= limit && 548 limit < cc->max_threshold) { 549 limit = min(limit << 1, cc->max_threshold); 550 ctl &= ~MC_CTL2_THRESHOLD; 551 ctl |= limit; 552 wrmsr(MSR_MC_CTL2(bank), limit); 553 } 554 cc->last_intr = ticks; 555 return; 556 } 557 558 /* 559 * When the banks are polled, check to see if the threshold 560 * should be lowered. 561 */ 562 if (mode != POLLED) 563 return; 564 565 /* If a CMCI occured recently, do nothing for now. */ 566 if (delta < cmc_throttle) 567 return; 568 569 /* 570 * Compute a new limit based on the average rate of events per 571 * cmc_throttle seconds since the last interrupt. 572 */ 573 if (valid) { 574 count = (rec->mr_status & MC_STATUS_COR_COUNT) >> 38; 575 limit = count * cmc_throttle / delta; 576 if (limit <= 0) 577 limit = 1; 578 else if (limit > cc->max_threshold) 579 limit = cc->max_threshold; 580 } else 581 limit = 1; 582 if ((ctl & MC_CTL2_THRESHOLD) != limit) { 583 ctl &= ~MC_CTL2_THRESHOLD; 584 ctl |= limit; 585 wrmsr(MSR_MC_CTL2(bank), limit); 586 } 587 } 588 #endif 589 590 /* 591 * This scans all the machine check banks of the current CPU to see if 592 * there are any machine checks. Any non-recoverable errors are 593 * reported immediately via mca_log(). The current thread must be 594 * pinned when this is called. The 'mode' parameter indicates if we 595 * are being called from the MC exception handler, the CMCI handler, 596 * or the periodic poller. In the MC exception case this function 597 * returns true if the system is restartable. Otherwise, it returns a 598 * count of the number of valid MC records found. 599 */ 600 static int 601 mca_scan(enum scan_mode mode) 602 { 603 struct mca_record rec; 604 uint64_t mcg_cap, ucmask; 605 int count, i, recoverable, valid; 606 607 count = 0; 608 recoverable = 1; 609 ucmask = MC_STATUS_UC | MC_STATUS_PCC; 610 611 /* When handling a MCE#, treat the OVER flag as non-restartable. */ 612 if (mode == MCE) 613 ucmask |= MC_STATUS_OVER; 614 mcg_cap = rdmsr(MSR_MCG_CAP); 615 for (i = 0; i < (mcg_cap & MCG_CAP_COUNT); i++) { 616 #ifdef DEV_APIC 617 /* 618 * For a CMCI, only check banks this CPU is 619 * responsible for. 620 */ 621 if (mode == CMCI && !(PCPU_GET(cmci_mask) & 1 << i)) 622 continue; 623 #endif 624 625 valid = mca_check_status(i, &rec); 626 if (valid) { 627 count++; 628 if (rec.mr_status & ucmask) { 629 recoverable = 0; 630 mtx_lock_spin(&mca_lock); 631 mca_log(&rec); 632 mtx_unlock_spin(&mca_lock); 633 } 634 mca_record_entry(mode, &rec); 635 } 636 637 #ifdef DEV_APIC 638 /* 639 * If this is a bank this CPU monitors via CMCI, 640 * update the threshold. 641 */ 642 if (PCPU_GET(cmci_mask) & 1 << i) 643 cmci_update(mode, i, valid, &rec); 644 #endif 645 } 646 if (mode == POLLED) 647 mca_fill_freelist(); 648 return (mode == MCE ? recoverable : count); 649 } 650 651 /* 652 * Scan the machine check banks on all CPUs by binding to each CPU in 653 * turn. If any of the CPUs contained new machine check records, log 654 * them to the console. 655 */ 656 static void 657 mca_scan_cpus(void *context, int pending) 658 { 659 struct mca_internal *mca; 660 struct thread *td; 661 int count, cpu; 662 663 mca_fill_freelist(); 664 td = curthread; 665 count = 0; 666 thread_lock(td); 667 CPU_FOREACH(cpu) { 668 sched_bind(td, cpu); 669 thread_unlock(td); 670 count += mca_scan(POLLED); 671 thread_lock(td); 672 sched_unbind(td); 673 } 674 thread_unlock(td); 675 if (count != 0) { 676 mtx_lock_spin(&mca_lock); 677 STAILQ_FOREACH(mca, &mca_records, link) { 678 if (!mca->logged) { 679 mca->logged = 1; 680 mca_log(&mca->rec); 681 } 682 } 683 mtx_unlock_spin(&mca_lock); 684 } 685 } 686 687 static void 688 mca_periodic_scan(void *arg) 689 { 690 691 taskqueue_enqueue_fast(mca_tq, &mca_scan_task); 692 callout_reset(&mca_timer, mca_ticks * hz, mca_periodic_scan, NULL); 693 } 694 695 static int 696 sysctl_mca_scan(SYSCTL_HANDLER_ARGS) 697 { 698 int error, i; 699 700 i = 0; 701 error = sysctl_handle_int(oidp, &i, 0, req); 702 if (error) 703 return (error); 704 if (i) 705 taskqueue_enqueue_fast(mca_tq, &mca_scan_task); 706 return (0); 707 } 708 709 static void 710 mca_createtq(void *dummy) 711 { 712 if (mca_banks <= 0) 713 return; 714 715 mca_tq = taskqueue_create_fast("mca", M_WAITOK, 716 taskqueue_thread_enqueue, &mca_tq); 717 taskqueue_start_threads(&mca_tq, 1, PI_SWI(SWI_TQ), "mca taskq"); 718 } 719 SYSINIT(mca_createtq, SI_SUB_CONFIGURE, SI_ORDER_ANY, mca_createtq, NULL); 720 721 static void 722 mca_startup(void *dummy) 723 { 724 725 if (mca_banks <= 0) 726 return; 727 728 callout_reset(&mca_timer, mca_ticks * hz, mca_periodic_scan, NULL); 729 } 730 SYSINIT(mca_startup, SI_SUB_SMP, SI_ORDER_ANY, mca_startup, NULL); 731 732 #ifdef DEV_APIC 733 static void 734 cmci_setup(void) 735 { 736 int i; 737 738 cmc_state = malloc((mp_maxid + 1) * sizeof(struct cmc_state *), M_MCA, 739 M_WAITOK); 740 for (i = 0; i <= mp_maxid; i++) 741 cmc_state[i] = malloc(sizeof(struct cmc_state) * mca_banks, 742 M_MCA, M_WAITOK | M_ZERO); 743 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO, 744 "cmc_throttle", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 745 &cmc_throttle, 0, sysctl_positive_int, "I", 746 "Interval in seconds to throttle corrected MC interrupts"); 747 } 748 #endif 749 750 static void 751 mca_setup(uint64_t mcg_cap) 752 { 753 754 /* 755 * On AMD Family 10h processors, unless logging of level one TLB 756 * parity (L1TP) errors is disabled, enable the recommended workaround 757 * for Erratum 383. 758 */ 759 if (cpu_vendor_id == CPU_VENDOR_AMD && 760 CPUID_TO_FAMILY(cpu_id) == 0x10 && amd10h_L1TP) 761 workaround_erratum383 = 1; 762 763 mca_banks = mcg_cap & MCG_CAP_COUNT; 764 mtx_init(&mca_lock, "mca", NULL, MTX_SPIN); 765 STAILQ_INIT(&mca_records); 766 TASK_INIT(&mca_scan_task, 0, mca_scan_cpus, NULL); 767 callout_init(&mca_timer, CALLOUT_MPSAFE); 768 STAILQ_INIT(&mca_freelist); 769 TASK_INIT(&mca_refill_task, 0, mca_refill, NULL); 770 mca_fill_freelist(); 771 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO, 772 "count", CTLFLAG_RD, (int *)(uintptr_t)&mca_count, 0, 773 "Record count"); 774 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO, 775 "interval", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, &mca_ticks, 776 0, sysctl_positive_int, "I", 777 "Periodic interval in seconds to scan for machine checks"); 778 SYSCTL_ADD_NODE(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO, 779 "records", CTLFLAG_RD, sysctl_mca_records, "Machine check records"); 780 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO, 781 "force_scan", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, NULL, 0, 782 sysctl_mca_scan, "I", "Force an immediate scan for machine checks"); 783 #ifdef DEV_APIC 784 if (mcg_cap & MCG_CAP_CMCI_P) 785 cmci_setup(); 786 #endif 787 } 788 789 #ifdef DEV_APIC 790 /* 791 * See if we should monitor CMCI for this bank. If CMCI_EN is already 792 * set in MC_CTL2, then another CPU is responsible for this bank, so 793 * ignore it. If CMCI_EN returns zero after being set, then this bank 794 * does not support CMCI_EN. If this CPU sets CMCI_EN, then it should 795 * now monitor this bank. 796 */ 797 static void 798 cmci_monitor(int i) 799 { 800 struct cmc_state *cc; 801 uint64_t ctl; 802 803 KASSERT(i < mca_banks, ("CPU %d has more MC banks", PCPU_GET(cpuid))); 804 805 ctl = rdmsr(MSR_MC_CTL2(i)); 806 if (ctl & MC_CTL2_CMCI_EN) 807 /* Already monitored by another CPU. */ 808 return; 809 810 /* Set the threshold to one event for now. */ 811 ctl &= ~MC_CTL2_THRESHOLD; 812 ctl |= MC_CTL2_CMCI_EN | 1; 813 wrmsr(MSR_MC_CTL2(i), ctl); 814 ctl = rdmsr(MSR_MC_CTL2(i)); 815 if (!(ctl & MC_CTL2_CMCI_EN)) 816 /* This bank does not support CMCI. */ 817 return; 818 819 cc = &cmc_state[PCPU_GET(cpuid)][i]; 820 821 /* Determine maximum threshold. */ 822 ctl &= ~MC_CTL2_THRESHOLD; 823 ctl |= 0x7fff; 824 wrmsr(MSR_MC_CTL2(i), ctl); 825 ctl = rdmsr(MSR_MC_CTL2(i)); 826 cc->max_threshold = ctl & MC_CTL2_THRESHOLD; 827 828 /* Start off with a threshold of 1. */ 829 ctl &= ~MC_CTL2_THRESHOLD; 830 ctl |= 1; 831 wrmsr(MSR_MC_CTL2(i), ctl); 832 833 /* Mark this bank as monitored. */ 834 PCPU_SET(cmci_mask, PCPU_GET(cmci_mask) | 1 << i); 835 } 836 837 /* 838 * For resume, reset the threshold for any banks we monitor back to 839 * one and throw away the timestamp of the last interrupt. 840 */ 841 static void 842 cmci_resume(int i) 843 { 844 struct cmc_state *cc; 845 uint64_t ctl; 846 847 KASSERT(i < mca_banks, ("CPU %d has more MC banks", PCPU_GET(cpuid))); 848 849 /* Ignore banks not monitored by this CPU. */ 850 if (!(PCPU_GET(cmci_mask) & 1 << i)) 851 return; 852 853 cc = &cmc_state[PCPU_GET(cpuid)][i]; 854 cc->last_intr = -ticks; 855 ctl = rdmsr(MSR_MC_CTL2(i)); 856 ctl &= ~MC_CTL2_THRESHOLD; 857 ctl |= MC_CTL2_CMCI_EN | 1; 858 wrmsr(MSR_MC_CTL2(i), ctl); 859 } 860 #endif 861 862 /* 863 * Initializes per-CPU machine check registers and enables corrected 864 * machine check interrupts. 865 */ 866 static void 867 _mca_init(int boot) 868 { 869 uint64_t mcg_cap; 870 uint64_t ctl, mask; 871 int i, skip; 872 873 /* MCE is required. */ 874 if (!mca_enabled || !(cpu_feature & CPUID_MCE)) 875 return; 876 877 if (cpu_feature & CPUID_MCA) { 878 if (boot) 879 PCPU_SET(cmci_mask, 0); 880 881 mcg_cap = rdmsr(MSR_MCG_CAP); 882 if (mcg_cap & MCG_CAP_CTL_P) 883 /* Enable MCA features. */ 884 wrmsr(MSR_MCG_CTL, MCG_CTL_ENABLE); 885 if (PCPU_GET(cpuid) == 0 && boot) 886 mca_setup(mcg_cap); 887 888 /* 889 * Disable logging of level one TLB parity (L1TP) errors by 890 * the data cache as an alternative workaround for AMD Family 891 * 10h Erratum 383. Unlike the recommended workaround, there 892 * is no performance penalty to this workaround. However, 893 * L1TP errors will go unreported. 894 */ 895 if (cpu_vendor_id == CPU_VENDOR_AMD && 896 CPUID_TO_FAMILY(cpu_id) == 0x10 && !amd10h_L1TP) { 897 mask = rdmsr(MSR_MC0_CTL_MASK); 898 if ((mask & (1UL << 5)) == 0) 899 wrmsr(MSR_MC0_CTL_MASK, mask | (1UL << 5)); 900 } 901 for (i = 0; i < (mcg_cap & MCG_CAP_COUNT); i++) { 902 /* By default enable logging of all errors. */ 903 ctl = 0xffffffffffffffffUL; 904 skip = 0; 905 906 if (cpu_vendor_id == CPU_VENDOR_INTEL) { 907 /* 908 * For P6 models before Nehalem MC0_CTL is 909 * always enabled and reserved. 910 */ 911 if (i == 0 && CPUID_TO_FAMILY(cpu_id) == 0x6 912 && CPUID_TO_MODEL(cpu_id) < 0x1a) 913 skip = 1; 914 } else if (cpu_vendor_id == CPU_VENDOR_AMD) { 915 /* BKDG for Family 10h: unset GartTblWkEn. */ 916 if (i == 4 && CPUID_TO_FAMILY(cpu_id) >= 0xf) 917 ctl &= ~(1UL << 10); 918 } 919 920 if (!skip) 921 wrmsr(MSR_MC_CTL(i), ctl); 922 923 #ifdef DEV_APIC 924 if (mcg_cap & MCG_CAP_CMCI_P) { 925 if (boot) 926 cmci_monitor(i); 927 else 928 cmci_resume(i); 929 } 930 #endif 931 932 /* Clear all errors. */ 933 wrmsr(MSR_MC_STATUS(i), 0); 934 } 935 936 #ifdef DEV_APIC 937 if (PCPU_GET(cmci_mask) != 0 && boot) 938 lapic_enable_cmc(); 939 #endif 940 } 941 942 load_cr4(rcr4() | CR4_MCE); 943 } 944 945 /* Must be executed on each CPU during boot. */ 946 void 947 mca_init(void) 948 { 949 950 _mca_init(1); 951 } 952 953 /* Must be executed on each CPU during resume. */ 954 void 955 mca_resume(void) 956 { 957 958 _mca_init(0); 959 } 960 961 /* 962 * The machine check registers for the BSP cannot be initialized until 963 * the local APIC is initialized. This happens at SI_SUB_CPU, 964 * SI_ORDER_SECOND. 965 */ 966 static void 967 mca_init_bsp(void *arg __unused) 968 { 969 970 mca_init(); 971 } 972 SYSINIT(mca_init_bsp, SI_SUB_CPU, SI_ORDER_ANY, mca_init_bsp, NULL); 973 974 /* Called when a machine check exception fires. */ 975 void 976 mca_intr(void) 977 { 978 uint64_t mcg_status; 979 int old_count, recoverable; 980 981 if (!(cpu_feature & CPUID_MCA)) { 982 /* 983 * Just print the values of the old Pentium registers 984 * and panic. 985 */ 986 printf("MC Type: 0x%jx Address: 0x%jx\n", 987 (uintmax_t)rdmsr(MSR_P5_MC_TYPE), 988 (uintmax_t)rdmsr(MSR_P5_MC_ADDR)); 989 panic("Machine check"); 990 } 991 992 /* Scan the banks and check for any non-recoverable errors. */ 993 old_count = mca_count; 994 recoverable = mca_scan(MCE); 995 mcg_status = rdmsr(MSR_MCG_STATUS); 996 if (!(mcg_status & MCG_STATUS_RIPV)) 997 recoverable = 0; 998 999 if (!recoverable) { 1000 /* 1001 * Wait for at least one error to be logged before 1002 * panic'ing. Some errors will assert a machine check 1003 * on all CPUs, but only certain CPUs will find a valid 1004 * bank to log. 1005 */ 1006 while (mca_count == old_count) 1007 cpu_spinwait(); 1008 1009 panic("Unrecoverable machine check exception"); 1010 } 1011 1012 /* Clear MCIP. */ 1013 wrmsr(MSR_MCG_STATUS, mcg_status & ~MCG_STATUS_MCIP); 1014 } 1015 1016 #ifdef DEV_APIC 1017 /* Called for a CMCI (correctable machine check interrupt). */ 1018 void 1019 cmc_intr(void) 1020 { 1021 struct mca_internal *mca; 1022 int count; 1023 1024 /* 1025 * Serialize MCA bank scanning to prevent collisions from 1026 * sibling threads. 1027 */ 1028 count = mca_scan(CMCI); 1029 1030 /* If we found anything, log them to the console. */ 1031 if (count != 0) { 1032 mtx_lock_spin(&mca_lock); 1033 STAILQ_FOREACH(mca, &mca_records, link) { 1034 if (!mca->logged) { 1035 mca->logged = 1; 1036 mca_log(&mca->rec); 1037 } 1038 } 1039 mtx_unlock_spin(&mca_lock); 1040 } 1041 } 1042 #endif
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