Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/x86/x86/mptable.c
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1 /*- 2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3 * Copyright (c) 1996, by Steve Passe 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. The name of the developer may NOT be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_mptable_force_htt.h" 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/kernel.h> 35 #include <sys/malloc.h> 36 37 #include <vm/vm.h> 38 #include <vm/vm_param.h> 39 #include <vm/pmap.h> 40 41 #include <machine/apicreg.h> 42 #include <machine/frame.h> 43 #include <machine/intr_machdep.h> 44 #include <machine/apicvar.h> 45 #include <machine/md_var.h> 46 #include <machine/mptable.h> 47 #include <machine/specialreg.h> 48 49 #include <dev/pci/pcivar.h> 50 51 /* string defined by the Intel MP Spec as identifying the MP table */ 52 #define MP_SIG 0x5f504d5f /* _MP_ */ 53 54 #ifdef __amd64__ 55 #define MAX_LAPIC_ID 63 /* Max local APIC ID for HTT fixup */ 56 #define SI_SUB_MPTBL (SI_SUB_TUNABLES - 1) 57 #else 58 #define MAX_LAPIC_ID 31 /* Max local APIC ID for HTT fixup */ 59 #define SI_SUB_MPTBL (SI_SUB_CPU - 1) 60 #endif 61 62 #ifdef PC98 63 #define BIOS_BASE (0xe8000) 64 #define BIOS_SIZE (0x18000) 65 #else 66 #define BIOS_BASE (0xf0000) 67 #define BIOS_SIZE (0x10000) 68 #endif 69 #define BIOS_COUNT (BIOS_SIZE/4) 70 71 typedef void mptable_entry_handler(u_char *entry, void *arg); 72 73 static basetable_entry basetable_entry_types[] = 74 { 75 {0, 20, "Processor"}, 76 {1, 8, "Bus"}, 77 {2, 8, "I/O APIC"}, 78 {3, 8, "I/O INT"}, 79 {4, 8, "Local INT"} 80 }; 81 82 typedef struct BUSDATA { 83 u_char bus_id; 84 enum busTypes bus_type; 85 } bus_datum; 86 87 typedef struct INTDATA { 88 u_char int_type; 89 u_short int_flags; 90 u_char src_bus_id; 91 u_char src_bus_irq; 92 u_char dst_apic_id; 93 u_char dst_apic_int; 94 u_char int_vector; 95 } io_int, local_int; 96 97 typedef struct BUSTYPENAME { 98 u_char type; 99 char name[7]; 100 } bus_type_name; 101 102 /* From MP spec v1.4, table 4-8. */ 103 static bus_type_name bus_type_table[] = 104 { 105 {UNKNOWN_BUSTYPE, "CBUS "}, 106 {UNKNOWN_BUSTYPE, "CBUSII"}, 107 {EISA, "EISA "}, 108 {UNKNOWN_BUSTYPE, "FUTURE"}, 109 {UNKNOWN_BUSTYPE, "INTERN"}, 110 {ISA, "ISA "}, 111 {UNKNOWN_BUSTYPE, "MBI "}, 112 {UNKNOWN_BUSTYPE, "MBII "}, 113 {MCA, "MCA "}, 114 {UNKNOWN_BUSTYPE, "MPI "}, 115 {UNKNOWN_BUSTYPE, "MPSA "}, 116 {UNKNOWN_BUSTYPE, "NUBUS "}, 117 {PCI, "PCI "}, 118 {UNKNOWN_BUSTYPE, "PCMCIA"}, 119 {UNKNOWN_BUSTYPE, "TC "}, 120 {UNKNOWN_BUSTYPE, "VL "}, 121 {UNKNOWN_BUSTYPE, "VME "}, 122 {UNKNOWN_BUSTYPE, "XPRESS"} 123 }; 124 125 /* From MP spec v1.4, table 5-1. */ 126 static int default_data[7][5] = 127 { 128 /* nbus, id0, type0, id1, type1 */ 129 {1, 0, ISA, 255, NOBUS}, 130 {1, 0, EISA, 255, NOBUS}, 131 {1, 0, EISA, 255, NOBUS}, 132 {1, 0, MCA, 255, NOBUS}, 133 {2, 0, ISA, 1, PCI}, 134 {2, 0, EISA, 1, PCI}, 135 {2, 0, MCA, 1, PCI} 136 }; 137 138 struct pci_probe_table_args { 139 u_char bus; 140 u_char found; 141 }; 142 143 struct pci_route_interrupt_args { 144 u_char bus; /* Source bus. */ 145 u_char irq; /* Source slot:pin. */ 146 int vector; /* Return value. */ 147 }; 148 149 static mpfps_t mpfps; 150 static mpcth_t mpct; 151 static void *ioapics[MAX_APIC_ID + 1]; 152 static bus_datum *busses; 153 static int mptable_nioapics, mptable_nbusses, mptable_maxbusid; 154 static int pci0 = -1; 155 156 static MALLOC_DEFINE(M_MPTABLE, "mptable", "MP Table Items"); 157 158 static enum intr_polarity conforming_polarity(u_char src_bus, 159 u_char src_bus_irq); 160 static enum intr_trigger conforming_trigger(u_char src_bus, u_char src_bus_irq); 161 static enum intr_polarity intentry_polarity(int_entry_ptr intr); 162 static enum intr_trigger intentry_trigger(int_entry_ptr intr); 163 static int lookup_bus_type(char *name); 164 static void mptable_count_items(void); 165 static void mptable_count_items_handler(u_char *entry, void *arg); 166 #ifdef MPTABLE_FORCE_HTT 167 static void mptable_hyperthread_fixup(u_int id_mask); 168 #endif 169 static void mptable_parse_apics_and_busses(void); 170 static void mptable_parse_apics_and_busses_handler(u_char *entry, 171 void *arg); 172 static void mptable_parse_default_config_ints(void); 173 static void mptable_parse_ints(void); 174 static void mptable_parse_ints_handler(u_char *entry, void *arg); 175 static void mptable_parse_io_int(int_entry_ptr intr); 176 static void mptable_parse_local_int(int_entry_ptr intr); 177 static void mptable_pci_probe_table_handler(u_char *entry, void *arg); 178 static void mptable_pci_route_interrupt_handler(u_char *entry, void *arg); 179 static void mptable_pci_setup(void); 180 static int mptable_probe(void); 181 static int mptable_probe_cpus(void); 182 static void mptable_probe_cpus_handler(u_char *entry, void *arg __unused); 183 static void mptable_register(void *dummy); 184 static int mptable_setup_local(void); 185 static int mptable_setup_io(void); 186 static void mptable_walk_table(mptable_entry_handler *handler, void *arg); 187 static int search_for_sig(u_int32_t target, int count); 188 189 static struct apic_enumerator mptable_enumerator = { 190 "MPTable", 191 mptable_probe, 192 mptable_probe_cpus, 193 mptable_setup_local, 194 mptable_setup_io 195 }; 196 197 /* 198 * look for the MP spec signature 199 */ 200 201 static int 202 search_for_sig(u_int32_t target, int count) 203 { 204 int x; 205 u_int32_t *addr = (u_int32_t *) (KERNBASE + target); 206 207 for (x = 0; x < count; x += 4) 208 if (addr[x] == MP_SIG) 209 /* make array index a byte index */ 210 return (target + (x * sizeof(u_int32_t))); 211 return (-1); 212 } 213 214 static int 215 lookup_bus_type(char *name) 216 { 217 int x; 218 219 for (x = 0; x < MAX_BUSTYPE; ++x) 220 if (strncmp(bus_type_table[x].name, name, 6) == 0) 221 return (bus_type_table[x].type); 222 223 return (UNKNOWN_BUSTYPE); 224 } 225 226 /* 227 * Look for an Intel MP spec table (ie, SMP capable hardware). 228 */ 229 static int 230 mptable_probe(void) 231 { 232 int x; 233 u_long segment; 234 u_int32_t target; 235 236 /* see if EBDA exists */ 237 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) { 238 /* search first 1K of EBDA */ 239 target = (u_int32_t) (segment << 4); 240 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 241 goto found; 242 } else { 243 /* last 1K of base memory, effective 'top of base' passed in */ 244 target = (u_int32_t) ((basemem * 1024) - 0x400); 245 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 246 goto found; 247 } 248 249 /* search the BIOS */ 250 target = (u_int32_t) BIOS_BASE; 251 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) 252 goto found; 253 254 /* nothing found */ 255 return (ENXIO); 256 257 found: 258 mpfps = (mpfps_t)(KERNBASE + x); 259 260 /* Map in the configuration table if it exists. */ 261 if (mpfps->config_type != 0) { 262 if (bootverbose) 263 printf( 264 "MP Table version 1.%d found using Default Configuration %d\n", 265 mpfps->spec_rev, mpfps->config_type); 266 if (mpfps->config_type != 5 && mpfps->config_type != 6) { 267 printf( 268 "MP Table Default Configuration %d is unsupported\n", 269 mpfps->config_type); 270 return (ENXIO); 271 } 272 mpct = NULL; 273 } else { 274 if ((uintptr_t)mpfps->pap >= 1024 * 1024) { 275 printf("%s: Unable to map MP Configuration Table\n", 276 __func__); 277 return (ENXIO); 278 } 279 mpct = (mpcth_t)(KERNBASE + (uintptr_t)mpfps->pap); 280 if (mpct->base_table_length + (uintptr_t)mpfps->pap >= 281 1024 * 1024) { 282 printf("%s: Unable to map end of MP Config Table\n", 283 __func__); 284 return (ENXIO); 285 } 286 if (mpct->signature[0] != 'P' || mpct->signature[1] != 'C' || 287 mpct->signature[2] != 'M' || mpct->signature[3] != 'P') { 288 printf("%s: MP Config Table has bad signature: %c%c%c%c\n", 289 __func__, mpct->signature[0], mpct->signature[1], 290 mpct->signature[2], mpct->signature[3]); 291 return (ENXIO); 292 } 293 if (bootverbose) 294 printf( 295 "MP Configuration Table version 1.%d found at %p\n", 296 mpct->spec_rev, mpct); 297 } 298 299 return (-100); 300 } 301 302 /* 303 * Run through the MP table enumerating CPUs. 304 */ 305 static int 306 mptable_probe_cpus(void) 307 { 308 u_int cpu_mask; 309 310 /* Is this a pre-defined config? */ 311 if (mpfps->config_type != 0) { 312 lapic_create(0, 1); 313 lapic_create(1, 0); 314 } else { 315 cpu_mask = 0; 316 mptable_walk_table(mptable_probe_cpus_handler, &cpu_mask); 317 #ifdef MPTABLE_FORCE_HTT 318 mptable_hyperthread_fixup(cpu_mask); 319 #endif 320 } 321 return (0); 322 } 323 324 /* 325 * Initialize the local APIC on the BSP. 326 */ 327 static int 328 mptable_setup_local(void) 329 { 330 vm_paddr_t addr; 331 332 /* Is this a pre-defined config? */ 333 printf("MPTable: <"); 334 if (mpfps->config_type != 0) { 335 addr = DEFAULT_APIC_BASE; 336 printf("Default Configuration %d", mpfps->config_type); 337 } else { 338 addr = mpct->apic_address; 339 printf("%.*s %.*s", (int)sizeof(mpct->oem_id), mpct->oem_id, 340 (int)sizeof(mpct->product_id), mpct->product_id); 341 } 342 printf(">\n"); 343 lapic_init(addr); 344 return (0); 345 } 346 347 /* 348 * Run through the MP table enumerating I/O APICs. 349 */ 350 static int 351 mptable_setup_io(void) 352 { 353 int i; 354 u_char byte; 355 356 /* First, we count individual items and allocate arrays. */ 357 mptable_count_items(); 358 busses = malloc((mptable_maxbusid + 1) * sizeof(bus_datum), M_MPTABLE, 359 M_WAITOK); 360 for (i = 0; i <= mptable_maxbusid; i++) 361 busses[i].bus_type = NOBUS; 362 363 /* Second, we run through adding I/O APIC's and busses. */ 364 mptable_parse_apics_and_busses(); 365 366 /* Third, we run through the table tweaking interrupt sources. */ 367 mptable_parse_ints(); 368 369 /* Fourth, we register all the I/O APIC's. */ 370 for (i = 0; i <= MAX_APIC_ID; i++) 371 if (ioapics[i] != NULL) 372 ioapic_register(ioapics[i]); 373 374 /* Fifth, we setup data structures to handle PCI interrupt routing. */ 375 mptable_pci_setup(); 376 377 /* Finally, we throw the switch to enable the I/O APIC's. */ 378 if (mpfps->mpfb2 & MPFB2_IMCR_PRESENT) { 379 outb(0x22, 0x70); /* select IMCR */ 380 byte = inb(0x23); /* current contents */ 381 byte |= 0x01; /* mask external INTR */ 382 outb(0x23, byte); /* disconnect 8259s/NMI */ 383 } 384 385 return (0); 386 } 387 388 static void 389 mptable_register(void *dummy __unused) 390 { 391 392 apic_register_enumerator(&mptable_enumerator); 393 } 394 SYSINIT(mptable_register, SI_SUB_MPTBL, SI_ORDER_FIRST, mptable_register, NULL); 395 396 /* 397 * Call the handler routine for each entry in the MP config table. 398 */ 399 static void 400 mptable_walk_table(mptable_entry_handler *handler, void *arg) 401 { 402 u_int i; 403 u_char *entry; 404 405 entry = (u_char *)(mpct + 1); 406 for (i = 0; i < mpct->entry_count; i++) { 407 switch (*entry) { 408 case MPCT_ENTRY_PROCESSOR: 409 case MPCT_ENTRY_IOAPIC: 410 case MPCT_ENTRY_BUS: 411 case MPCT_ENTRY_INT: 412 case MPCT_ENTRY_LOCAL_INT: 413 break; 414 default: 415 panic("%s: Unknown MP Config Entry %d\n", __func__, 416 (int)*entry); 417 } 418 handler(entry, arg); 419 entry += basetable_entry_types[*entry].length; 420 } 421 } 422 423 static void 424 mptable_probe_cpus_handler(u_char *entry, void *arg) 425 { 426 proc_entry_ptr proc; 427 u_int *cpu_mask; 428 429 switch (*entry) { 430 case MPCT_ENTRY_PROCESSOR: 431 proc = (proc_entry_ptr)entry; 432 if (proc->cpu_flags & PROCENTRY_FLAG_EN) { 433 lapic_create(proc->apic_id, proc->cpu_flags & 434 PROCENTRY_FLAG_BP); 435 if (proc->apic_id < MAX_LAPIC_ID) { 436 cpu_mask = (u_int *)arg; 437 *cpu_mask |= (1ul << proc->apic_id); 438 } 439 } 440 break; 441 } 442 } 443 444 static void 445 mptable_count_items_handler(u_char *entry, void *arg __unused) 446 { 447 io_apic_entry_ptr apic; 448 bus_entry_ptr bus; 449 450 switch (*entry) { 451 case MPCT_ENTRY_BUS: 452 bus = (bus_entry_ptr)entry; 453 mptable_nbusses++; 454 if (bus->bus_id > mptable_maxbusid) 455 mptable_maxbusid = bus->bus_id; 456 break; 457 case MPCT_ENTRY_IOAPIC: 458 apic = (io_apic_entry_ptr)entry; 459 if (apic->apic_flags & IOAPICENTRY_FLAG_EN) 460 mptable_nioapics++; 461 break; 462 } 463 } 464 465 /* 466 * Count items in the table. 467 */ 468 static void 469 mptable_count_items(void) 470 { 471 472 /* Is this a pre-defined config? */ 473 if (mpfps->config_type != 0) { 474 mptable_nioapics = 1; 475 switch (mpfps->config_type) { 476 case 1: 477 case 2: 478 case 3: 479 case 4: 480 mptable_nbusses = 1; 481 break; 482 case 5: 483 case 6: 484 case 7: 485 mptable_nbusses = 2; 486 break; 487 default: 488 panic("Unknown pre-defined MP Table config type %d", 489 mpfps->config_type); 490 } 491 mptable_maxbusid = mptable_nbusses - 1; 492 } else 493 mptable_walk_table(mptable_count_items_handler, NULL); 494 } 495 496 /* 497 * Add a bus or I/O APIC from an entry in the table. 498 */ 499 static void 500 mptable_parse_apics_and_busses_handler(u_char *entry, void *arg __unused) 501 { 502 io_apic_entry_ptr apic; 503 bus_entry_ptr bus; 504 enum busTypes bus_type; 505 int i; 506 507 508 switch (*entry) { 509 case MPCT_ENTRY_BUS: 510 bus = (bus_entry_ptr)entry; 511 bus_type = lookup_bus_type(bus->bus_type); 512 if (bus_type == UNKNOWN_BUSTYPE) { 513 printf("MPTable: Unknown bus %d type \"", bus->bus_id); 514 for (i = 0; i < 6; i++) 515 printf("%c", bus->bus_type[i]); 516 printf("\"\n"); 517 } 518 busses[bus->bus_id].bus_id = bus->bus_id; 519 busses[bus->bus_id].bus_type = bus_type; 520 break; 521 case MPCT_ENTRY_IOAPIC: 522 apic = (io_apic_entry_ptr)entry; 523 if (!(apic->apic_flags & IOAPICENTRY_FLAG_EN)) 524 break; 525 if (apic->apic_id > MAX_APIC_ID) 526 panic("%s: I/O APIC ID %d too high", __func__, 527 apic->apic_id); 528 if (ioapics[apic->apic_id] != NULL) 529 panic("%s: Double APIC ID %d", __func__, 530 apic->apic_id); 531 ioapics[apic->apic_id] = ioapic_create(apic->apic_address, 532 apic->apic_id, -1); 533 break; 534 default: 535 break; 536 } 537 } 538 539 /* 540 * Enumerate I/O APIC's and busses. 541 */ 542 static void 543 mptable_parse_apics_and_busses(void) 544 { 545 546 /* Is this a pre-defined config? */ 547 if (mpfps->config_type != 0) { 548 ioapics[2] = ioapic_create(DEFAULT_IO_APIC_BASE, 2, 0); 549 busses[0].bus_id = 0; 550 busses[0].bus_type = default_data[mpfps->config_type - 1][2]; 551 if (mptable_nbusses > 1) { 552 busses[1].bus_id = 1; 553 busses[1].bus_type = 554 default_data[mpfps->config_type - 1][4]; 555 } 556 } else 557 mptable_walk_table(mptable_parse_apics_and_busses_handler, 558 NULL); 559 } 560 561 /* 562 * Determine conforming polarity for a given bus type. 563 */ 564 static enum intr_polarity 565 conforming_polarity(u_char src_bus, u_char src_bus_irq) 566 { 567 568 KASSERT(src_bus <= mptable_maxbusid, ("bus id %d too large", src_bus)); 569 switch (busses[src_bus].bus_type) { 570 case ISA: 571 case EISA: 572 return (INTR_POLARITY_HIGH); 573 case PCI: 574 return (INTR_POLARITY_LOW); 575 default: 576 panic("%s: unknown bus type %d", __func__, 577 busses[src_bus].bus_type); 578 } 579 } 580 581 /* 582 * Determine conforming trigger for a given bus type. 583 */ 584 static enum intr_trigger 585 conforming_trigger(u_char src_bus, u_char src_bus_irq) 586 { 587 588 KASSERT(src_bus <= mptable_maxbusid, ("bus id %d too large", src_bus)); 589 switch (busses[src_bus].bus_type) { 590 case ISA: 591 #ifndef PC98 592 if (elcr_found) 593 return (elcr_read_trigger(src_bus_irq)); 594 else 595 #endif 596 return (INTR_TRIGGER_EDGE); 597 case PCI: 598 return (INTR_TRIGGER_LEVEL); 599 #ifndef PC98 600 case EISA: 601 KASSERT(src_bus_irq < 16, ("Invalid EISA IRQ %d", src_bus_irq)); 602 KASSERT(elcr_found, ("Missing ELCR")); 603 return (elcr_read_trigger(src_bus_irq)); 604 #endif 605 default: 606 panic("%s: unknown bus type %d", __func__, 607 busses[src_bus].bus_type); 608 } 609 } 610 611 static enum intr_polarity 612 intentry_polarity(int_entry_ptr intr) 613 { 614 615 switch (intr->int_flags & INTENTRY_FLAGS_POLARITY) { 616 case INTENTRY_FLAGS_POLARITY_CONFORM: 617 return (conforming_polarity(intr->src_bus_id, 618 intr->src_bus_irq)); 619 case INTENTRY_FLAGS_POLARITY_ACTIVEHI: 620 return (INTR_POLARITY_HIGH); 621 case INTENTRY_FLAGS_POLARITY_ACTIVELO: 622 return (INTR_POLARITY_LOW); 623 default: 624 panic("Bogus interrupt flags"); 625 } 626 } 627 628 static enum intr_trigger 629 intentry_trigger(int_entry_ptr intr) 630 { 631 632 switch (intr->int_flags & INTENTRY_FLAGS_TRIGGER) { 633 case INTENTRY_FLAGS_TRIGGER_CONFORM: 634 return (conforming_trigger(intr->src_bus_id, 635 intr->src_bus_irq)); 636 case INTENTRY_FLAGS_TRIGGER_EDGE: 637 return (INTR_TRIGGER_EDGE); 638 case INTENTRY_FLAGS_TRIGGER_LEVEL: 639 return (INTR_TRIGGER_LEVEL); 640 default: 641 panic("Bogus interrupt flags"); 642 } 643 } 644 645 /* 646 * Parse an interrupt entry for an I/O interrupt routed to a pin on an I/O APIC. 647 */ 648 static void 649 mptable_parse_io_int(int_entry_ptr intr) 650 { 651 void *ioapic; 652 u_int pin, apic_id; 653 654 apic_id = intr->dst_apic_id; 655 if (intr->dst_apic_id == 0xff) { 656 /* 657 * An APIC ID of 0xff means that the interrupt is connected 658 * to the specified pin on all I/O APICs in the system. If 659 * there is only one I/O APIC, then use that APIC to route 660 * the interrupts. If there is more than one I/O APIC, then 661 * punt. 662 */ 663 if (mptable_nioapics == 1) { 664 apic_id = 0; 665 while (ioapics[apic_id] == NULL) 666 apic_id++; 667 } else { 668 printf( 669 "MPTable: Ignoring global interrupt entry for pin %d\n", 670 intr->dst_apic_int); 671 return; 672 } 673 } 674 if (apic_id > MAX_APIC_ID) { 675 printf("MPTable: Ignoring interrupt entry for ioapic%d\n", 676 intr->dst_apic_id); 677 return; 678 } 679 ioapic = ioapics[apic_id]; 680 if (ioapic == NULL) { 681 printf( 682 "MPTable: Ignoring interrupt entry for missing ioapic%d\n", 683 apic_id); 684 return; 685 } 686 pin = intr->dst_apic_int; 687 switch (intr->int_type) { 688 case INTENTRY_TYPE_INT: 689 switch (busses[intr->src_bus_id].bus_type) { 690 case NOBUS: 691 panic("interrupt from missing bus"); 692 case ISA: 693 case EISA: 694 if (busses[intr->src_bus_id].bus_type == ISA) 695 ioapic_set_bus(ioapic, pin, APIC_BUS_ISA); 696 else 697 ioapic_set_bus(ioapic, pin, APIC_BUS_EISA); 698 if (intr->src_bus_irq == pin) 699 break; 700 ioapic_remap_vector(ioapic, pin, intr->src_bus_irq); 701 if (ioapic_get_vector(ioapic, intr->src_bus_irq) == 702 intr->src_bus_irq) 703 ioapic_disable_pin(ioapic, intr->src_bus_irq); 704 break; 705 case PCI: 706 ioapic_set_bus(ioapic, pin, APIC_BUS_PCI); 707 break; 708 default: 709 ioapic_set_bus(ioapic, pin, APIC_BUS_UNKNOWN); 710 break; 711 } 712 break; 713 case INTENTRY_TYPE_NMI: 714 ioapic_set_nmi(ioapic, pin); 715 break; 716 case INTENTRY_TYPE_SMI: 717 ioapic_set_smi(ioapic, pin); 718 break; 719 case INTENTRY_TYPE_EXTINT: 720 ioapic_set_extint(ioapic, pin); 721 break; 722 default: 723 panic("%s: invalid interrupt entry type %d\n", __func__, 724 intr->int_type); 725 } 726 if (intr->int_type == INTENTRY_TYPE_INT || 727 (intr->int_flags & INTENTRY_FLAGS_TRIGGER) != 728 INTENTRY_FLAGS_TRIGGER_CONFORM) 729 ioapic_set_triggermode(ioapic, pin, intentry_trigger(intr)); 730 if (intr->int_type == INTENTRY_TYPE_INT || 731 (intr->int_flags & INTENTRY_FLAGS_POLARITY) != 732 INTENTRY_FLAGS_POLARITY_CONFORM) 733 ioapic_set_polarity(ioapic, pin, intentry_polarity(intr)); 734 } 735 736 /* 737 * Parse an interrupt entry for a local APIC LVT pin. 738 */ 739 static void 740 mptable_parse_local_int(int_entry_ptr intr) 741 { 742 u_int apic_id, pin; 743 744 if (intr->dst_apic_id == 0xff) 745 apic_id = APIC_ID_ALL; 746 else 747 apic_id = intr->dst_apic_id; 748 if (intr->dst_apic_int == 0) 749 pin = LVT_LINT0; 750 else 751 pin = LVT_LINT1; 752 switch (intr->int_type) { 753 case INTENTRY_TYPE_INT: 754 #if 1 755 printf( 756 "MPTable: Ignoring vectored local interrupt for LINTIN%d vector %d\n", 757 intr->dst_apic_int, intr->src_bus_irq); 758 return; 759 #else 760 lapic_set_lvt_mode(apic_id, pin, APIC_LVT_DM_FIXED); 761 break; 762 #endif 763 case INTENTRY_TYPE_NMI: 764 lapic_set_lvt_mode(apic_id, pin, APIC_LVT_DM_NMI); 765 break; 766 case INTENTRY_TYPE_SMI: 767 lapic_set_lvt_mode(apic_id, pin, APIC_LVT_DM_SMI); 768 break; 769 case INTENTRY_TYPE_EXTINT: 770 lapic_set_lvt_mode(apic_id, pin, APIC_LVT_DM_EXTINT); 771 break; 772 default: 773 panic("%s: invalid interrupt entry type %d\n", __func__, 774 intr->int_type); 775 } 776 if ((intr->int_flags & INTENTRY_FLAGS_TRIGGER) != 777 INTENTRY_FLAGS_TRIGGER_CONFORM) 778 lapic_set_lvt_triggermode(apic_id, pin, 779 intentry_trigger(intr)); 780 if ((intr->int_flags & INTENTRY_FLAGS_POLARITY) != 781 INTENTRY_FLAGS_POLARITY_CONFORM) 782 lapic_set_lvt_polarity(apic_id, pin, intentry_polarity(intr)); 783 } 784 785 /* 786 * Parse interrupt entries. 787 */ 788 static void 789 mptable_parse_ints_handler(u_char *entry, void *arg __unused) 790 { 791 int_entry_ptr intr; 792 793 intr = (int_entry_ptr)entry; 794 switch (*entry) { 795 case MPCT_ENTRY_INT: 796 mptable_parse_io_int(intr); 797 break; 798 case MPCT_ENTRY_LOCAL_INT: 799 mptable_parse_local_int(intr); 800 break; 801 } 802 } 803 804 /* 805 * Configure interrupt pins for a default configuration. For details see 806 * Table 5-2 in Section 5 of the MP Table specification. 807 */ 808 static void 809 mptable_parse_default_config_ints(void) 810 { 811 struct INTENTRY entry; 812 int pin; 813 814 /* 815 * All default configs route IRQs from bus 0 to the first 16 pins 816 * of the first I/O APIC with an APIC ID of 2. 817 */ 818 entry.type = MPCT_ENTRY_INT; 819 entry.int_flags = INTENTRY_FLAGS_POLARITY_CONFORM | 820 INTENTRY_FLAGS_TRIGGER_CONFORM; 821 entry.src_bus_id = 0; 822 entry.dst_apic_id = 2; 823 824 /* Run through all 16 pins. */ 825 for (pin = 0; pin < 16; pin++) { 826 entry.dst_apic_int = pin; 827 switch (pin) { 828 case 0: 829 /* Pin 0 is an ExtINT pin. */ 830 entry.int_type = INTENTRY_TYPE_EXTINT; 831 break; 832 case 2: 833 /* IRQ 0 is routed to pin 2. */ 834 entry.int_type = INTENTRY_TYPE_INT; 835 entry.src_bus_irq = 0; 836 break; 837 default: 838 /* All other pins are identity mapped. */ 839 entry.int_type = INTENTRY_TYPE_INT; 840 entry.src_bus_irq = pin; 841 break; 842 } 843 mptable_parse_io_int(&entry); 844 } 845 846 /* Certain configs disable certain pins. */ 847 if (mpfps->config_type == 7) 848 ioapic_disable_pin(ioapics[2], 0); 849 if (mpfps->config_type == 2) { 850 ioapic_disable_pin(ioapics[2], 2); 851 ioapic_disable_pin(ioapics[2], 13); 852 } 853 } 854 855 /* 856 * Configure the interrupt pins 857 */ 858 static void 859 mptable_parse_ints(void) 860 { 861 862 /* Is this a pre-defined config? */ 863 if (mpfps->config_type != 0) { 864 /* Configure LINT pins. */ 865 lapic_set_lvt_mode(APIC_ID_ALL, LVT_LINT0, APIC_LVT_DM_EXTINT); 866 lapic_set_lvt_mode(APIC_ID_ALL, LVT_LINT1, APIC_LVT_DM_NMI); 867 868 /* Configure I/O APIC pins. */ 869 mptable_parse_default_config_ints(); 870 } else 871 mptable_walk_table(mptable_parse_ints_handler, NULL); 872 } 873 874 #ifdef MPTABLE_FORCE_HTT 875 /* 876 * Perform a hyperthreading "fix-up" to enumerate any logical CPU's 877 * that aren't already listed in the table. 878 * 879 * XXX: We assume that all of the physical CPUs in the 880 * system have the same number of logical CPUs. 881 * 882 * XXX: We assume that APIC ID's are allocated such that 883 * the APIC ID's for a physical processor are aligned 884 * with the number of logical CPU's in the processor. 885 */ 886 static void 887 mptable_hyperthread_fixup(u_int id_mask) 888 { 889 u_int i, id, logical_cpus; 890 891 /* Nothing to do if there is no HTT support. */ 892 if ((cpu_feature & CPUID_HTT) == 0) 893 return; 894 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 895 if (logical_cpus <= 1) 896 return; 897 898 /* 899 * For each APIC ID of a CPU that is set in the mask, 900 * scan the other candidate APIC ID's for this 901 * physical processor. If any of those ID's are 902 * already in the table, then kill the fixup. 903 */ 904 for (id = 0; id <= MAX_LAPIC_ID; id++) { 905 if ((id_mask & 1 << id) == 0) 906 continue; 907 /* First, make sure we are on a logical_cpus boundary. */ 908 if (id % logical_cpus != 0) 909 return; 910 for (i = id + 1; i < id + logical_cpus; i++) 911 if ((id_mask & 1 << i) != 0) 912 return; 913 } 914 915 /* 916 * Ok, the ID's checked out, so perform the fixup by 917 * adding the logical CPUs. 918 */ 919 while ((id = ffs(id_mask)) != 0) { 920 id--; 921 for (i = id + 1; i < id + logical_cpus; i++) { 922 if (bootverbose) 923 printf( 924 "MPTable: Adding logical CPU %d from main CPU %d\n", 925 i, id); 926 lapic_create(i, 0); 927 } 928 id_mask &= ~(1 << id); 929 } 930 } 931 #endif /* MPTABLE_FORCE_HTT */ 932 933 /* 934 * Support code for routing PCI interrupts using the MP Table. 935 */ 936 static void 937 mptable_pci_setup(void) 938 { 939 int i; 940 941 /* 942 * Find the first pci bus and call it 0. Panic if pci0 is not 943 * bus zero and there are multiple PCI busses. 944 */ 945 for (i = 0; i <= mptable_maxbusid; i++) 946 if (busses[i].bus_type == PCI) { 947 if (pci0 == -1) 948 pci0 = i; 949 else if (pci0 != 0) 950 panic( 951 "MPTable contains multiple PCI busses but no PCI bus 0"); 952 } 953 } 954 955 static void 956 mptable_pci_probe_table_handler(u_char *entry, void *arg) 957 { 958 struct pci_probe_table_args *args; 959 int_entry_ptr intr; 960 961 if (*entry != MPCT_ENTRY_INT) 962 return; 963 intr = (int_entry_ptr)entry; 964 args = (struct pci_probe_table_args *)arg; 965 KASSERT(args->bus <= mptable_maxbusid, 966 ("bus %d is too big", args->bus)); 967 KASSERT(busses[args->bus].bus_type == PCI, ("probing for non-PCI bus")); 968 if (intr->src_bus_id == args->bus) 969 args->found = 1; 970 } 971 972 int 973 mptable_pci_probe_table(int bus) 974 { 975 struct pci_probe_table_args args; 976 977 if (bus < 0) 978 return (EINVAL); 979 if (mpct == NULL || pci0 == -1 || pci0 + bus > mptable_maxbusid) 980 return (ENXIO); 981 if (busses[pci0 + bus].bus_type != PCI) 982 return (ENXIO); 983 args.bus = pci0 + bus; 984 args.found = 0; 985 mptable_walk_table(mptable_pci_probe_table_handler, &args); 986 if (args.found == 0) 987 return (ENXIO); 988 return (0); 989 } 990 991 static void 992 mptable_pci_route_interrupt_handler(u_char *entry, void *arg) 993 { 994 struct pci_route_interrupt_args *args; 995 int_entry_ptr intr; 996 int vector; 997 998 if (*entry != MPCT_ENTRY_INT) 999 return; 1000 intr = (int_entry_ptr)entry; 1001 args = (struct pci_route_interrupt_args *)arg; 1002 if (intr->src_bus_id != args->bus || intr->src_bus_irq != args->irq) 1003 return; 1004 1005 /* Make sure the APIC maps to a known APIC. */ 1006 KASSERT(ioapics[intr->dst_apic_id] != NULL, 1007 ("No I/O APIC %d to route interrupt to", intr->dst_apic_id)); 1008 1009 /* 1010 * Look up the vector for this APIC / pin combination. If we 1011 * have previously matched an entry for this PCI IRQ but it 1012 * has the same vector as this entry, just return. Otherwise, 1013 * we use the vector for this APIC / pin combination. 1014 */ 1015 vector = ioapic_get_vector(ioapics[intr->dst_apic_id], 1016 intr->dst_apic_int); 1017 if (args->vector == vector) 1018 return; 1019 KASSERT(args->vector == -1, 1020 ("Multiple IRQs for PCI interrupt %d.%d.INT%c: %d and %d\n", 1021 args->bus, args->irq >> 2, 'A' + (args->irq & 0x3), args->vector, 1022 vector)); 1023 args->vector = vector; 1024 } 1025 1026 int 1027 mptable_pci_route_interrupt(device_t pcib, device_t dev, int pin) 1028 { 1029 struct pci_route_interrupt_args args; 1030 int slot; 1031 1032 /* Like ACPI, pin numbers are 0-3, not 1-4. */ 1033 pin--; 1034 KASSERT(pci0 != -1, ("do not know how to route PCI interrupts")); 1035 args.bus = pci_get_bus(dev) + pci0; 1036 slot = pci_get_slot(dev); 1037 1038 /* 1039 * PCI interrupt entries in the MP Table encode both the slot and 1040 * pin into the IRQ with the pin being the two least significant 1041 * bits, the slot being the next five bits, and the most significant 1042 * bit being reserved. 1043 */ 1044 args.irq = slot << 2 | pin; 1045 args.vector = -1; 1046 mptable_walk_table(mptable_pci_route_interrupt_handler, &args); 1047 if (args.vector < 0) { 1048 device_printf(pcib, "unable to route slot %d INT%c\n", slot, 1049 'A' + pin); 1050 return (PCI_INVALID_IRQ); 1051 } 1052 if (bootverbose) 1053 device_printf(pcib, "slot %d INT%c routed to irq %d\n", slot, 1054 'A' + pin, args.vector); 1055 return (args.vector); 1056 }
Cache object: b729418ba50c663991f50c051483ae05
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