The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/xen/interface/arch-arm.h

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    1 /******************************************************************************
    2  * arch-arm.h
    3  *
    4  * Guest OS interface to ARM Xen.
    5  *
    6  * Permission is hereby granted, free of charge, to any person obtaining a copy
    7  * of this software and associated documentation files (the "Software"), to
    8  * deal in the Software without restriction, including without limitation the
    9  * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
   10  * sell copies of the Software, and to permit persons to whom the Software is
   11  * furnished to do so, subject to the following conditions:
   12  *
   13  * The above copyright notice and this permission notice shall be included in
   14  * all copies or substantial portions of the Software.
   15  *
   16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
   17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
   19  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
   20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
   21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
   22  * DEALINGS IN THE SOFTWARE.
   23  *
   24  * Copyright 2011 (C) Citrix Systems
   25  */
   26 
   27 #ifndef __XEN_PUBLIC_ARCH_ARM_H__
   28 #define __XEN_PUBLIC_ARCH_ARM_H__
   29 
   30 /* hypercall calling convention
   31  * ----------------------------
   32  *
   33  * A hypercall is issued using the ARM HVC instruction.
   34  *
   35  * A hypercall can take up to 5 arguments. These are passed in
   36  * registers, the first argument in r0, the second argument in r1, the
   37  * third in r2, the forth in r3 and the fifth in r4.
   38  *
   39  * The hypercall number is passed in r12.
   40  *
   41  * The HVC ISS must contain a Xen specific TAG: XEN_HYPERCALL_TAG.
   42  *
   43  * The return value is in r0.
   44  *
   45  * The hypercall will clobber r12 and the argument registers used by
   46  * that hypercall (except r0 which is the return value) i.e. a 2
   47  * argument hypercall will clobber r1 and a 4 argument hypercall will
   48  * clobber r1, r2 and r3.
   49  *
   50  */
   51 
   52 #define XEN_HYPERCALL_TAG   0XEA1
   53 
   54 
   55 #ifndef __ASSEMBLY__
   56 #define ___DEFINE_XEN_GUEST_HANDLE(name, type) \
   57     typedef struct { type *p; } __guest_handle_ ## name
   58 
   59 #define __DEFINE_XEN_GUEST_HANDLE(name, type) \
   60     ___DEFINE_XEN_GUEST_HANDLE(name, type);   \
   61     ___DEFINE_XEN_GUEST_HANDLE(const_##name, const type)
   62 #define DEFINE_XEN_GUEST_HANDLE(name)   __DEFINE_XEN_GUEST_HANDLE(name, name)
   63 #define __XEN_GUEST_HANDLE(name)        __guest_handle_ ## name
   64 #define XEN_GUEST_HANDLE(name)          __XEN_GUEST_HANDLE(name)
   65 #define set_xen_guest_handle_raw(hnd, val)  do { (hnd).p = val; } while (0)
   66 #ifdef __XEN_TOOLS__
   67 #define get_xen_guest_handle(val, hnd)  do { val = (hnd).p; } while (0)
   68 #endif
   69 #define set_xen_guest_handle(hnd, val) set_xen_guest_handle_raw(hnd, val)
   70 
   71 struct cpu_user_regs
   72 {
   73     uint32_t r0;
   74     uint32_t r1;
   75     uint32_t r2;
   76     uint32_t r3;
   77     uint32_t r4;
   78     uint32_t r5;
   79     uint32_t r6;
   80     uint32_t r7;
   81     uint32_t r8;
   82     uint32_t r9;
   83     uint32_t r10;
   84     union {
   85         uint32_t r11;
   86         uint32_t fp;
   87     };
   88     uint32_t r12;
   89 
   90     uint32_t sp; /* r13 - SP: Valid for Hyp. frames only, o/w banked (see below) */
   91 
   92     /* r14 - LR: is the same physical register as LR_usr */
   93     union {
   94         uint32_t lr; /* r14 - LR: Valid for Hyp. Same physical register as lr_usr. */
   95         uint32_t lr_usr;
   96     };
   97 
   98     uint32_t pc; /* Return IP */
   99     uint32_t cpsr; /* Return mode */
  100     uint32_t pad0; /* Doubleword-align the kernel half of the frame */
  101 
  102     /* Outer guest frame only from here on... */
  103 
  104     uint32_t r8_fiq, r9_fiq, r10_fiq, r11_fiq, r12_fiq;
  105 
  106     uint32_t sp_usr; /* LR_usr is the same register as LR, see above */
  107 
  108     uint32_t sp_svc, sp_abt, sp_und, sp_irq, sp_fiq;
  109     uint32_t lr_svc, lr_abt, lr_und, lr_irq, lr_fiq;
  110 
  111     uint32_t spsr_svc, spsr_abt, spsr_und, spsr_irq, spsr_fiq;
  112 
  113     uint32_t pad1; /* Doubleword-align the user half of the frame */
  114 };
  115 typedef struct cpu_user_regs cpu_user_regs_t;
  116 DEFINE_XEN_GUEST_HANDLE(cpu_user_regs_t);
  117 
  118 typedef uint64_t xen_pfn_t;
  119 #define PRI_xen_pfn PRIx64
  120 
  121 /* Maximum number of virtual CPUs in legacy multi-processor guests. */
  122 /* Only one. All other VCPUS must use VCPUOP_register_vcpu_info */
  123 #define XEN_LEGACY_MAX_VCPUS 1
  124 
  125 typedef uint32_t xen_ulong_t;
  126 
  127 struct vcpu_guest_context {
  128     struct cpu_user_regs user_regs;         /* User-level CPU registers     */
  129 
  130     uint32_t sctlr;
  131     uint32_t ttbr0, ttbr1, ttbcr;
  132 };
  133 typedef struct vcpu_guest_context vcpu_guest_context_t;
  134 DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t);
  135 
  136 struct arch_vcpu_info { };
  137 typedef struct arch_vcpu_info arch_vcpu_info_t;
  138 
  139 struct arch_shared_info { };
  140 typedef struct arch_shared_info arch_shared_info_t;
  141 typedef uint64_t xen_callback_t;
  142 
  143 #endif /* ifndef __ASSEMBLY __ */
  144 
  145 /* PSR bits (CPSR, SPSR)*/
  146 
  147 /* 0-4: Mode */
  148 #define PSR_MODE_MASK 0x1f
  149 #define PSR_MODE_USR 0x10
  150 #define PSR_MODE_FIQ 0x11
  151 #define PSR_MODE_IRQ 0x12
  152 #define PSR_MODE_SVC 0x13
  153 #define PSR_MODE_MON 0x16
  154 #define PSR_MODE_ABT 0x17
  155 #define PSR_MODE_HYP 0x1a
  156 #define PSR_MODE_UND 0x1b
  157 #define PSR_MODE_SYS 0x1f
  158 
  159 #define PSR_THUMB       (1<<5)        /* Thumb Mode enable */
  160 #define PSR_FIQ_MASK    (1<<6)        /* Fast Interrupt mask */
  161 #define PSR_IRQ_MASK    (1<<7)        /* Interrupt mask */
  162 #define PSR_ABT_MASK    (1<<8)        /* Asynchronous Abort mask */
  163 #define PSR_BIG_ENDIAN  (1<<9)        /* Big Endian Mode */
  164 #define PSR_JAZELLE     (1<<24)       /* Jazelle Mode */
  165 
  166 #endif /*  __XEN_PUBLIC_ARCH_ARM_H__ */
  167 
  168 /*
  169  * Local variables:
  170  * mode: C
  171  * c-set-style: "BSD"
  172  * c-basic-offset: 4
  173  * tab-width: 4
  174  * indent-tabs-mode: nil
  175  * End:
  176  */

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