The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/xen/interface/hvm/params.h

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    1 /*
    2  * Permission is hereby granted, free of charge, to any person obtaining a copy
    3  * of this software and associated documentation files (the "Software"), to
    4  * deal in the Software without restriction, including without limitation the
    5  * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
    6  * sell copies of the Software, and to permit persons to whom the Software is
    7  * furnished to do so, subject to the following conditions:
    8  *
    9  * The above copyright notice and this permission notice shall be included in
   10  * all copies or substantial portions of the Software.
   11  *
   12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
   13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
   15  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
   16  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
   17  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
   18  * DEALINGS IN THE SOFTWARE.
   19  *
   20  * Copyright (c) 2007, Keir Fraser
   21  */
   22 
   23 #ifndef __XEN_PUBLIC_HVM_PARAMS_H__
   24 #define __XEN_PUBLIC_HVM_PARAMS_H__
   25 
   26 #include "hvm_op.h"
   27 
   28 /*
   29  * Parameter space for HVMOP_{set,get}_param.
   30  */
   31 
   32 /*
   33  * How should CPU0 event-channel notifications be delivered?
   34  * val[63:56] == 0: val[55:0] is a delivery GSI (Global System Interrupt).
   35  * val[63:56] == 1: val[55:0] is a delivery PCI INTx line, as follows:
   36  *                  Domain = val[47:32], Bus  = val[31:16],
   37  *                  DevFn  = val[15: 8], IntX = val[ 1: 0]
   38  * val[63:56] == 2: val[7:0] is a vector number, check for
   39  *                  XENFEAT_hvm_callback_vector to know if this delivery
   40  *                  method is available.
   41  * If val == 0 then CPU0 event-channel notifications are not delivered.
   42  */
   43 #define HVM_PARAM_CALLBACK_IRQ 0
   44 
   45 /*
   46  * These are not used by Xen. They are here for convenience of HVM-guest
   47  * xenbus implementations.
   48  */
   49 #define HVM_PARAM_STORE_PFN    1
   50 #define HVM_PARAM_STORE_EVTCHN 2
   51 
   52 #define HVM_PARAM_PAE_ENABLED  4
   53 
   54 #define HVM_PARAM_IOREQ_PFN    5
   55 
   56 #define HVM_PARAM_BUFIOREQ_PFN 6
   57 #define HVM_PARAM_BUFIOREQ_EVTCHN 26
   58 
   59 #if defined(__i386__) || defined(__x86_64__)
   60 
   61 /*
   62  * Viridian enlightenments
   63  *
   64  * (See http://download.microsoft.com/download/A/B/4/AB43A34E-BDD0-4FA6-BDEF-79EEF16E880B/Hypervisor%20Top%20Level%20Functional%20Specification%20v4.0.docx)
   65  *
   66  * To expose viridian enlightenments to the guest set this parameter
   67  * to the desired feature mask. The base feature set must be present
   68  * in any valid feature mask.
   69  */
   70 #define HVM_PARAM_VIRIDIAN     9
   71 
   72 /* Base+Freq viridian feature sets:
   73  *
   74  * - Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL)
   75  * - APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR)
   76  * - Virtual Processor index MSR (HV_X64_MSR_VP_INDEX)
   77  * - Timer frequency MSRs (HV_X64_MSR_TSC_FREQUENCY and
   78  *   HV_X64_MSR_APIC_FREQUENCY)
   79  */
   80 #define _HVMPV_base_freq 0
   81 #define HVMPV_base_freq  (1 << _HVMPV_base_freq)
   82 
   83 /* Feature set modifications */
   84 
   85 /* Disable timer frequency MSRs (HV_X64_MSR_TSC_FREQUENCY and
   86  * HV_X64_MSR_APIC_FREQUENCY).
   87  * This modification restores the viridian feature set to the
   88  * original 'base' set exposed in releases prior to Xen 4.4.
   89  */
   90 #define _HVMPV_no_freq 1
   91 #define HVMPV_no_freq  (1 << _HVMPV_no_freq)
   92 
   93 /* Enable Partition Time Reference Counter (HV_X64_MSR_TIME_REF_COUNT) */
   94 #define _HVMPV_time_ref_count 2
   95 #define HVMPV_time_ref_count  (1 << _HVMPV_time_ref_count)
   96 
   97 /* Enable Reference TSC Page (HV_X64_MSR_REFERENCE_TSC) */
   98 #define _HVMPV_reference_tsc 3
   99 #define HVMPV_reference_tsc  (1 << _HVMPV_reference_tsc)
  100 
  101 #define HVMPV_feature_mask \
  102         (HVMPV_base_freq | \
  103          HVMPV_no_freq | \
  104          HVMPV_time_ref_count | \
  105          HVMPV_reference_tsc)
  106 
  107 #endif
  108 
  109 /*
  110  * Set mode for virtual timers (currently x86 only):
  111  *  delay_for_missed_ticks (default):
  112  *   Do not advance a vcpu's time beyond the correct delivery time for
  113  *   interrupts that have been missed due to preemption. Deliver missed
  114  *   interrupts when the vcpu is rescheduled and advance the vcpu's virtual
  115  *   time stepwise for each one.
  116  *  no_delay_for_missed_ticks:
  117  *   As above, missed interrupts are delivered, but guest time always tracks
  118  *   wallclock (i.e., real) time while doing so.
  119  *  no_missed_ticks_pending:
  120  *   No missed interrupts are held pending. Instead, to ensure ticks are
  121  *   delivered at some non-zero rate, if we detect missed ticks then the
  122  *   internal tick alarm is not disabled if the VCPU is preempted during the
  123  *   next tick period.
  124  *  one_missed_tick_pending:
  125  *   Missed interrupts are collapsed together and delivered as one 'late tick'.
  126  *   Guest time always tracks wallclock (i.e., real) time.
  127  */
  128 #define HVM_PARAM_TIMER_MODE   10
  129 #define HVMPTM_delay_for_missed_ticks    0
  130 #define HVMPTM_no_delay_for_missed_ticks 1
  131 #define HVMPTM_no_missed_ticks_pending   2
  132 #define HVMPTM_one_missed_tick_pending   3
  133 
  134 /* Boolean: Enable virtual HPET (high-precision event timer)? (x86-only) */
  135 #define HVM_PARAM_HPET_ENABLED 11
  136 
  137 /* Identity-map page directory used by Intel EPT when CR0.PG=0. */
  138 #define HVM_PARAM_IDENT_PT     12
  139 
  140 /* Device Model domain, defaults to 0. */
  141 #define HVM_PARAM_DM_DOMAIN    13
  142 
  143 /* ACPI S state: currently support S0 and S3 on x86. */
  144 #define HVM_PARAM_ACPI_S_STATE 14
  145 
  146 /* TSS used on Intel when CR0.PE=0. */
  147 #define HVM_PARAM_VM86_TSS     15
  148 
  149 /* Boolean: Enable aligning all periodic vpts to reduce interrupts */
  150 #define HVM_PARAM_VPT_ALIGN    16
  151 
  152 /* Console debug shared memory ring and event channel */
  153 #define HVM_PARAM_CONSOLE_PFN    17
  154 #define HVM_PARAM_CONSOLE_EVTCHN 18
  155 
  156 /*
  157  * Select location of ACPI PM1a and TMR control blocks. Currently two locations
  158  * are supported, specified by version 0 or 1 in this parameter:
  159  *   - 0: default, use the old addresses
  160  *        PM1A_EVT == 0x1f40; PM1A_CNT == 0x1f44; PM_TMR == 0x1f48
  161  *   - 1: use the new default qemu addresses
  162  *        PM1A_EVT == 0xb000; PM1A_CNT == 0xb004; PM_TMR == 0xb008
  163  * You can find these address definitions in <hvm/ioreq.h>
  164  */
  165 #define HVM_PARAM_ACPI_IOPORTS_LOCATION 19
  166 
  167 /* Deprecated */
  168 #define HVM_PARAM_MEMORY_EVENT_CR0          20
  169 #define HVM_PARAM_MEMORY_EVENT_CR3          21
  170 #define HVM_PARAM_MEMORY_EVENT_CR4          22
  171 #define HVM_PARAM_MEMORY_EVENT_INT3         23
  172 #define HVM_PARAM_MEMORY_EVENT_SINGLE_STEP  25
  173 #define HVM_PARAM_MEMORY_EVENT_MSR          30
  174 
  175 /* Boolean: Enable nestedhvm (hvm only) */
  176 #define HVM_PARAM_NESTEDHVM    24
  177 
  178 /* Params for the mem event rings */
  179 #define HVM_PARAM_PAGING_RING_PFN   27
  180 #define HVM_PARAM_MONITOR_RING_PFN  28
  181 #define HVM_PARAM_SHARING_RING_PFN  29
  182 
  183 /* SHUTDOWN_* action in case of a triple fault */
  184 #define HVM_PARAM_TRIPLE_FAULT_REASON 31
  185 
  186 #define HVM_PARAM_IOREQ_SERVER_PFN 32
  187 #define HVM_PARAM_NR_IOREQ_SERVER_PAGES 33
  188 
  189 /* Location of the VM Generation ID in guest physical address space. */
  190 #define HVM_PARAM_VM_GENERATION_ID_ADDR 34
  191 
  192 /* Boolean: Enable altp2m */
  193 #define HVM_PARAM_ALTP2M       35
  194 
  195 #define HVM_NR_PARAMS          36
  196 
  197 #endif /* __XEN_PUBLIC_HVM_PARAMS_H__ */

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