The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)

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FreeBSD/Linux Kernel Cross Reference

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[ typedefs ] [ structs ] [ enums ] [ unions ]

4904 definition(s) of typedef

AAC_VMCommand ABM_SOFT_RESET ACPI_EXTENDED_HID_DEVICE_PATH
ACPI_HID_DEVICE_PATH AC_AifCommand AC_AifEventNotifyType
AC_AifJobStatus AC_AifJobType AC_BatteryPlatform
AC_CacheLevel AC_ClusterAifEvent AC_CommitLevel
AC_CpuSubType AC_CpuType AC_FSACommand
AC_FSAStatus AC_FSAVolType AC_FType
AC_FibCommands AC_NVBATTSTATUS AC_NVBATT_TRANSITION
AC_NVSTATUS AC_OemFlavor AC_Platform
ADDRESS_LENGTH_PAIR ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3
ADJUST_DISPLAY_PLL_PARAMETERS ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 ADW_DVC_CFG
ADW_EEPROM ADW_SCSI_REQ_Q ADW_SG_BLOCK
ADW_SOFTC AES_CMAC_CTX AES_CTX
AES_GMAC_CTX AFMT_ACP_TYPE AFMT_AUDIO_CRC_CONTROL_CH_SEL
AFMT_AUDIO_CRC_CONTROL_CONT AFMT_AUDIO_CRC_CONTROL_SOURCE AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD
AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS AFMT_AUDIO_SRC_CONTROL_SELECT
AFMT_HDMI_AUDIO_SEND_MAX_PACKETS AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE AFMT_INTERRUPT_STATUS_CHG_MASK
AFMT_MEM_PWR_DIS_CTRL AFMT_MEM_PWR_FORCE_CTRL AFMT_RAMP_CONTROL0_SIGN
AFMT_VBI_GSP_INDEX AFMT_VBI_PACKET_CONTROL_ACP_SOURCE ALLOW_SR_ON_TRANS_REQ
AMCLOCK_ENABLE AMDGPU_DOORBELL64_ASSIGNMENT AMDGPU_DOORBELL_ASSIGNMENT
AMDGPU_NAVI10_DOORBELL_ASSIGNMENT AMDGPU_VEGA20_DOORBELL_ASSIGNMENT ANY_CTX
AOUT_CRC_CONT_EN AOUT_CRC_SOFT_RESET AOUT_CRC_TEST_EN
AOUT_EN AOUT_FIFO_START_ADDR APG_AUDIO_CRC_CONTROL_CH_SEL
APG_AUDIO_CRC_CONTROL_CONT APG_DBG_ACP_TYPE APG_DBG_AUDIO_DTO_BASE
APG_DBG_AUDIO_DTO_DIV APG_DBG_AUDIO_DTO_MULTI APG_DBG_MUX_SEL
APG_DP_ASP_CHANNEL_COUNT_OVERRIDE APG_MEM_POWER_STATE APG_MEM_PWR_DIS_CTRL
APG_MEM_PWR_FORCE_CTRL APG_PACKET_CONTROL_ACP_SOURCE APG_PACKET_CONTROL_AUDIO_INFO_SOURCE
APG_RAMP_CONTROL_SIGN ARRAY_MODE ASCEEP_CONFIG
ASC_MIN_SG_HEAD ASC_QDONE_INFO ASC_RISC_Q
ASC_RISC_SG_LIST_Q ASC_SCSIQ_1 ASC_SCSIQ_2
ASC_SCSIQ_3 ASC_SCSIQ_4 ASC_SCSI_BIOS_REQ_Q
ASC_SCSI_Q ASC_SCSI_REQ_Q ASC_SG_HEAD
ASC_SG_LIST ASC_SG_LIST_Q ASC_SOFTC
ASIC_ENCODER_INFO ASIC_INIT_CLOCK_PARAMETERS ASIC_INIT_PARAMETERS
ASIC_INIT_PARAMETERS_V1_2 ASIC_INIT_PS_ALLOCATION ASIC_INIT_PS_ALLOCATION_V1_2
ASIC_TRANSMITTER_INFO ASIC_TRANSMITTER_INFO_V2 ATAPI_DEVICE_PATH
ATOM_ADJUST_MEMORY_CLOCK_FREQ ATOM_ANALOG_TV_INFO ATOM_ANALOG_TV_INFO_V1_2
ATOM_ASIC_INTERNAL_SS_INFO ATOM_ASIC_INTERNAL_SS_INFO_V2 ATOM_ASIC_INTERNAL_SS_INFO_V3
ATOM_ASIC_MVDD_INFO ATOM_ASIC_PROFILE_VOLTAGE ATOM_ASIC_PROFILING_INFO
ATOM_ASIC_PROFILING_INFO_V2_1 ATOM_ASIC_PROFILING_INFO_V3_1 ATOM_ASIC_PROFILING_INFO_V3_2
ATOM_ASIC_PROFILING_INFO_V3_3 ATOM_ASIC_PROFILING_INFO_V3_4 ATOM_ASIC_PROFILING_INFO_V3_5
ATOM_ASIC_PROFILING_INFO_V3_6 ATOM_ASIC_SS_ASSIGNMENT ATOM_ASIC_SS_ASSIGNMENT_V2
ATOM_ASIC_SS_ASSIGNMENT_V3 ATOM_AVAILABLE_SCLK_LIST ATOM_BIOS_INT_TVSTD_MODE
ATOM_BRACKET_LAYOUT_RECORD ATOM_CLK_VOLT_CAPABILITY ATOM_CLK_VOLT_CAPABILITY_V2
ATOM_COMMON_RECORD_HEADER ATOM_COMMON_ROM_COMMAND_TABLE_HEADER ATOM_COMMON_TABLE_HEADER
ATOM_COMPONENT_VIDEO_INFO ATOM_COMPONENT_VIDEO_INFO_V21 ATOM_COMPUTE_CLOCK_FREQ
ATOM_CONNECTOR_AUXDDC_LUT_RECORD ATOM_CONNECTOR_CF_RECORD ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD
ATOM_CONNECTOR_DEVICE_TAG ATOM_CONNECTOR_DEVICE_TAG_RECORD ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD
ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD ATOM_CONNECTOR_HARDCODE_DTD_RECORD ATOM_CONNECTOR_HPDPIN_LUT_RECORD
ATOM_CONNECTOR_INC_SRC_BITMAP ATOM_CONNECTOR_INFO ATOM_CONNECTOR_INFO_ACCESS
ATOM_CONNECTOR_INFO_I2C ATOM_CONNECTOR_LAYOUT_INFO ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD
ATOM_CONNECTOR_REMOTE_CAP_RECORD ATOM_DAC_INFO ATOM_DIG_ENCODER_CONFIG_V2
ATOM_DIG_ENCODER_CONFIG_V3 ATOM_DIG_ENCODER_CONFIG_V4 ATOM_DIG_TRANSMITTER_CONFIG_V2
ATOM_DIG_TRANSMITTER_CONFIG_V3 ATOM_DIG_TRANSMITTER_CONFIG_V4 ATOM_DIG_TRANSMITTER_CONFIG_V5
ATOM_DISPLAY_DEVICE_PRIORITY_INFO ATOM_DISPLAY_EXTERNAL_OBJECT_PATH ATOM_DISPLAY_OBJECT_PATH
ATOM_DISPLAY_OBJECT_PATH_TABLE ATOM_DISP_CLOCK_ID ATOM_DISP_OUT_INFO
ATOM_DISP_OUT_INFO_V2 ATOM_DISP_OUT_INFO_V3 ATOM_DPCD_INFO
ATOM_DP_CONN_CHANNEL_MAPPING ATOM_DP_VS_MODE ATOM_DP_VS_MODE_V4
ATOM_DRAM_DATA_REMAP ATOM_DTD_FORMAT ATOM_DVI_CONN_CHANNEL_MAPPING
ATOM_ENCODER_ANALOG_ATTRIBUTE ATOM_ENCODER_ATTRIBUTE ATOM_ENCODER_CAP_RECORD
ATOM_ENCODER_CAP_RECORD_V2 ATOM_ENCODER_DIGITAL_ATTRIBUTE ATOM_ENCODER_DVO_CF_RECORD
ATOM_ENCODER_FPGA_CONTROL_RECORD ATOM_EVV_DPM_INFO ATOM_EVV_VOLTAGE_OBJECT_V3
ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO ATOM_FAKE_EDID_PATCH_RECORD ATOM_FIRMWARE_CAPABILITY
ATOM_FIRMWARE_CAPABILITY_ACCESS ATOM_FIRMWARE_INFO ATOM_FIRMWARE_INFO_V1_2
ATOM_FIRMWARE_INFO_V1_3 ATOM_FIRMWARE_INFO_V1_4 ATOM_FIRMWARE_INFO_V2_1
ATOM_FIRMWARE_INFO_V2_2 ATOM_FIRMWARE_VRAM_RESERVE_INFO ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5
ATOM_FUSION_SYSTEM_INFO_V1 ATOM_FUSION_SYSTEM_INFO_V2 ATOM_FUSION_SYSTEM_INFO_V3
ATOM_Fiji_Fan_Table ATOM_Fiji_PowerTune_Table ATOM_GFX_INFO_V2_1
ATOM_GFX_INFO_V2_3 ATOM_GPIO_I2C_ASSIGMENT ATOM_GPIO_I2C_INFO
ATOM_GPIO_INFO ATOM_GPIO_PIN_ASSIGNMENT ATOM_GPIO_PIN_CONTROL_PAIR
ATOM_GPIO_PIN_LUT ATOM_GPIO_VOLTAGE_OBJECT_V3 ATOM_GPU_VIRTUALIZATION_INFO_V2_1
ATOM_HOLE_INFO ATOM_HPD_INT_RECORD ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1
ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1 ATOM_HW_MISC_OPERATION_PS_ALLOCATION ATOM_I2C_DATA_RECORD
ATOM_I2C_DEVICE_SETUP_INFO ATOM_I2C_ID_CONFIG ATOM_I2C_ID_CONFIG_ACCESS
ATOM_I2C_RECORD ATOM_I2C_REG_INFO ATOM_I2C_VOLTAGE_OBJECT_V3
ATOM_INIT_REG_BLOCK ATOM_INIT_REG_INDEX_FORMAT ATOM_INTEGRATED_SYSTEM_INFO
ATOM_INTEGRATED_SYSTEM_INFO_V1_10 ATOM_INTEGRATED_SYSTEM_INFO_V1_7 ATOM_INTEGRATED_SYSTEM_INFO_V1_8
ATOM_INTEGRATED_SYSTEM_INFO_V1_9 ATOM_INTEGRATED_SYSTEM_INFO_V2 ATOM_INTEGRATED_SYSTEM_INFO_V5
ATOM_INTEGRATED_SYSTEM_INFO_V6 ATOM_JTAG_RECORD ATOM_LCD_INFO_V13
ATOM_LCD_MODE_CONTROL_CAP ATOM_LCD_REFRESH_RATE_SUPPORT ATOM_LCD_RTS_RECORD
ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 ATOM_LEAKID_VOLTAGE ATOM_LVDS_INFO
ATOM_LVDS_INFO_V12 ATOM_MASTER_COMMAND_TABLE ATOM_MASTER_DATA_TABLE
ATOM_MASTER_LIST_OF_COMMAND_TABLES ATOM_MASTER_LIST_OF_DATA_TABLES ATOM_MC_INIT_PARAM_TABLE
ATOM_MC_INIT_PARAM_TABLE_V2_1 ATOM_MEMORY_FORMAT ATOM_MEMORY_SETTING_DATA_BLOCK
ATOM_MEMORY_SETTING_ID_CONFIG ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ATOM_MEMORY_TIMING_FORMAT
ATOM_MEMORY_TIMING_FORMAT_V1 ATOM_MEMORY_TIMING_FORMAT_V2 ATOM_MEMORY_TRAINING_INFO
ATOM_MEMORY_TRAINING_INFO_V3_1 ATOM_MEMORY_VENDOR_BLOCK ATOM_MERGED_VOLTAGE_OBJECT_V3
ATOM_MISC_CONTROL_INFO ATOM_MODE_MISC_INFO ATOM_MODE_MISC_INFO_ACCESS
ATOM_MODE_TIMING ATOM_MULTIMEDIA_CAPABILITY_INFO ATOM_MULTIMEDIA_CONFIG_INFO
ATOM_OBJECT ATOM_OBJECT_GPIO_CNTL_RECORD ATOM_OBJECT_HEADER
ATOM_OBJECT_HEADER_V3 ATOM_OBJECT_LINK_RECORD ATOM_OBJECT_TABLE
ATOM_OEM_INFO ATOM_OUTPUT_PROTECTION_RECORD ATOM_PANEL_RESOLUTION_PATCH_RECORD
ATOM_PATCH_RECORD_MODE ATOM_POWERMODE_INFO ATOM_POWERMODE_INFO_V2
ATOM_POWERMODE_INFO_V3 ATOM_POWERPLAY_INFO ATOM_POWERPLAY_INFO_V2
ATOM_POWERPLAY_INFO_V3 ATOM_POWER_SOURCE_INFO ATOM_POWER_SOURCE_OBJECT
ATOM_PPLIB_ACPClk_Voltage_Limit_Record ATOM_PPLIB_ACPClk_Voltage_Limit_Table ATOM_PPLIB_ACP_Table
ATOM_PPLIB_CAC_Leakage_Table ATOM_PPLIB_CI_CLOCK_INFO ATOM_PPLIB_CZ_CLOCK_INFO
ATOM_PPLIB_Clock_Voltage_Dependency_Record ATOM_PPLIB_Clock_Voltage_Dependency_Table ATOM_PPLIB_Clock_Voltage_Limit_Record
ATOM_PPLIB_Clock_Voltage_Limit_Table ATOM_PPLIB_EVERGREEN_CLOCK_INFO ATOM_PPLIB_EXTENDEDHEADER
ATOM_PPLIB_FANTABLE ATOM_PPLIB_FANTABLE2 ATOM_PPLIB_FANTABLE3
ATOM_PPLIB_FANTABLE4 ATOM_PPLIB_FANTABLE5 ATOM_PPLIB_KV_CLOCK_INFO
ATOM_PPLIB_NONCLOCK_INFO ATOM_PPLIB_POWERPLAYTABLE ATOM_PPLIB_POWERPLAYTABLE2
ATOM_PPLIB_POWERPLAYTABLE3 ATOM_PPLIB_POWERPLAYTABLE4 ATOM_PPLIB_POWERPLAYTABLE5
ATOM_PPLIB_POWERTUNE_Table ATOM_PPLIB_POWERTUNE_Table_V1 ATOM_PPLIB_PPM_Table
ATOM_PPLIB_PhaseSheddingLimits_Record ATOM_PPLIB_PhaseSheddingLimits_Table ATOM_PPLIB_R600_CLOCK_INFO
ATOM_PPLIB_RS780_CLOCK_INFO ATOM_PPLIB_SAMClk_Voltage_Limit_Record ATOM_PPLIB_SAMClk_Voltage_Limit_Table
ATOM_PPLIB_SAMU_Table ATOM_PPLIB_SI_CLOCK_INFO ATOM_PPLIB_STATE
ATOM_PPLIB_STATE_V2 ATOM_PPLIB_SUMO_CLOCK_INFO ATOM_PPLIB_THERMALCONTROLLER
ATOM_PPLIB_THERMAL_STATE ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table
ATOM_PPLIB_UVD_Table ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table
ATOM_PPLIB_VCE_State_Record ATOM_PPLIB_VCE_State_Table ATOM_PPLIB_VCE_Table
ATOM_PPLIB_VQ_Budgeting_Record ATOM_PPLIB_VQ_Budgeting_Table ATOM_Polaris10_PCIE_Record
ATOM_Polaris10_PCIE_Table ATOM_Polaris_Fan_Table ATOM_Polaris_PowerTune_Table
ATOM_Polaris_SCLK_Dependency_Record ATOM_Polaris_SCLK_Dependency_Table ATOM_PowerTune_Table
ATOM_REG_INIT_SETTING ATOM_ROM_HEADER ATOM_ROM_HEADER_V2_1
ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD ATOM_ROUTER_DDC_PATH_SELECT_RECORD ATOM_SCLK_FCW_RANGE_ENTRY_V1
ATOM_SERVICE_DESCRIPTION ATOM_SERVICE_INFO ATOM_SMU_INFO_V2_1
ATOM_SPREAD_SPECTRUM_ASSIGNMENT ATOM_SPREAD_SPECTRUM_INFO ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT
ATOM_STANDARD_VESA_TIMING ATOM_STD_FORMAT ATOM_SUPPORTED_DEVICES_INFO
ATOM_SUPPORTED_DEVICES_INFO_2 ATOM_SUPPORTED_DEVICES_INFO_2d1 ATOM_SVID2_VOLTAGE_OBJECT_V3
ATOM_S_MPLL_FB_DIVIDER ATOM_TABLE_ATTRIBUTE ATOM_TABLE_ATTRIBUTE_ACCESS
ATOM_TDP_CONFIG ATOM_TDP_CONFIG_BITS ATOM_TMDS_INFO
ATOM_TV_MODE ATOM_TV_MODE_SCALER_PTR ATOM_Tonga_Fan_Table
ATOM_Tonga_GPIO_Table ATOM_Tonga_Hard_Limit_Record ATOM_Tonga_Hard_Limit_Table
ATOM_Tonga_MCLK_Dependency_Record ATOM_Tonga_MCLK_Dependency_Table ATOM_Tonga_MM_Dependency_Record
ATOM_Tonga_MM_Dependency_Table ATOM_Tonga_PCIE_Record ATOM_Tonga_PCIE_Table
ATOM_Tonga_POWERPLAYTABLE ATOM_Tonga_PPM_Table ATOM_Tonga_PowerTune_Table
ATOM_Tonga_SCLK_Dependency_Record ATOM_Tonga_SCLK_Dependency_Table ATOM_Tonga_State
ATOM_Tonga_State_Array ATOM_Tonga_Thermal_Controller ATOM_Tonga_VCE_State_Record
ATOM_Tonga_VCE_State_Table ATOM_Tonga_Voltage_Lookup_Record ATOM_Tonga_Voltage_Lookup_Table
ATOM_VEGA20_OVERDRIVE8_RECORD ATOM_VEGA20_POWER_SAVING_CLOCK_RECORD ATOM_VESA_TO_EXTENDED_MODE
ATOM_VESA_TO_INTENAL_MODE_LUT ATOM_VOLTAGE_CONTROL ATOM_VOLTAGE_FORMULA
ATOM_VOLTAGE_FORMULA_V2 ATOM_VOLTAGE_INFO ATOM_VOLTAGE_INFO_HEADER
ATOM_VOLTAGE_OBJECT ATOM_VOLTAGE_OBJECT_HEADER_V3 ATOM_VOLTAGE_OBJECT_INFO
ATOM_VOLTAGE_OBJECT_INFO_V2 ATOM_VOLTAGE_OBJECT_INFO_V3_1 ATOM_VOLTAGE_OBJECT_V2
ATOM_VOLTAGE_OBJECT_V3 ATOM_VRAM_GPIO_DETECTION_INFO ATOM_VRAM_INFO_HEADER_V2_1
ATOM_VRAM_INFO_HEADER_V2_2 ATOM_VRAM_INFO_V2 ATOM_VRAM_INFO_V3
ATOM_VRAM_INFO_V4 ATOM_VRAM_MODULE_V1 ATOM_VRAM_MODULE_V2
ATOM_VRAM_MODULE_V3 ATOM_VRAM_MODULE_V4 ATOM_VRAM_MODULE_V5
ATOM_VRAM_MODULE_V6 ATOM_VRAM_MODULE_V7 ATOM_VRAM_MODULE_V8
ATOM_VRAM_USAGE_BY_FIRMWARE ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5 ATOM_Vega10_CLK_Dependency_Record
ATOM_Vega10_DCEFCLK_Dependency_Table ATOM_Vega10_DISPCLK_Dependency_Table ATOM_Vega10_Fan_Table
ATOM_Vega10_Fan_Table_V2 ATOM_Vega10_Fan_Table_V3 ATOM_Vega10_GFXCLK_Dependency_Record
ATOM_Vega10_GFXCLK_Dependency_Record_V2 ATOM_Vega10_GFXCLK_Dependency_Table ATOM_Vega10_Hard_Limit_Record
ATOM_Vega10_Hard_Limit_Table ATOM_Vega10_MCLK_Dependency_Record ATOM_Vega10_MCLK_Dependency_Table
ATOM_Vega10_MM_Dependency_Record ATOM_Vega10_MM_Dependency_Table ATOM_Vega10_PCIE_Record
ATOM_Vega10_PCIE_Table ATOM_Vega10_PHYCLK_Dependency_Table ATOM_Vega10_PIXCLK_Dependency_Table
ATOM_Vega10_POWERPLAYTABLE ATOM_Vega10_PowerTune_Table ATOM_Vega10_PowerTune_Table_V2
ATOM_Vega10_PowerTune_Table_V3 ATOM_Vega10_SOCCLK_Dependency_Table ATOM_Vega10_State
ATOM_Vega10_State_Array ATOM_Vega10_Thermal_Controller ATOM_Vega10_VCE_State_Record
ATOM_Vega10_VCE_State_Table ATOM_Vega10_Voltage_Lookup_Record ATOM_Vega10_Voltage_Lookup_Table
ATOM_Vega12_POWERPLAYTABLE ATOM_Vega20_POWERPLAYTABLE ATOM_XTMDS_INFO
AUDIO_LAYOUT_SELECT AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY
AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE
AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE AZALIA_SOFT_RESET_REFCLK_SOFT_RESET
AZ_CORB_SIZE AZ_GLOBAL_CAPABILITIES AZ_LATENCY_COUNTER_CONTROL
AZ_RIRB_SIZE AZ_RIRB_WRITE_POINTER_RESET AZ_STATE_CHANGE_STATUS
ArrayMode BANK_HEIGHT BANK_WIDTH
BBS_BBS_DEVICE_PATH BIGK_FRAGMENT_SIZE BIOS_CLKID
BLANK_CRTC_PARAMETERS BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN
BLNDV_CONTROL2_PTI_ENABLE BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY BLNDV_CONTROL_BLND_ALPHA_MODE
BLNDV_CONTROL_BLND_FEEDTHROUGH_EN BLNDV_CONTROL_BLND_MODE BLNDV_CONTROL_BLND_MULTIPLIED_MODE
BLNDV_CONTROL_BLND_STEREO_POLARITY BLNDV_CONTROL_BLND_STEREO_TYPE BLNDV_DEBUG_BLND_CNV_MUX_SELECT
BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL
BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE BLNDV_SM_CONTROL2_SM_MODE BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN
BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK
BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK
BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE
BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN BLND_CONTROL2_PTI_ENABLE
BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY BLND_CONTROL_BLND_ALPHA_MODE BLND_CONTROL_BLND_FEEDTHROUGH_EN
BLND_CONTROL_BLND_MODE BLND_CONTROL_BLND_MULTIPLIED_MODE BLND_CONTROL_BLND_STEREO_POLARITY
BLND_CONTROL_BLND_STEREO_TYPE BLND_DEBUG_BLND_CNV_MUX_SELECT BLND_SM_CONTROL2_SM_FIELD_ALTERNATE
BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL BLND_SM_CONTROL2_SM_FRAME_ALTERNATE
BLND_SM_CONTROL2_SM_MODE BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK
BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK
BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK
BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE BOARD_GPIO_TYPE_e
BOOLEAN BOOTPLAYER BORROWBUFFER_MEM_POWER_STATE_ENUM
BUF_DATA_FORMAT BUF_FMT BUF_NUM_FORMAT
BankHeight BankInterleaveSize BankSwapBytes
BankTiling BankWidth BankWidthHeight
BinEventCntl BinMapMode BinSizeExtend
BinningMode BlendOp BlendOpt
BoardTable_t BootConfig BootValues_t
Buffer Byte Bytef
CAMERA_DATA CAMERA_MODULE_INFO CBMode
CBPerfClearFilterSel CBPerfOpFilterSel CBPerfSel
CBRamList CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY
CDROM_DEVICE_PATH CHACHA20_POLY1305_CTX CHAR16
CHAR8 CHA_PERF_SEL CHCG_PERF_SEL
CHC_PERF_SEL CHUB_TC_RET_CREDITS_ENUM CHUNK_SIZE
CLEAR_SMU_INTR CLKGATE_BASE_MODE CLKGATE_SM_MODE
CLOCK_BRANCH_SOFT_RESET CLOCK_CONDITION_REGESTER_INFO CLOCK_CONDITION_SETTING_ENTRY
CLOCK_CONDITION_SETTING_INFO CLOCK_GATING_DISABLE_ENUM CLOCK_GATING_EN
CLOCK_ID_e CLOCK_IDs_e CMC_3DLUT_30BIT_ENUM
CMC_3DLUT_RAM_SEL CMC_3DLUT_SIZE_ENUM CMC_LUT_2_CONFIG_ENUM
CMC_LUT_2_MODE_ENUM CMC_LUT_NUM_SEG CMC_LUT_RAM_SEL
CM_BYPASS CM_COEF_FORMAT_ENUM CM_DATA_SIGNED
CM_EN CM_GAMMA_LUT_MODE_ENUM CM_GAMMA_LUT_PWL_DISABLE_ENUM
CM_GAMMA_LUT_SEL_ENUM CM_GAMUT_REMAP_MODE_ENUM CM_ICSC_MODE_ENUM
CM_LUT_2_CONFIG_ENUM CM_LUT_2_MODE_ENUM CM_LUT_4_CONFIG_ENUM
CM_LUT_4_MODE_ENUM CM_LUT_CONFIG_MODE CM_LUT_NUM_SEG
CM_LUT_RAM_SEL CM_LUT_READ_COLOR_SEL CM_LUT_READ_DBG
CM_PENDING CM_POST_CSC_MODE_ENUM CM_WRITE_BASE_ONLY
CNVC_BYPASS CNVC_COEF_FORMAT_ENUM CNVC_ENABLE
CNVC_PENDING CNV_CSC_BYPASS_ENUM CNV_EYE_SELECT
CNV_FRAME_CAPTURE_EN_ENUM CNV_FRAME_CAPTURE_RATE_ENUM CNV_INTERLACED_FIELD_ORDER_ENUM
CNV_INTERLACED_MODE_ENUM CNV_NEW_CONTENT_ENUM CNV_OUT_BPC_ENUM
CNV_STEREO_POLARITY_ENUM CNV_STEREO_SPLIT_ENUM CNV_STEREO_TYPE_ENUM
CNV_TEST_CRC_CONT_EN_ENUM CNV_TEST_CRC_EN_ENUM CNV_UPDATE_LOCK_ENUM
CNV_UPDATE_PENDING_ENUM CNV_WINDOW_CROP_EN_ENUM CODE
COEF_RAM_SELECT_RD COLOR_KEYER_MODE COL_MAN_DEGAMMA_MODE
COL_MAN_DENORM_CLAMP_CONTROL COL_MAN_DISABLE_MULTIPLE_UPDATE COL_MAN_GAMMA_CORR_CONTROL
COL_MAN_GAMUT_REMAP_MODE COL_MAN_GLOBAL_PASSTHROUGH_ENABLE COL_MAN_INPUTCSC_CONVERT
COL_MAN_INPUTCSC_MODE COL_MAN_INPUTCSC_TYPE COL_MAN_INPUT_GAMMA_MODE
COL_MAN_OUTPUT_CSC_MODE COL_MAN_PRESCALE_MODE COL_MAN_REGAMMA_MODE_CONTROL
COL_MAN_UPDATE_LOCK COMPASSIONATE_DATA COMPAT_LEVEL
COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_7 COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6
COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2
COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_3 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2
COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5
CONTROLLER_DEVICE_PATH CORB_READ_POINTER_RESET CORE_REF_CLK_SOURCE
CPC_LATENCY_STATS_SEL CPC_PERFCOUNT_SEL CPF_LATENCY_STATS_SEL
CPF_PERFCOUNTWINDOW_SEL CPF_PERFCOUNT_SEL CPF_SCRATCH_REG_ATOMIC_OP
CPG_LATENCY_STATS_SEL CPG_PERFCOUNTWINDOW_SEL CPG_PERFCOUNT_SEL
CP_ALPHA_TAG_RAM_SEL CP_DDID_CNTL_MODE CP_DDID_CNTL_SIZE
CP_DDID_CNTL_VMID_SEL CP_ME_ID CP_PERFMON_ENABLE_MODE
CP_PERFMON_STATE CP_PIPE_ID CP_RING_ID
CRC_CUR_BITS_SEL CRC_CUR_SEL CRC_INTERLACE_SEL
CRC_IN_CUR_SEL CRC_IN_PIX_SEL CRC_SRC_SEL
CRC_STEREO_SEL CROB_MEM_PWR_LIGHT_SLEEP_MODE CROSSBAR_FOR_ALPHA
CROSSBAR_FOR_CB_B CROSSBAR_FOR_CR_R CROSSBAR_FOR_Y_G
CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR
CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE CRTC_ADD_PIXEL CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN
CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE
CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY CRTC_CONTROL_CRTC_MASTER_EN
CRTC_CONTROL_CRTC_SOF_PULL_EN CRTC_CONTROL_CRTC_START_POINT_CNTL CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN
CRTC_CRC_CNTL_CRTC_CRC_CONT_EN CRTC_CRC_CNTL_CRTC_CRC_EN CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE
CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT
CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE
CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY CRTC_DROP_PIXEL CRTC_DRR_MODE_DBUF_UPDATE_MODE
CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE
CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE
CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE
CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE
CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT
CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR
CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT
CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR
CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL CRTC_HORZ_REPETITION_COUNT
CRTC_H_SYNC_A_POL CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE
CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE
CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK
CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE
CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK
CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE
CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE
CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR
CRTC_PIXEL_CLOCK_FREQ CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR
CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN
CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE
CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE
CRTC_STEREO_CONTROL_CRTC_STEREO_EN CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY
CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT
CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE
CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT
CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK
CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE
CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE
CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE
CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR
CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR CRTC_V_SYNC_A_POL
CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC
CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL
CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR
CSCNTL_TYPE CSDATA_TYPE CURSOR_2X_MAGNIFY
CURSOR_ENABLE CURSOR_LINES_PER_CHUNK CURSOR_MODE
CURSOR_PERFMON_LATENCY_MEASURE_EN CURSOR_PERFMON_LATENCY_MEASURE_SEL CURSOR_PITCH
CURSOR_REQ_MODE CURSOR_SNOOP CURSOR_STEREO_EN
CURSOR_SURFACE_TMZ CURSOR_SYSTEM CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS
CUR_ENABLE CUR_EXPAND_MODE CUR_INV_CLAMP
CUR_MODE CUR_PENDING CUR_ROM_EN
CUSTOMER_VARIANT_e CUSTOM_DPM_SETTING_e ClockInfoArray
CmaskAddr CmaskCode CmaskMode
ColorArray ColorFormat ColorTransform
CombFunc CompareFrag CompareRef
ConservativeZExport Count CovToShaderSel
CustomDpmSettings_t D3HOTSequence_e DACA_SOFT_RESET
DAC_ENCODER_CONTROL_PARAMETERS DAC_LOAD_DETECTION_PARAMETERS DAC_LOAD_DETECTION_PS_ALLOCATION
DAC_MUX_SELECT DBDataBlock DBSetInfoBlock
DB_CLK_SOFT_RESET DCCG_AUDIO_DTO0_SOURCE_SEL DCCG_AUDIO_DTO2_SOURCE_SEL
DCCG_AUDIO_DTO_SEL DCCG_AUDIO_DTO_USE_512FBR_DTO DCCG_DBG_BLOCK_SEL
DCCG_DBG_CLOCK_SEL DCCG_DBG_EN DCCG_DBG_OUT_BLOCK_SEL
DCCG_DEEP_COLOR_CNTL DCCG_FIFO_ERRDET_OVR_EN DCCG_FIFO_ERRDET_RESET
DCCG_FIFO_ERRDET_STATE DCCG_PERF_CRTC_SELECT DCCG_PERF_MODE_HSYNC
DCCG_PERF_MODE_VSYNC DCCG_PERF_OTG_SELECT DCCG_PERF_RUN
DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE DCHUBBUB_MEM_PWR_DIS_MODE DCHUBBUB_MEM_PWR_MODE
DCIOCHIP_AUXSLAVE_PAD_MODE DCIOCHIP_AUX_ALL_PWR_OK DCIOCHIP_AUX_CSEL0P9
DCIOCHIP_AUX_CSEL1P1 DCIOCHIP_AUX_FALLSLEWSEL DCIOCHIP_AUX_HYS_TUNE
DCIOCHIP_AUX_RECEIVER_SEL DCIOCHIP_AUX_RSEL0P9 DCIOCHIP_AUX_RSEL1P1
DCIOCHIP_AUX_SPIKESEL DCIOCHIP_AUX_VOD_TUNE DCIOCHIP_DVO_VREFPON
DCIOCHIP_DVO_VREFSEL DCIOCHIP_ENABLE_2BIT DCIOCHIP_ENABLE_4BIT
DCIOCHIP_ENABLE_5BIT DCIOCHIP_GPIO_I2C_DRIVE DCIOCHIP_GPIO_I2C_EN
DCIOCHIP_GPIO_I2C_MASK DCIOCHIP_GPIO_MASK_EN DCIOCHIP_HPD_SEL
DCIOCHIP_I2C_COMPSEL DCIOCHIP_I2C_FALLSLEWSEL DCIOCHIP_I2C_RECEIVER_SEL
DCIOCHIP_I2C_VPH_1V2_EN DCIOCHIP_INVERT DCIOCHIP_MASK
DCIOCHIP_MASK_2BIT DCIOCHIP_MASK_4BIT DCIOCHIP_MASK_5BIT
DCIOCHIP_PAD_MODE DCIOCHIP_PD_EN DCIOCHIP_REF_27_SRC_SEL
DCIOCHIP_SPDIF1_IMODE DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN
DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT DCIO_BL_PWM_CNTL_BL_PWM_EN DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN
DCIO_BL_PWM_GRP1_REG_LOCK DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL
DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_RAMP_DIS DCIO_DACA_SOFT_RESET
DCIO_DBG_ASYNC_4BIT_SEL DCIO_DBG_ASYNC_BLOCK_SEL DCIO_DBG_CLOCK_SEL
DCIO_DBG_OUT_12BIT_SEL DCIO_DBG_OUT_PIN_SEL DCIO_DCO_DCFE_EXT_VSYNC_MUX
DCIO_DCO_EXT_VSYNC_MASK DCIO_DCRXPHY_SOFT_RESET DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN
DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN DCIO_DC_GENERICA_SEL
DCIO_DC_GENERICB_SEL DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL
DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL
DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE DCIO_DC_GPIO_MACRO_DEBUG
DCIO_DC_GPIO_VIP_DEBUG DCIO_DC_GPU_TIMER_READ_SELECT DCIO_DC_GPU_TIMER_START_POSITION
DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS DCIO_DC_PAD_EXTERN_SIG_SEL DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL
DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL DCIO_DIO_EXT_VSYNC_MASK DCIO_DIO_OTG_EXT_VSYNC_MUX
DCIO_DPCS_INTERRUPT_MASK DCIO_DPCS_INTERRUPT_TYPE DCIO_DPHY_LANE_SEL
DCIO_DSYNC_SOFT_RESET DCIO_GENLK_CLK_GSL_MASK DCIO_GENLK_VSYNC_GSL_MASK
DCIO_GSL0_GLOBAL_UNLOCK_SEL DCIO_GSL0_TIMING_SYNC_SEL DCIO_GSL1_GLOBAL_UNLOCK_SEL
DCIO_GSL1_TIMING_SYNC_SEL DCIO_GSL2_GLOBAL_UNLOCK_SEL DCIO_GSL2_TIMING_SYNC_SEL
DCIO_GSL_SEL DCIO_GSL_VSYNC_SEL DCIO_IMPCAL_STEP_DELAY
DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL
DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL
DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN DCIO_PHY_HPO_ENC_SRC_SEL
DCIO_SWAPLOCK_A_GSL_MASK DCIO_SWAPLOCK_B_GSL_MASK DCIO_UNIPHY_CHANNEL_XBAR_SOURCE
DCIO_UNIPHY_IMPCAL_SEL DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK
DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION DCO_DBG_BLOCK_SEL DCO_DBG_CLOCK_SEL
DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE DCP_ALPHA_ROUND_TRUNC_MODE DCP_CRC_ENABLE
DCP_CRC_LINE_SEL DCP_CRC_SOURCE_SEL DCP_CUR2_INV_TRANS_CLAMP
DCP_CURSOR2_2X_MAGNIFY DCP_CURSOR2_DEGAMMA_MODE DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE
DCP_CURSOR2_EN DCP_CURSOR2_FORCE_MC_ON DCP_CURSOR2_MODE
DCP_CURSOR2_STEREO_EN DCP_CURSOR2_STEREO_OFFSET_YNX DCP_CURSOR2_UPDATE_LOCK
DCP_CURSOR2_UPDATE_PENDING DCP_CURSOR2_UPDATE_STEREO_MODE DCP_CURSOR2_UPDATE_TAKEN
DCP_CURSOR2_URGENT_CONTROL DCP_CURSOR_2X_MAGNIFY DCP_CURSOR_ALPHA_BLND_ENA
DCP_CURSOR_DEGAMMA_MODE DCP_CURSOR_DISABLE_MULTIPLE_UPDATE DCP_CURSOR_EN
DCP_CURSOR_FORCE_MC_ON DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM DCP_CURSOR_MODE
DCP_CURSOR_STEREO_EN DCP_CURSOR_STEREO_OFFSET_YNX DCP_CURSOR_UPDATE_LOCK
DCP_CURSOR_UPDATE_PENDING DCP_CURSOR_UPDATE_STEREO_MODE DCP_CURSOR_UPDATE_TAKEN
DCP_CURSOR_URGENT_CONTROL DCP_CUR_INV_TRANS_CLAMP DCP_CUR_REQUEST_FILTER_DIS
DCP_DC_LUT_AUTOFILL DCP_DC_LUT_AUTOFILL_DONE DCP_DC_LUT_DATA_B_FLOAT_POINT_EN
DCP_DC_LUT_DATA_B_FORMAT DCP_DC_LUT_DATA_B_SIGNED_EN DCP_DC_LUT_DATA_G_FLOAT_POINT_EN
DCP_DC_LUT_DATA_G_FORMAT DCP_DC_LUT_DATA_G_SIGNED_EN DCP_DC_LUT_DATA_R_FLOAT_POINT_EN
DCP_DC_LUT_DATA_R_FORMAT DCP_DC_LUT_DATA_R_SIGNED_EN DCP_DC_LUT_INC_B
DCP_DC_LUT_INC_G DCP_DC_LUT_INC_R DCP_DC_LUT_RW_MODE
DCP_DC_LUT_VGA_ACCESS_ENABLE DCP_DENORM_14BIT_OUT DCP_DENORM_MODE
DCP_FRAME_RANDOM_ENABLE DCP_GRPH_ADDRESS_TRANSLATION_ENABLE DCP_GRPH_ALPHA_CROSSBAR
DCP_GRPH_ARRAY_MODE DCP_GRPH_BANK_HEIGHT DCP_GRPH_BANK_WIDTH
DCP_GRPH_BLUE_CROSSBAR DCP_GRPH_COLOR_EXPANSION_MODE DCP_GRPH_DEGAMMA_MODE
DCP_GRPH_DEPTH DCP_GRPH_DFQ_MIN_FREE_ENTRIES DCP_GRPH_DFQ_RESET
DCP_GRPH_DFQ_RESET_ACK DCP_GRPH_DFQ_SIZE DCP_GRPH_ENABLE
DCP_GRPH_ENDIAN_SWAP DCP_GRPH_FLIP_RATE DCP_GRPH_FLIP_RATE_ENABLE
DCP_GRPH_FORMAT DCP_GRPH_GAMUT_REMAP_MODE DCP_GRPH_GREEN_CROSSBAR
DCP_GRPH_INPUT_GAMMA_MODE DCP_GRPH_KEYER_ALPHA_SEL DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN
DCP_GRPH_LUT_10BIT_BYPASS_EN DCP_GRPH_MACRO_TILE_ASPECT DCP_GRPH_MICRO_TILE_MODE
DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE DCP_GRPH_MODE_UPDATE_PENDING DCP_GRPH_MODE_UPDATE_TAKEN
DCP_GRPH_NUM_BANKS DCP_GRPH_NUM_PIPES DCP_GRPH_PFLIP_INT_CLEAR
DCP_GRPH_PFLIP_INT_MASK DCP_GRPH_PFLIP_INT_TYPE DCP_GRPH_PRESCALE_BYPASS
DCP_GRPH_PRESCALE_B_SIGN DCP_GRPH_PRESCALE_G_SIGN DCP_GRPH_PRESCALE_R_SIGN
DCP_GRPH_PRESCALE_SELECT DCP_GRPH_PRIMARY_DFQ_ENABLE DCP_GRPH_PRIVILEGED_ACCESS_ENABLE
DCP_GRPH_RED_CROSSBAR DCP_GRPH_REGAMMA_MODE DCP_GRPH_ROTATION_ANGLE
DCP_GRPH_SECONDARY_DFQ_ENABLE DCP_GRPH_STEREOSYNC_FLIP_EN DCP_GRPH_STEREOSYNC_FLIP_MODE
DCP_GRPH_STEREOSYNC_SELECT_DISABLE DCP_GRPH_SURFACE_COUNTER_EN DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED
DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK
DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN DCP_GRPH_SURFACE_UPDATE_PENDING DCP_GRPH_SURFACE_UPDATE_TAKEN
DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE DCP_GRPH_SW_MODE DCP_GRPH_TILE_SPLIT
DCP_GRPH_UPDATE_LOCK DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE
DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK
DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK DCP_GRPH_XDMA_DRR_MODE_ENABLE DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK
DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK DCP_GRPH_XDMA_FLIP_TYPE_CLEAR DCP_GRPH_XDMA_MULTIFLIP_ENABLE
DCP_GRPH_XDMA_SUPER_AA_EN DCP_GSL0_EN DCP_GSL1_EN
DCP_GSL2_EN DCP_GSL_DELAY_SURFACE_UPDATE_PENDING DCP_GSL_MASTER_EN
DCP_GSL_SYNC_SOURCE DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC DCP_GSL_XDMA_GROUP
DCP_GSL_XDMA_GROUP_UNDERFLOW_EN DCP_HIGHPASS_RANDOM_ENABLE DCP_INPUT_CSC_GRPH_MODE
DCP_KEY_MODE DCP_OUTPUT_CSC_GRPH_MODE DCP_OUT_ROUND_TRUNC_MODE
DCP_RGB_RANDOM_ENABLE DCP_SPATIAL_DITHER_DEPTH DCP_SPATIAL_DITHER_EN
DCP_SPATIAL_DITHER_MODE DCP_TEST_DEBUG_WRITE_EN DCS_ARCH_e
DC_DMCUB_INT_TYPE DC_DMCUB_TIMER_WINDOW DC_MEM_GLOBAL_PWR_REQ_DIS
DC_SMU_INTERRUPT_ENABLE DDR32_t DENORM_TRUNCATE
DESC_ARRAY DETILE_BUFFER_PACKER_ENABLE DET_MEM_PWR_LIGHT_SLEEP_MODE
DFP_DPMS_STATUS_CHANGE_PARAMETERS DFQ_MIN_FREE_ENTRIES DFQ_NUM_ENTRIES
DFQ_SIZE DFSMFlushEvents DF_SWITCH_TYPE_e
DIGA_BE_SOFT_RESET DIGA_FE_SOFT_RESET DIGB_BE_SOFT_RESET
DIGB_FE_SOFT_RESET DIGC_BE_SOFT_RESET DIGC_FE_SOFT_RESET
DIGD_BE_SOFT_RESET DIGD_FE_SOFT_RESET DIGE_BE_SOFT_RESET
DIGE_FE_SOFT_RESET DIGF_BE_SOFT_RESET DIGF_FE_SOFT_RESET
DIGG_BE_SOFT_RESET DIGG_FE_SOFT_RESET DIGLPA_BE_SOFT_RESET
DIGLPA_FE_SOFT_RESET DIGLPB_BE_SOFT_RESET DIGLPB_FE_SOFT_RESET
DIG_BE_CNTL_HPD_SELECT DIG_BE_CNTL_MODE DIG_DIGITAL_BYPASS_ENABLE
DIG_DIGITAL_BYPASS_SEL DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK
DIG_DISPCLK_SWITCH_CNTL_SWITCH_POINT DIG_ENCODER_CONTROL_PARAMETERS DIG_ENCODER_CONTROL_PARAMETERS_V2
DIG_ENCODER_CONTROL_PARAMETERS_V3 DIG_ENCODER_CONTROL_PARAMETERS_V4 DIG_ENCODER_CONTROL_PARAMETERS_V5
DIG_FE_CNTL_SOURCE_SELECT DIG_FE_CNTL_STEREOSYNC_SELECT DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX
DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL DIG_FIFO_ERROR_ACK DIG_FIFO_FORCE_RECAL_AVERAGE
DIG_FIFO_OUTPUT_PROCESSING_MODE DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR DIG_FIFO_READ_CLOCK_SRC
DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL
DIG_INPUT_PIXEL_SEL DIG_OUTPUT_CRC_CNTL_LINK_SEL DIG_OUTPUT_CRC_DATA_SEL
DIG_RANDOM_PATTERN_SEED_RAN_PAT DIG_SL_PIXEL_GROUPING DIG_TEST_PATTERN_EXTERNAL_RESET_EN
DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN DIG_TEST_PATTERN_RANDOM_PATTERN_RESET
DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN DIG_TRANSMITTER_CONTROL_PARAMETERS DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5
DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3
DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 DIG_TRANSMITTER_INFO_HEADER_V3_1 DIG_TRANSMITTER_INFO_HEADER_V3_2
DIG_TRANSMITTER_INFO_HEADER_V3_3 DIM_TYPE DIOMEM_PWR_DIS_CTRL
DIOMEM_PWR_FORCE_CTRL DIOMEM_PWR_FORCE_CTRL2 DIOMEM_PWR_SEL_CTRL
DIOMEM_PWR_SEL_CTRL2 DIO_DBG_BLOCK_SEL DIO_FIFO_ERROR
DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE DISABLE_CLOCK_GATING DISABLE_CLOCK_GATING_IN_DCO
DISPCLK_CHG_FWD_CORR_DISABLE DISPCLK_FREQ_RAMP_DONE DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
DISPLAY_GAP DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE DMDATA_DONE
DMDATA_MODE DMDATA_QOS_MODE DMDATA_REPEAT
DMDATA_UNDERFLOW DMDATA_UNDERFLOW_CLEAR DMDATA_UPDATED
DMDATA_VM_DONE DME_MEM_POWER_STATE_ENUM DME_MEM_PWR_DIS_CTRL
DME_MEM_PWR_FORCE_CTRL DMU_CLOCK_GATING_DISABLE DMU_CLOCK_ON
DMU_DC_GPU_TIMER_READ_SELECT DMU_DC_GPU_TIMER_START_POSITION DOLBY_VISION_ENABLE
DOUT_I2C_ACK DOUT_I2C_ARBITRATION_ABORT_XFER DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG
DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO DOUT_I2C_ARBITRATION_SW_PRIORITY DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ
DOUT_I2C_CONTROL_DBG_REF_SEL DOUT_I2C_CONTROL_DDC_SELECT DOUT_I2C_CONTROL_GO
DOUT_I2C_CONTROL_SEND_RESET DOUT_I2C_CONTROL_SEND_RESET_LENGTH DOUT_I2C_CONTROL_SOFT_RESET
DOUT_I2C_CONTROL_SW_STATUS_RESET DOUT_I2C_CONTROL_TRANSACTION_COUNT DOUT_I2C_DATA_INDEX_WRITE
DOUT_I2C_DDC_EDID_DETECT_STATUS DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN
DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE DOUT_I2C_DDC_SPEED_THRESHOLD
DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE DOUT_I2C_TRANSACTION_STOP_ON_NACK
DPCSRX_DBG_CFGCLK_SEL DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL DPCSRX_RX_SYMCLK_SEL
DPCSTX_DBG_CFGCLK_SEL DPCSTX_DBG_CLOCK_SEL DPCSTX_DVI_LINK_MODE
DPCSTX_TX_SYMCLK_DIV2_SEL DPCSTX_TX_SYMCLK_SEL DPDBG_CLK_FORCE_EN
DPDBG_EN DPDBG_ERROR_DETECTION_MODE DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK
DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE DPDBG_INPUT_EN
DPDBG_SOFT_RESET DPHY_8B10B_CUR_DISP DPHY_8B10B_RESET
DPHY_ALT_SCRAMBLER_RESET_EN DPHY_ALT_SCRAMBLER_RESET_SEL DPHY_ATEST_SEL_LANE0
DPHY_ATEST_SEL_LANE1 DPHY_ATEST_SEL_LANE2 DPHY_ATEST_SEL_LANE3
DPHY_BYPASS DPHY_CRC_CONT_EN DPHY_CRC_EN
DPHY_CRC_FIELD DPHY_CRC_MST_PHASE_ERROR_ACK DPHY_CRC_SEL
DPHY_ELEC_PARA DPHY_FEC_ENABLE DPHY_FEC_READY
DPHY_LOAD_BS_COUNT_START DPHY_PRBS_EN DPHY_PRBS_SEL
DPHY_RX_FAST_TRAINING_CAPABLE DPHY_SCRAMBLER_ADVANCE DPHY_SCRAMBLER_DIS
DPHY_SCRAMBLER_KCODE DPHY_SCRAMBLER_SEL DPHY_SKEW_BYPASS
DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM DPHY_SW_FAST_TRAINING_START DPHY_TIMING_PARA
DPHY_TRAINING_PATTERN_SEL DPREFCLK_SRC_SEL DPRX_SD_COMPONENT_DEPTH
DPRX_SD_PIXEL_ENCODING DPTE_GROUP_SIZE DP_AUX_ARB_CONTROL_ARB_PRIORITY
DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ DP_AUX_ARB_STATUS
DP_AUX_CONTROL_HPD_SEL DP_AUX_CONTROL_TEST_MODE DP_AUX_DEFINITE_ERR_REACHED_ACK
DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP
DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW
DP_AUX_DPHY_RX_CONTROL_START_WINDOW DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN DP_AUX_DPHY_RX_DETECTION_THRESHOLD
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE
DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL DP_AUX_ERR_OCCURRED_ACK DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ
DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN
DP_AUX_INT_ACK DP_AUX_LS_UPDATE_ACK DP_AUX_PHY_WAKE_PRIORITY
DP_AUX_POTENTIAL_ERR_REACHED_ACK DP_AUX_RESET DP_AUX_RESET_DONE
DP_AUX_RX_TIMEOUT_LEN_MUL DP_AUX_SW_CONTROL_LS_READ_TRIG DP_AUX_SW_CONTROL_SW_GO
DP_AUX_TX_PRECHARGE_LEN_MUL DP_COMBINE_PIXEL_NUM DP_COMPONENT_DEPTH
DP_CP_ENCRYPTION_TYPE DP_DPHY_8B10B_EXT_DISP DP_DPHY_FAST_TRAINING_COMPLETE_ACK
DP_DPHY_FAST_TRAINING_COMPLETE_MASK DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN DP_DPHY_HBR2_PATTERN_CONTROL_MODE
DP_DSC_MODE DP_DTO_DS_DISABLE DP_DYN_RANGE
DP_EMBEDDED_PANEL_MODE DP_ENCODER_SERVICE_PARAMETERS DP_ENCODER_SERVICE_PARAMETERS_V2
DP_ENCODER_SERVICE_PS_ALLOCATION_V2 DP_LINK_TRAINING_COMPLETE DP_LINK_TRAINING_SWITCH_MODE
DP_ML_PHY_SEQ_MODE DP_MSA_MISC0_OVERRIDE_ENABLE DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE
DP_MSA_V_TIMING_OVERRIDE_EN DP_MSE_BLANK_CODE DP_MSE_LINK_LINE
DP_MSE_OUTPUT_DPDBG_DATA DP_MSE_SAT_ENCRYPT0 DP_MSE_SAT_ENCRYPT1
DP_MSE_SAT_ENCRYPT2 DP_MSE_SAT_ENCRYPT3 DP_MSE_SAT_ENCRYPT4
DP_MSE_SAT_ENCRYPT5 DP_MSE_SAT_UPDATE_ACT DP_MSE_TIMESTAMP_MODE
DP_MSE_ZERO_ENCODER DP_MSO_NUM_OF_SST_LINKS DP_PANEL_MODE_SETUP_PARAMETERS_V5
DP_PIXEL_ENCODING DP_PIXEL_PER_CYCLE_PROCESSING_NUM DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE
DP_SEC_ASP_PRIORITY DP_SEC_AUDIO_MUTE DP_SEC_COLLISION_ACK
DP_SEC_GSP0_PRIORITY DP_SEC_GSP0_SEND DP_SEC_GSP_SEND
DP_SEC_GSP_SEND_ANY_LINE DP_SEC_GSP_SEND_PPS DP_SEC_LINE_REFERENCE
DP_SEC_TIMESTAMP_MODE DP_STEER_OVERFLOW_ACK DP_STEER_OVERFLOW_MASK
DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT DP_STREAM_ENC_READ_CLOCK_CONTROL
DP_STREAM_ENC_RESET_CONTROL DP_STREAM_ENC_STREAM_ACTIVE DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET
DP_SYNC_POLARITY DP_TU_OVERFLOW_ACK DP_UDI_LANES
DP_VID_ENHANCED_FRAME_MODE DP_VID_MSA_TOP_FIELD_MODE DP_VID_M_DOUBLE_VALUE_EN
DP_VID_M_N_DOUBLE_BUFFER_MODE DP_VID_M_N_GEN_EN DP_VID_N_MUL
DP_VID_STREAM_DISABLE_ACK DP_VID_STREAM_DISABLE_MASK DP_VID_STREAM_DIS_DEFER
DP_VID_TIMING_MODE DP_VID_VBID_FIELD_POL DP_YCBCR_RANGE
DRAM_BIT_WIDTH_TYPE_e DRR_UPDATE_LOCK_SEL DSCCIF_BITS_PER_COMPONENT_ENUM
DSCCIF_ENABLE_ENUM DSCCIF_INPUT_PIXEL_FORMAT_ENUM DSCC_BITS_PER_COMPONENT_ENUM
DSCC_DSC_VERSION_MAJOR_ENUM DSCC_DSC_VERSION_MINOR_ENUM DSCC_ENABLE_ENUM
DSCC_ICH_RESET_ENUM DSCC_LINEBUF_DEPTH_ENUM DSCC_MEM_PWR_DIS_ENUM
DSCC_MEM_PWR_FORCE_ENUM DSCL_MODE_SEL DSI_BIT_SWAP
DSI_CLK_GATING DSI_CLOCK_LANE_EN DSI_CLOCK_LANE_HS_FORCE_REQUEST
DSI_CMD_EMBEDDED_MODE DSI_CMD_MODE_EN DSI_CMD_ORDER
DSI_CMD_PACKET_TYPE DSI_CMD_PWR_MODE DSI_COMMAND_MODE_DST_FORMAT
DSI_COMMAND_MODE_SRC_FORMAT DSI_COMMAND_TRIGGER_MODE DSI_COMMAND_TRIGGER_ORDER
DSI_COMMAND_TRIGGER_SEL DSI_CONTROLLER_EN DSI_CRC_ENABLE
DSI_CRTC_FREEZE_TRIG DSI_CRTC_SEL DSI_DATA_BUFFER_ID
DSI_DATA_LANE0_EN DSI_DATA_LANE1_EN DSI_DATA_LANE2_EN
DSI_DATA_LANE3_EN DSI_DBG_CLK_SEL DSI_DEBUG_BYTECLK_SEL
DSI_DEBUG_DSICLK_SEL DSI_DENG_FIFO_FORCE_RECAL_AVERAGE DSI_DENG_FIFO_FORCE_RECOMP_MINMAX
DSI_DENG_FIFO_START DSI_DENG_FIFO_USE_OVERWRITE_LEVEL DSI_DMAFIFO_READ_WATERMARK
DSI_DMAFIFO_WRITE_WATERMARK DSI_DWORD_BYTE_SWAP DSI_EXT_RESET_POL
DSI_EXT_TE_MODE DSI_EXT_TE_MUX DSI_EXT_TE_POL
DSI_FLAG_CLR DSI_HW_SOURCE_SEL DSI_INSERT_DCS_COMMAND
DSI_LANE_FORCE_TX_STOP DSI_LANE_ULPS_EXIT DSI_LANE_ULPS_REQUEST
DSI_MIPI_BIST_RESET DSI_MIPI_BIST_START DSI_MIPI_BIST_VIDEO_FRMT
DSI_PACKET_BYTE_MSB_LSB_FLIP DSI_PERF_LATENCY_SEL DSI_PHY_DATA_LANE0_EN
DSI_PHY_DATA_LANE1_EN DSI_PHY_DATA_LANE2_EN DSI_PHY_DATA_LANE3_EN
DSI_RESET_BYTECLK DSI_RESET_DISPCLK DSI_RESET_DSICLK
DSI_RESET_ESCCLK DSI_RESET_PANEL DSI_RGB_SWAP
DSI_RX_EOT_IGNORE DSI_TE_SRC_SEL DSI_TX_EOT_APPEND
DSI_USE_CMDFIFO DSI_USE_DENG_LENGTH DSI_VIDEO_BLLP_PWR_MODE
DSI_VIDEO_EOF_BLLP_PWR_MODE DSI_VIDEO_MODE_DST_FORMAT DSI_VIDEO_MODE_EN
DSI_VIDEO_PULSE_MODE_OPT DSI_VIDEO_PWR_MODE DSI_VIDEO_TRAFFIC_MODE
DSM_DATA_SEL DSM_ENABLE_ERROR_INJECT DSM_SELECT_INJECT_DELAY
DSM_SINGLE_WRITE DSPCLK_e DS_HW_CAL_ENABLE
DS_JITTER_COUNT_SRC_SEL DS_REF_SRC DVOACLKC_IN_PHASE
DVOACLKC_MVP_IN_PHASE DVOACLKC_MVP_SKEW_PHASE_OVERRIDE DVOACLKD_IN_PHASE
DVOACLK_COARSE_SKEW_CNTL DVOACLK_FINE_SKEW_CNTL DVO_ENABLE_RST
DVO_ENCODER_CONTROL_PARAMETERS DVO_ENCODER_CONTROL_PARAMETERS_V1_4 DVO_ENCODER_CONTROL_PARAMETERS_V3
DVO_ENCODER_CONTROL_PS_ALLOCATION DVO_SOFT_RESET DV_CCB
DWB_CRC_CONT_EN_ENUM DWB_CRC_SRC_SEL_ENUM DWB_DATA_DEPTH_WARMUP_ENUM
DWB_DATA_OVERFLOW_INT_TYPE_ENUM DWB_DATA_OVERFLOW_TYPE_ENUM DWB_DEBUG_SEL_ENUM
DWB_GAMUT_REMAP_COEF_FORMAT_ENUM DWB_GAMUT_REMAP_MODE_ENUM DWB_GMC_WARM_UP_ENABLE_ENUM
DWB_LUT_NUM_SEG DWB_MEM_PWR_FORCE_ENUM DWB_MEM_PWR_STATE_ENUM
DWB_MODE_WARMUP_ENUM DWB_OGAM_LUT_CONFIG_MODE_ENUM DWB_OGAM_LUT_HOST_SEL_ENUM
DWB_OGAM_LUT_READ_COLOR_SEL_ENUM DWB_OGAM_LUT_READ_DBG_ENUM DWB_OGAM_MODE_ENUM
DWB_OGAM_PWL_DISABLE_ENUM DWB_OGAM_SELECT_ENUM DWB_TEST_CLK_SEL_ENUM
DW_CARRIER DW_CCB DW_SCSI_INQUIRY
DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE DYNAMICE_ENGINE_SETTINGS_PARAMETER DYNAMICE_MC_DPM_SETTINGS_PARAMETER
DYNAMICE_MEMORY_SETTINGS_PARAMETER DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1 DYNAMIC_CLOCK_GATING_PARAMETERS
DbMemArbWatermarks DbPRTFaultBehavior DbPSLControl
DebugBlockId DebugBlockId_BY16 DebugBlockId_BY2
DebugBlockId_BY4 DebugBlockId_BY8 DebugBlockId_OLD
DepthArray DepthFormat DfPstateTable314_t
DfPstateTable_t DfllDroopModelSelect_e DisplayClockTable_t
DmlPipe DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeffIntExternal_t
DpmActivityMonitorCoeffInt_t DpmClock_t DpmClocks314_t
DpmClocks_315_t DpmClocks_316_t DpmClocks_t
DpmDescriptor_t DriverInfoTable_t DriverReportedClocks_t
DriverSmuConfigExternal_t DriverSmuConfig_t DroopInt_t
EFC_SURFACE_PIXEL_FORMAT EFIAPI EFI_ALLOCATE_TYPE
EFI_BLOCK_IO EFI_BLOCK_IO_MEDIA EFI_BOOT_SERVICES
EFI_CONFIGURATION_TABLE EFI_CONSOLE_CONTROL_PROTOCOL EFI_CONSOLE_CONTROL_SCREEN_MODE
EFI_DEVICE_IO_INTERFACE EFI_DEVICE_PATH EFI_DEVICE_PATH_TO_TEXT_NODE
EFI_DEVICE_PATH_TO_TEXT_PATH EFI_DEVICE_PATH_TO_TEXT_PROTOCOL EFI_DEV_PATH
EFI_DEV_PATH_PTR EFI_DISK_IO EFI_EVENT
EFI_FILE EFI_FILE_HANDLE EFI_FILE_HEADER
EFI_FILE_INFO EFI_FILE_IO_INTERFACE EFI_FILE_SYSTEM_INFO
EFI_FILE_SYSTEM_VOLUME_LABEL_INFO EFI_GRAPHICS_OUTPUT EFI_GRAPHICS_OUTPUT_BLT_OPERATION
EFI_GRAPHICS_OUTPUT_BLT_PIXEL EFI_GRAPHICS_OUTPUT_MODE_INFORMATION EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE
EFI_GRAPHICS_PIXEL_FORMAT EFI_GUID EFI_HANDLE
EFI_INPUT_KEY EFI_INTERFACE_TYPE EFI_IO_ACCESS
EFI_IO_OPERATION_TYPE EFI_IO_WIDTH EFI_IP_ADDRESS
EFI_IPv4_ADDRESS EFI_IPv6_ADDRESS EFI_LBA
EFI_LBAL EFI_LOADED_IMAGE EFI_LOAD_FILE_INTERFACE
EFI_LOCATE_SEARCH_TYPE EFI_MAC_ADDRESS EFI_MEMORY_DESCRIPTOR
EFI_MEMORY_TYPE EFI_NETWORK_INTERFACE_IDENTIFIER_INTERFACE EFI_NETWORK_INTERFACE_TYPE
EFI_NETWORK_STATISTICS EFI_OPEN_PROTOCOL_INFORMATION_ENTRY EFI_PARITY_TYPE
EFI_PARTITION_HEADER EFI_PHYSICAL_ADDRESS EFI_PIXEL_BITMASK
EFI_PXE_BASE_CODE EFI_PXE_BASE_CODE_ARP_ENTRY EFI_PXE_BASE_CODE_CALLBACK
EFI_PXE_BASE_CODE_CALLBACK_STATUS EFI_PXE_BASE_CODE_DHCPV4_PACKET EFI_PXE_BASE_CODE_DISCOVER_INFO
EFI_PXE_BASE_CODE_FUNCTION EFI_PXE_BASE_CODE_ICMP_ERROR EFI_PXE_BASE_CODE_IP_FILTER
EFI_PXE_BASE_CODE_MODE EFI_PXE_BASE_CODE_MTFTP_INFO EFI_PXE_BASE_CODE_PACKET
EFI_PXE_BASE_CODE_ROUTE_ENTRY EFI_PXE_BASE_CODE_SRVLIST EFI_PXE_BASE_CODE_TFTP_ERROR
EFI_PXE_BASE_CODE_TFTP_OPCODE EFI_PXE_BASE_CODE_UDP_PORT EFI_RESET_TYPE
EFI_RL EFI_RNG_ALGORITHM EFI_RNG_PROTOCOL
EFI_RUNTIME_SERVICES EFI_SIMPLE_NETWORK EFI_SIMPLE_NETWORK_MODE
EFI_SIMPLE_NETWORK_STATE EFI_SIMPLE_TEXT_INPUT_PROTOCOL EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL
EFI_STATUS EFI_STOP_BITS_TYPE EFI_SYSTEM_RESOURCE_ENTRY
EFI_SYSTEM_RESOURCE_TABLE EFI_SYSTEM_TABLE EFI_TABLE_HEADER
EFI_TIME EFI_TIMER_DELAY EFI_TIME_CAPABILITIES
EFI_TPL EFI_UNICODE_COLLATION_INTERFACE EFI_VIRTUAL_ADDRESS
EFUSE_INPUT_PARAMETER EFUSE_LINEAR_FUNC_PARAM EFUSE_LOGISTIC_FUNC_PARAM
ENABLE ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS ENABLE_CLOCK
ENABLE_CRTC_PARAMETERS ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 ENABLE_DISP_POWER_GATING_PS_ALLOCATION
ENABLE_ENUM ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION
ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 ENABLE_GRAPH_SURFACE_PARAMETERS ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2
ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3 ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4 ENABLE_GRAPH_SURFACE_PS_ALLOCATION
ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION ENABLE_LVDS_SS_PARAMETERS
ENABLE_LVDS_SS_PARAMETERS_V2 ENABLE_SCALER_PARAMETERS ENABLE_SPREAD_SPECTRUM_ON_PPLL
ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 ENABLE_YUV_PARAMETERS
ENCODER_GENERIC_CMD_PARAMETERS_V5 ENCODER_LINK_SETUP_PARAMETERS_V5 ENCODER_STREAM_SETUP_PARAMETERS_V5
ENUM_DIO_DCN_ACTIVE_STATUS ENUM_DPG_BIT_DEPTH ENUM_DPG_DYNAMIC_RANGE
ENUM_DPG_EN ENUM_DPG_FIELD_POLARITY ENUM_DPG_MODE
ENUM_DP_DPHY_SYM32_CRC_END_EVENT ENUM_DP_DPHY_SYM32_CRC_START_EVENT ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE
ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS ENUM_DP_DPHY_SYM32_ENABLE ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE
ENUM_DP_DPHY_SYM32_MODE ENUM_DP_DPHY_SYM32_NUM_LANES ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING
ENUM_DP_DPHY_SYM32_RESET ENUM_DP_DPHY_SYM32_RESET_STATUS ENUM_DP_DPHY_SYM32_SAT_UPDATE
ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING ENUM_DP_DPHY_SYM32_STATUS ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE
ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE ENUM_DP_DPHY_SYM32_TP_PRBS_SEL ENUM_DP_DPHY_SYM32_TP_SELECT
ENUM_DP_SYM32_ENC_AUDIO_MUTE ENUM_DP_SYM32_ENC_CONTINUOUS_MODE ENUM_DP_SYM32_ENC_CRC_VALID
ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH ENUM_DP_SYM32_ENC_ENABLE ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED
ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING
ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM ENUM_DP_SYM32_ENC_OVERFLOW_STATUS ENUM_DP_SYM32_ENC_PENDING
ENUM_DP_SYM32_ENC_PIXEL_ENCODING ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE ENUM_DP_SYM32_ENC_POWER_STATE_ENUM
ENUM_DP_SYM32_ENC_RESET ENUM_DP_SYM32_ENC_SDP_PRIORITY ENUM_DP_SYM32_ENC_SOF_REFERENCE
ENUM_DP_SYM32_ENC_VID_STREAM_DEFER ENUM_DSCRM_EN ENUM_FMT_PTI_FIELD_POLARITY
ENUM_NUM_SIMD_PER_CU ENUM_SQ_EXPORT_RAT_INST ENUM_XDMA_LOCAL_SW_MODE
ENUM_XDMA_MSTR_ALPHA_POSITION ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL ENUM_XDMA_SLV_ALPHA_POSITION
EXPANSION_MODE EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION
EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 EXT_DISPLAY_PATH EXT_MSG
EccInfoTable_t EccInfo_V2_t EccInfo_t
Elf32_Addr Elf32_Dyn Elf32_Ehdr
Elf32_Half Elf32_Lword Elf32_Nhdr
Elf32_Note Elf32_Off Elf32_Phdr
Elf32_RegInfo Elf32_Rel Elf32_Rela
Elf32_Relr Elf32_Shdr Elf32_Sword
Elf32_Sym Elf32_Word Elf32_gptab
Elf64_Addr Elf64_Dyn Elf64_Ehdr
Elf64_Half Elf64_Lword Elf64_Nhdr
Elf64_Note Elf64_Off Elf64_Phdr
Elf64_Rel Elf64_Rela Elf64_Relr
Elf64_Shalf Elf64_Shdr Elf64_Sword
Elf64_Sxword Elf64_Sym Elf64_Word
Elf64_Xword Event F1394_DEVICE_PATH
FAR FBC_IDLE_MASK_MASK_BITS FC_EYE_SELECTION_ENUM
FC_FRAME_CAPTURE_RATE_ENUM FC_STEREO_EYE_POLARITY_ENUM FEATURE_PWR_DOMAIN_e
FEC_ACTIVE_STATUS FIBRECHANNEL_DEVICE_PATH FILEPATH_DEVICE_PATH
FIRMWARE_ID FLAGS FLASHLIGHT_INFO
FLIP_RATE FMT0_SOFT_RESET FMT1_SOFT_RESET
FMT2_SOFT_RESET FMT3_SOFT_RESET FMT420_MEMORY_SOURCE_SEL
FMT4_SOFT_RESET FMT5_SOFT_RESET FMTMEM_PWR_DIS_CTRL
FMTMEM_PWR_FORCE_CTRL FMT_BIT_DEPTH_CONTROL_25FRC_SEL FMT_BIT_DEPTH_CONTROL_50FRC_SEL
FMT_BIT_DEPTH_CONTROL_75FRC_SEL FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH
FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE
FMT_CLAMP_CNTL_COLOR_FORMAT FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS FMT_CONTROL_PIXEL_ENCODING
FMT_CONTROL_SUBSAMPLING_MODE FMT_CONTROL_SUBSAMPLING_ORDER FMT_CRC_CNTL_CONT_EN
FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT FMT_CRC_CNTL_INCLUDE_OVERSCAN
FMT_CRC_CNTL_INTERLACE_MODE FMT_CRC_CNTL_ONLY_BLANKB FMT_CRC_CNTL_PSR_MODE_ENABLE
FMT_DEBUG_CNTL_COLOR_SELECT FMT_DYNAMIC_EXP_MODE FMT_FRAME_RANDOM_ENABLE_CONTROL
FMT_POWER_STATE_ENUM FMT_RGB_RANDOM_ENABLE_CONTROL FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL
FMT_SPATIAL_DITHER_MODE FMT_STEREOSYNC_OVERRIDE_CONTROL FMT_STEREOSYNC_OVR_POL
FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT FOPT_CALC_e
FORCE_DISABLE_CLOCK FORCE_ONE_ROW_FOR_FRAME FORCE_VBI
FORMAT_CROSSBAR FPSWA_INTERFACE FPSWA_RET
FW_ATT_DB_HEADER FW_ATT_RECORD FanMode_e
FclkSwitchAllow_e File FloatInIntFormat_t
ForceControl FullTileWaveBreak FwStatus_t
GATCL1RequestType GB_EDC_DED_MODE GB_VDROOP_TABLE_t
GCRPerfSel GDS_PERFCOUNT_SELECT GE1_PERFCOUNT_SELECT
GE2_DIST_PERFCOUNT_SELECT GE2_SE_PERFCOUNT_SELECT GENERICA_STEREOSYNC_SEL
GENERICB_STEREOSYNC_SEL GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED
GENERIC_AZ_CONTROLLER_REGISTER_STATUS GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED GENERIC_STEREOSYNC_SEL
GET_DISPLAY_SURFACE_SIZE_PARAMETERS GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2 GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2
GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3 GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2 GET_ENGINE_CLOCK_PARAMETERS
GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3 GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
GET_MEMORY_CLOCK_PARAMETERS GET_SMU_CLOCK_INFO_INPUT_PARAMETER_V2_1 GET_SMU_CLOCK_INFO_OUTPUT_PARAMETER_V2_1
GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1 GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3
GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1 GE_PERFCOUNT_SELECT GFXCLK_SOURCE_e
GFXOFF_ERROR_e GFX_HAVESTING_PARAMETERS GHASH_CTX
GL0V_CACHE_POLICIES GL1A_PERF_SEL GL1CG_PERF_SEL
GL1C_PERF_SEL GL1H_REQ_PERF_SEL GL1_CACHE_POLICIES
GL1_CACHE_STORE_POLICIES GL2A_PERF_SEL GL2C_PERF_SEL
GL2_CACHE_POLICIES GL2_EA_CID GL2_NACKS
GL2_OP GL2_OP_MASKS GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE
GLOBAL_CONTROL_CONTROLLER_RESET GLOBAL_CONTROL_FLUSH_CONTROL GLOBAL_STATUS_FLUSH_STATUS
GOP_LIB1_CONTENT GOP_VBIOS_CONTENT GPIO_PIN_CONTROL_PARAMETERS
GRBM_PERF_SEL GRBM_SE0_PERF_SEL GRBM_SE1_PERF_SEL
GRBM_SE2_PERF_SEL GRBM_SE3_PERF_SEL GRBM_SE4_PERF_SEL
GRBM_SE5_PERF_SEL GRBM_SE6_PERF_SEL GRBM_SE7_PERF_SEL
GbVdroopTable_t GcCacWeight_Data Gc_Cac_Weight_Data
GfxclkSrc_e GpioIntPolarity_e GroupInterleave
HAL_ANT_SETTING HAL_BEACON_STATE HAL_BOOL
HAL_CHANNEL HAL_CHIP HAL_CIPHER
HAL_CTRY_CODE HAL_INT HAL_KEYVAL
HAL_LED_STATE HAL_MIB_STATS HAL_MODE
HAL_OPMODE HAL_PKT_TYPE HAL_POWER_MODE
HAL_RATE HAL_RATE_TABLE HAL_RFGAIN
HAL_STATUS HAL_TXQ_INFO HAL_TX_QUEUE
HAL_TX_QUEUE_ID HAL_TX_QUEUE_SUBTYPE HARDDRIVE_DEVICE_PATH
HDMICHARCLK_SRC_SEL HDMISTREAMCLK_DTO_FORCE_DIS HDMISTREAMCLK_SRC_SEL
HDMI_ACP_SEND HDMI_ACR_AUDIO_PRIORITY HDMI_ACR_CONT
HDMI_ACR_N_MULTIPLE HDMI_ACR_SELECT HDMI_ACR_SEND
HDMI_ACR_SOURCE HDMI_AUDIO_DELAY_EN HDMI_AUDIO_INFO_CONT
HDMI_AUDIO_INFO_SEND HDMI_AUDIO_SEND_MAX_PACKETS HDMI_AVI_INFO_CONT
HDMI_AVI_INFO_SEND HDMI_BORROW_MODE HDMI_CLOCK_CHANNEL_RATE
HDMI_DATA_SCRAMBLE_EN HDMI_DEEP_COLOR_DEPTH HDMI_DEFAULT_PAHSE
HDMI_ERROR_ACK HDMI_ERROR_MASK HDMI_GC_AVMUTE
HDMI_GC_AVMUTE_CONT HDMI_GC_CONT HDMI_GC_SEND
HDMI_GENERIC0_CONT HDMI_GENERIC0_SEND HDMI_GENERIC1_CONT
HDMI_GENERIC1_SEND HDMI_GENERIC2_CONT HDMI_GENERIC2_SEND
HDMI_GENERIC3_CONT HDMI_GENERIC3_SEND HDMI_GENERIC_CONT
HDMI_GENERIC_SEND HDMI_ISRC_CONT HDMI_ISRC_SEND
HDMI_KEEPOUT_MODE HDMI_METADATA_ENABLE HDMI_MPEG_INFO_CONT
HDMI_MPEG_INFO_SEND HDMI_NO_EXTRA_NULL_PACKET_FILLED HDMI_NULL_SEND
HDMI_PACKET_GEN_VERSION HDMI_PACKET_LINE_REFERENCE HDMI_PACKING_PHASE_OVERRIDE
HDMI_STREAM_ENC_DB_DISABLE_CONTROL HDMI_STREAM_ENC_DSC_MODE HDMI_STREAM_ENC_ENABLE_CONTROL
HDMI_STREAM_ENC_ODM_COMBINE_MODE HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT
HDMI_STREAM_ENC_PIXEL_ENCODING HDMI_STREAM_ENC_READ_CLOCK_CONTROL HDMI_STREAM_ENC_RESET_CONTROL
HDMI_STREAM_ENC_STREAM_ACTIVE HDMI_TB_ENC_ACP_SEND HDMI_TB_ENC_ACR_AUDIO_PRIORITY
HDMI_TB_ENC_ACR_CONT HDMI_TB_ENC_ACR_N_MULTIPLE HDMI_TB_ENC_ACR_SELECT
HDMI_TB_ENC_ACR_SEND HDMI_TB_ENC_ACR_SOURCE HDMI_TB_ENC_AUDIO_INFO_CONT
HDMI_TB_ENC_AUDIO_INFO_SEND HDMI_TB_ENC_CRC_SRC_SEL HDMI_TB_ENC_CRC_TYPE
HDMI_TB_ENC_DEEP_COLOR_DEPTH HDMI_TB_ENC_DEFAULT_PAHSE HDMI_TB_ENC_DSC_MODE
HDMI_TB_ENC_ENABLE HDMI_TB_ENC_GC_AVMUTE HDMI_TB_ENC_GC_AVMUTE_CONT
HDMI_TB_ENC_GC_CONT HDMI_TB_ENC_GC_SEND HDMI_TB_ENC_GENERIC_CONT
HDMI_TB_ENC_GENERIC_LOCK_EN HDMI_TB_ENC_GENERIC_SEND HDMI_TB_ENC_ISRC_CONT
HDMI_TB_ENC_ISRC_SEND HDMI_TB_ENC_METADATA_ENABLE HDMI_TB_ENC_PACKET_LINE_REFERENCE
HDMI_TB_ENC_PIXEL_ENCODING HDMI_TB_ENC_RESET HDMI_TB_ENC_SYNC_PHASE
HMAC_MD5_CTX HMAC_SHA1_CTX HMAC_SHA256_CTX
HM_AutoThrottleSource HM_PerformanceLevel HM_PerformanceLevelDesignation
HPD_INT_CONTROL_ACK HPD_INT_CONTROL_POLARITY HPD_INT_CONTROL_RX_INT_ACK
HPO_TOP_CLOCK_GATING_DISABLE HPO_TOP_TEST_CLK_SEL HUBP_BLANK_EN
HUBP_DISABLE HUBP_IN_BLANK HUBP_MEASURE_WIN_MODE_DCFCLK
HUBP_NO_OUTSTANDING_REQ HUBP_SOFT_RESET HUBP_TTU_DISABLE
HUBP_VREADY_AT_OR_AFTER_VSYNC HUBP_VTG_SEL HUBP_XFC_CHUNK_SIZE_ENUM
HUBP_XFC_FRAME_MODE_ENUM HUBP_XFC_PIXEL_FORMAT_ENUM H_MIRROR_EN
Hdp_SurfaceEndian HighCount HostVM
I2O_DEVICE_PATH I2S0_SPDIF0_SOFT_RESET I2S1_SOFT_RESET
I2S_LRCLK_POLARITY I2S_SAMPLE_ALIGNMENT I2S_SAMPLE_BIT_ORDER
I2S_WORD_ALIGNMENT I2S_WORD_SIZE I2cCmdType_e
I2cControllerConfig_t I2cControllerName_e I2cControllerPort_e
I2cControllerProtocol_e I2cControllerSpeed_e I2cControllerThrottler_e
I2cPort_e I2cSpeed_e IA_PERFCOUNT_SELECT
IHC_INTERRUPT_DEST IHC_INTERRUPT_LINE_STATUS IH_CLIENT_ID
IH_CLIENT_TYPE IH_INTERFACE_TYPE IH_PERF_SEL
IH_RING_ID IH_VF_RB_SELECT IMG_DATA_FORMAT
IMG_FMT IMG_NUM_FORMAT IMG_NUM_FORMAT_ASTC_2D
IMG_NUM_FORMAT_ASTC_3D IMG_NUM_FORMAT_FMASK IMG_NUM_FORMAT_N_IN_16
IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID IN
INDIRECT_IO_ACCESS INFINIBAND_DEVICE_PATH INPUT_FIFO_ERROR_TYPE
INT16 INT32 INT64
INT8 INTERRUPT_SERVICE_PARAMETER_V2 INTN
INT_MASK INVALID_REG_ACCESS_TYPE IP4_t
IPos IPv4_DEVICE_PATH IPv6_DEVICE_PATH
ISODIR ISOMNT ISONODE
ISO_639_2 ISO_RRIP_ALTNAME ISO_RRIP_ANALYZE
ISO_RRIP_ATTR ISO_RRIP_CLINK ISO_RRIP_CONT
ISO_RRIP_DEVICE ISO_RRIP_EXTREF ISO_RRIP_IDFLAG
ISO_RRIP_INODE ISO_RRIP_OFFSET ISO_RRIP_PLINK
ISO_RRIP_RELDIR ISO_RRIP_SLINK ISO_RRIP_SLINK_COMPONENT
ISO_RRIP_TSTAMP ISO_SUSP_HEADER ImageHandle
InstFmt JITTER_REMOVE_DISABLE LBV_DITHER_EN
LBV_DOWNSCALE_PREFETCH_EN LBV_DYNAMIC_PIXEL_DEPTH LBV_INTERLEAVE_EN
LBV_MEMORY_CONFIG LBV_PIXEL_DEPTH LBV_PIXEL_EXPAN_MODE
LBV_PIXEL_REDUCE_MODE LBV_SYNC_DURATION LBV_SYNC_RESET_SEL2
LB_ALPHA_EN LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK
LB_DATA_FORMAT_ALPHA_EN LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH LB_DATA_FORMAT_INTERLEAVE_EN
LB_DATA_FORMAT_PIXEL_DEPTH LB_DATA_FORMAT_PIXEL_EXPAN_MODE LB_DATA_FORMAT_PIXEL_REDUCE_MODE
LB_DATA_FORMAT_PREFILL_EN LB_DATA_FORMAT_REQUEST_MODE LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE
LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE
LB_INTERLEAVE_EN LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK
LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN
LB_MEMORY_CONFIG LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK
LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE
LB_SYNC_RESET_SEL_LB_SYNC_DURATION LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2
LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN LB_VBLANK_STATUS_VBLANK_ACK LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE
LB_VLINE2_START_END_VLINE2_INV LB_VLINE2_STATUS_VLINE2_ACK LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE
LB_VLINE_START_END_VLINE_INV LB_VLINE_STATUS_VLINE_ACK LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE
LEAKAGE_VOLTAGE_LUT_ENTRY_V2 LEGACY_NUM_BANKS LEGACY_PIPE_INTERLEAVE
LIST_HEAD LPATOM_PPLIB_POWERPLAYTABLE2 LPATOM_PPLIB_POWERPLAYTABLE3
LPATOM_PPLIB_POWERPLAYTABLE4 LPATOM_PPLIB_POWERPLAYTABLE5 LPATOM_PPLIB_THERMAL_STATE
LPRV7XX_SMC_MCLK_VALUE LSDMA_PERF_SEL LVDS_ENCODER_CONTROL_PARAMETERS
LVDS_ENCODER_CONTROL_PARAMETERS_V2 LVTMA_OUTPUT_CONTROL_PARAMETERS_V2 LVTMA_RANDOM_PATTERN_SEED_RAN_PAT
Latencies LinearInt_t LptNumBanks
LptNumPipes MACRO_TILE_ASPECT MAC_ADDR
MAC_ADDR_DEVICE_PATH MASTER_BOOT_RECORD MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK
MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK MASTER_UPDATE_LOCK_SEL MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK
MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE MASTER_UPDATE_MODE_MASTER_UPDATE_MODE MAX_COMPRESSED_FRAGS
MBR_PARTITION_RECORD MCuCodeHeader MD5_CTX
MD_ACPI_DESCRIPTION_HEADER MData MEDIA_PROTOCOL_DEVICE_PATH
MEMMAP_DEVICE_PATH MEMORY_CLEAN_UP_PARAMETERS MEMORY_PLLINIT_PARAMETERS
MEMORY_TRAINING_PARAMETERS MEMORY_TRAINING_PARAMETERS_V1_2 MEM_PWR_DIS_CTRL
MEM_PWR_DIS_MODE MEM_PWR_FORCE_CTRL MEM_PWR_FORCE_CTRL2
MEM_PWR_FORCE_MODE MEM_PWR_SEL_CTRL MEM_PWR_SEL_CTRL2
MEM_PWR_STATUS MEM_VENDOR_e METADATA_HUBP_SEL
METADATA_STREAM_TYPE_SEL META_CHUNK_SIZE META_LINEAR
METEOR_PIXTYPE MFW_VOLT_PLANE_e MICHAEL_CTX
MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL MICRO_TILE_MODE_NEW MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL
MIN_CHUNK_SIZE MIN_META_CHUNK_SIZE MMHUBBUB_XFC_FRAME_MODE_ENUM
MMHUBBUB_XFC_PIXEL_FORMAT_ENUM MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM MMHUBBUB_XFC_XFCMON_MODE_ENUM
MPCC_BG_COLOR_BPC MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY MPCC_CONTROL_MPCC_ALPHA_BLND_MODE
MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE MPCC_CONTROL_MPCC_BOT_GAIN_MODE MPCC_CONTROL_MPCC_MODE
MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM MPCC_GAMUT_REMAP_MODE_ENUM MPCC_MCM_3DLUT_30BIT_ENUM
MPCC_MCM_3DLUT_RAM_SEL MPCC_MCM_3DLUT_SIZE_ENUM MPCC_MCM_GAMMA_LUT_MODE_ENUM
MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM MPCC_MCM_GAMMA_LUT_SEL_ENUM MPCC_MCM_LUT_2_MODE_ENUM
MPCC_MCM_LUT_CONFIG_MODE MPCC_MCM_LUT_NUM_SEG MPCC_MCM_LUT_RAM_SEL
MPCC_MCM_LUT_READ_COLOR_SEL MPCC_MCM_LUT_READ_DBG MPCC_MCM_MEM_PWR_FORCE_ENUM
MPCC_MCM_MEM_PWR_STATE_ENUM MPCC_OGAM_LUT_2_CONFIG_ENUM MPCC_OGAM_LUT_CONFIG_MODE
MPCC_OGAM_LUT_PWL_DISABLE_ENUM MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL MPCC_OGAM_LUT_RAM_SEL
MPCC_OGAM_LUT_READ_COLOR_SEL MPCC_OGAM_LUT_READ_DBG MPCC_OGAM_LUT_SEL_ENUM
MPCC_OGAM_MODE_MPCC_OGAM_MODE MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM MPCC_OGAM_NUM_SEG
MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN MPCC_SM_CONTROL_MPCC_SM_EN MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT
MPCC_SM_CONTROL_MPCC_SM_MODE MPCC_STALL_STATUS_MPCC_STALL_INT_ACK MPCC_STALL_STATUS_MPCC_STALL_INT_MASK
MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET
MPC_CFG_ADR_VUPDATE_LOCK_SET MPC_CFG_CFG_VUPDATE_LOCK_SET MPC_CFG_CUR_VUPDATE_LOCK_SET
MPC_CFG_MPC_TEST_CLK_SEL MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN MPC_CRC_CALC_INTERLACE_MODE
MPC_CRC_CALC_MODE MPC_CRC_CALC_STEREO_MODE MPC_CRC_SOURCE_SELECT
MPC_DEBUG_BUS1_DATA_SELECT MPC_DEBUG_BUS2_DATA_SELECT MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT
MPC_DEBUG_BUS_MPCC_BYTE_SELECT MPC_OCSC_COEF_FORMAT MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN
MPC_OUT_CSC_MODE MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE MPC_OUT_RATE_CONTROL_DISABLE_SET
MPTE_GROUP_SIZE MTYPE MVPP2_BUFF_HDR
MVP_CLK_SRC_SEL MVP_SOFT_RESET MacroTileAspect
MemArbMode MemoryType_e MetricsMember_t
MicroTileMode Microseconds Mode_Reset_e
MsgLimits_t MultiGPUTileSize NISLANDS_SMC_HW_PERFORMANCE_LEVEL
NISLANDS_SMC_MCLK_VALUE NISLANDS_SMC_SCLK_VALUE NISLANDS_SMC_STATETABLE
NISLANDS_SMC_SWSTATE NISLANDS_SMC_VOLTAGEMASKTABLE NISLANDS_SMC_VOLTAGE_VALUE
NO_SIZE_T NUM_BANKS NUM_BANKS_BC_ENUM
NUM_PIPES NUM_PIPES_BC_ENUM NUM_RB_PER_SE
NUM_SE NewTpl NonClockInfoArray
NonDispTilingOrder NumBanks NumBanksConfig
NumGPUs NumLowerPipes NumMaxCompressedFragments
NumPipes NumRbPerShaderEngine NumShaderEngines
OBUF_BYPASS_SEL OBUF_IS_HALF_RECOUT_WIDTH_SEL OBUF_USE_FULL_BUFFER_SEL
OF OFS OPPBUF_DISPLAY_SEGMENTATION
OPP_ABM_DEBUG_BUS_SELECT_CONTROL OPP_DPG_DEBUG_BUS_SELECT_CONTROL OPP_FMT_DEBUG_BUS_SELECT_CONTROL
OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL OPP_PIPE_CLOCK_ENABLE_CONTROL
OPP_PIPE_CRC_CONT_EN OPP_PIPE_CRC_EN OPP_PIPE_CRC_INTERLACE_EN
OPP_PIPE_CRC_INTERLACE_MODE OPP_PIPE_CRC_ONE_SHOT_PENDING OPP_PIPE_CRC_PIXEL_SELECT
OPP_PIPE_CRC_SOURCE_SELECT OPP_PIPE_CRC_STEREO_EN OPP_PIPE_CRC_STEREO_MODE
OPP_PIPE_DIGTIAL_BYPASS_CONTROL OPP_TEST_CLK_SEL_CONTROL OPP_TOP_CLOCK_ENABLE_STATUS
OPP_TOP_CLOCK_GATING_CONTROL OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE
OTG_ADD_PIXEL OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE
OTG_CONTROL_OTG_DISABLE_POINT_CNTL OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE OTG_CONTROL_OTG_FIELD_NUMBER_CNTL
OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY OTG_CONTROL_OTG_MASTER_EN OTG_CONTROL_OTG_OUT_MUX
OTG_CONTROL_OTG_SOF_PULL_EN OTG_CONTROL_OTG_START_POINT_CNTL OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN
OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE
OTG_CRC_CNTL2_OTG_CRC_DSC_MODE OTG_CRC_CNTL_OTG_CRC1_EN OTG_CRC_CNTL_OTG_CRC_CONT_EN
OTG_CRC_CNTL_OTG_CRC_CONT_MODE OTG_CRC_CNTL_OTG_CRC_EN OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE
OTG_CRC_CNTL_OTG_CRC_STEREO_MODE OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT OTG_DIG_UPDATE_VCOUNT_MODE OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN
OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY
OTG_DROP_PIXEL OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE
OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE
OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL
OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL
OTG_GLOBAL_UPDATE_LOCK_EN OTG_GSL_MASTER_MODE OTG_HORZ_REPETITION_COUNT
OTG_H_SYNC_A_POL OTG_H_TIMING_DIV_BY2 OTG_H_TIMING_DIV_BY2_UPDATE_MODE
OTG_H_TIMING_DIV_MODE OTG_H_TIMING_DIV_MODE_MANUAL OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE
OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE
OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK
OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE
OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK
OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE
OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
OTG_MASTER_UPDATE_LOCK_DB_EN OTG_MASTER_UPDATE_LOCK_GSL_EN OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE
OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR
OTG_PIPE_ABORT OTG_PTI_CONTROL_OTG_PIT_EN OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL
OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN
OTG_START_LINE_CONTROL_OTG_PREFETCH_EN OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE
OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL OTG_STEREO_CONTROL_OTG_STEREO_EN
OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE
OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT OTG_TRIGA_FALLING_EDGE_DETECT_CNTL
OTG_TRIGA_FREQUENCY_SELECT OTG_TRIGA_RISING_EDGE_DETECT_CNTL OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT OTG_TRIGB_FALLING_EDGE_DETECT_CNTL OTG_TRIGB_FREQUENCY_SELECT
OTG_TRIGB_RISING_EDGE_DETECT_CNTL OTG_UPDATE_LOCK_OTG_UPDATE_LOCK OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE
OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE
OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR OTG_VUPDATE_BLOCK_DISABLE OTG_V_SYNC_A_POL
OTG_V_SYNC_MODE OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT
OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL
OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK
OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR OUT OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE OVERRIDE_CGTT_DCEFCLK OVERRIDE_CGTT_SCLK
OWER_SOURCE_e OldTpl OreoMode
OutOfBandMonitor_t OverDriveLimits_t OverDriveTableExternal_t
OverDriveTable_t PADDRESS_LENGTH_PAIR PALETTE_DATA_CONTROL_PARAMETERS_V3
PCCARD_DEVICE_PATH PCI_DEVICE_PATH PCLK_e
PDESC_ARRAY PERFCOUNTER_ACTIVE PERFCOUNTER_CNT0_STATE
PERFCOUNTER_CNT1_STATE PERFCOUNTER_CNT2_STATE PERFCOUNTER_CNT3_STATE
PERFCOUNTER_CNT4_STATE PERFCOUNTER_CNT5_STATE PERFCOUNTER_CNT6_STATE
PERFCOUNTER_CNT7_STATE PERFCOUNTER_CNTL_SEL PERFCOUNTER_CNTOFF_START_DIS
PERFCOUNTER_COUNTED_VALUE_TYPE PERFCOUNTER_CVALUE_SEL PERFCOUNTER_HW_CNTL_SEL
PERFCOUNTER_HW_STOP1_SEL PERFCOUNTER_HW_STOP2_SEL PERFCOUNTER_INC_MODE
PERFCOUNTER_INT_EN PERFCOUNTER_INT_TYPE PERFCOUNTER_OFF_MASK
PERFCOUNTER_RESTART_EN PERFCOUNTER_RUNEN_MODE PERFCOUNTER_STATE_SEL0
PERFCOUNTER_STATE_SEL1 PERFCOUNTER_STATE_SEL2 PERFCOUNTER_STATE_SEL3
PERFCOUNTER_STATE_SEL4 PERFCOUNTER_STATE_SEL5 PERFCOUNTER_STATE_SEL6
PERFCOUNTER_STATE_SEL7 PERFMON_CNTOFF_AND_OR PERFMON_CNTOFF_INT_EN
PERFMON_CNTOFF_INT_TYPE PERFMON_COUNTER_MODE PERFMON_SPM_MODE
PERFMON_STATE PGID PHYSYMCLK_FORCE_EN
PHYSYMCLK_FORCE_SRC_SEL PHY_ANALOG_SETTING_INFO PHY_ANALOG_SETTING_INFO_V2
PHY_CONDITION_REG_INFO PHY_CONDITION_REG_INFO_V2 PHY_CONDITION_REG_VAL
PHY_CONDITION_REG_VAL_V2 PH_PERFCNT_SEL PIPE_ALIGNED
PIPE_COMPAT_LEVEL PIPE_CONFIG PIPE_INTERLEAVE
PIPE_INT_MASK_MODE PIPE_INT_TYPE_MODE PIPE_IN_FLUSH_URGENT
PIPE_PHYPLL_PIXEL_RATE_SOURCE PIPE_PIXEL_RATE_PLL_SOURCE PIPE_PIXEL_RATE_SOURCE
PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE PIXEL_CLOCK_PARAMETERS PIXEL_CLOCK_PARAMETERS_V2
PIXEL_CLOCK_PARAMETERS_V3 PIXEL_CLOCK_PARAMETERS_V5 PIXEL_CLOCK_PARAMETERS_V6
PIXEL_CLOCK_PARAMETERS_V7 PIX_EXPAND_MODE PLL_CFG_IF_SOFT_RESET
PM_ASSERT_RESET POWER_CONNECTOR_DETECTION_PARAMETERS POWER_CONNECTOR_DETECTION_PS_ALLOCATION
POWER_STATE_ENUM PPTable_Generic_SubTable_Header PRE_CSC_MODE_ENUM
PRE_DEGAM_MODE PRE_DEGAM_SELECT PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS PRODUCT_BRANDING
PRQ_MRQ_FLUSH_URGENT PSMC_Msg PSMC_Result
PTE_BUFFER_MODE PTE_ROW_HEIGHT_LINEAR PTR_32_BIT_STRUCTURE
PTR_32_BIT_UNION PT_THROTTLER_e PTable_beige_goby_t
PTable_t PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN
PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT PWRSEQ_BL_PWM_CNTL_BL_PWM_EN PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN
PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN PWRSEQ_BL_PWM_GRP1_REG_LOCK
PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START PWRSEQ_GPIO_MASK_EN PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON
PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL
PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN
P_Clock P_GRTAVFS_FW_COMMON_FUSE_e P_GRTAVFS_FW_SEP_FUSE_e
P_GRTAVFS_HW_FUSE_e P_NIslands_CACTABLES P_NIslands_DPM2Parameters
P_NIslands_Dpm2PerfLevel P_OD_POWER_FEATURE_e P_PCIEGen
P_SIslands_CacConfig P_SIslands_DPM2Parameters P_SIslands_DPM2Status
P_SIslands_Dpm2PerfLevel P_SIslands_FanTable P_SIslands_PAPMParameters
P_SIslands_PAPMStatus P_StateClassificationFlags PerfCounter_Vals
PhSPIstatusMode PhysMem PipeConfig
PipeInterleaveSize PipeTiling PixelPipeCounterId
PixelPipeStride PkrMap PkrXsel
PkrXsel2 PkrYsel QuadExportFormat
QuadExportFormatOld QuadraticFixedPoint_t QuadraticInt_t
RB_ALIGNED RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN
RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS
RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN
RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN
RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET
RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK RDPCSPIPE_DBG_OCLA_SEL RDPCSPIPE_ENC_TYPE
RDPCSPIPE_FIFO_EMPTY RDPCSPIPE_FIFO_FULL RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK
RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE
RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK
RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK RDPCSPIPE_PACK_MODE RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL
RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE
RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV
RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT
RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE
RDPCSPIPE_PHY_IF_WIDTH RDPCSPIPE_PHY_RATE RDPCSPIPE_PHY_REF_ALT_CLK_EN
RDPCSPIPE_TEST_CLK_SEL RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_BYPASS
RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS
RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_CLOCK_ON RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_EN RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_GATE_DIS
RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_TX_EN RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET
RDPCSTX_CNTL_RDPCS_TX_FIFO_EN RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET
RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE
RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK
RDPCSTX_MEM_POWER_CTRL2_RDPCS_MEM_POWER_CTRL_POFF RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL
RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE
RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV
RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE
RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB
RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE RDPCS_TEST_CLK_SEL
RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
READ_EFUSE_VALUE_PARAMETER REALADR REFCLK_CLOCK_EN
REFCLK_SRC_SEL RESPONSE_STATUS RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL
RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL RLC_DOORBELL_MODE RLC_PERFCOUNTER_SEL
RLC_PERFMON_STATE RLC_TABLE_OF_CONTENT RMD160_CTX
RMIPerfSel RMI_CID ROTATION_ANGLE
ROW_TTU_MODE RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK RRIP_TABLE
RSPM_CMD RV730_SMC_MCLK_VALUE RV770_SMC_HW_PERFORMANCE_LEVEL
RV770_SMC_MCLK_VALUE RV770_SMC_SCLK_VALUE RV770_SMC_STATETABLE
RV770_SMC_SWSTATE RV770_SMC_VOLTAGEMASKTABLE RV770_SMC_VOLTAGE_VALUE
RV7XX_SMC_MCLK_VALUE RbMap RbXsel
RbXsel2 RbYsel ReadPolicy
ReadSize RevComponent RingCounterControl
RlcPaceFlopsPerByteOverrideExternal_t RlcPaceFlopsPerByteOverride_t RoundMode
RowSize RowTiling SATA_DEVICE_PATH
SCLV_COEF_UPDATE_COMPLETE SCLV_INTERLACE_SOURCE SCLV_MODE_SEL
SCLV_UPDATE_LOCK SCL_2TAP_HARDCODE SCL_ALPHA_COEF
SCL_ALU_DISABLE SCL_AUTOCAL_MODE SCL_BOUNDARY
SCL_BOUNDARY_MODE SCL_BYPASS_MODE SCL_CHROMA_COEF
SCL_COEF_FILTER_TYPE_SEL SCL_COEF_RAM_SEL SCL_COEF_UPDATE_COMPLETE
SCL_C_RAM_FILTER_TYPE SCL_C_RAM_PHASE SCL_C_RAM_TAP_PAIR_IDX
SCL_EARLY_EOL_MOD SCL_HF_SHARP_EN SCL_HF_SHARP_SCALE_FACTOR
SCL_HOST_CONFLICT_MASK SCL_H_2TAP_HARDCODE_COEF_EN SCL_H_CALC_AUTO_RATIO_EN
SCL_H_FILTER_PICK_NEAREST SCL_H_MANUAL_REPLICATE_FACTOR SCL_H_NUM_OF_TAPS
SCL_MODE_SEL SCL_PSCL_EN SCL_SCL_MODE_CHANGE_MASK
SCL_SHARP_EN SCL_UPDATE_LOCK SCL_UPDATE_TAKEN
SCL_VF_SHARP_EN SCL_VF_SHARP_SCALE_FACTOR SCL_V_2TAP_HARDCODE_COEF_EN
SCL_V_CALC_AUTO_RATIO_EN SCL_V_FILTER_PICK_NEAREST SCL_V_MANUAL_REPLICATE_FACTOR
SCL_V_NUM_OF_TAPS SCSI_DEVICE_PATH SCS_CELL_t
SC_PERFCNT_SEL SC_SCSI_INQ0 SC_SCSI_INQ1
SC_SCSI_INQ2 SC_SCSI_INQ3 SC_SCSI_INQ7
SC_SCSI_INQUIRY SDMA_PERFMON_SEL SDMA_PERF_SEL
SEGDESC_t SEGOFF16_t SEGSEL_t
SELECT_CRTC_SOURCE_PARAMETERS SELECT_CRTC_SOURCE_PARAMETERS_V2 SELECT_CRTC_SOURCE_PARAMETERS_V3
SEM_PERF_SEL SERIAL_IO_INTERFACE SERIAL_IO_MODE
SET_CRTC_OVERSCAN_PARAMETERS SET_CRTC_REPLICATION_PARAMETERS SET_CRTC_TIMING_PARAMETERS
SET_CRTC_USING_DTD_TIMING_PARAMETERS SET_DCE_CLOCK_PARAMETERS_V1_1 SET_DCE_CLOCK_PARAMETERS_V2_1
SET_DCE_CLOCK_PS_ALLOCATION_V1_1 SET_DCE_CLOCK_PS_ALLOCATION_V2_1 SET_ENGINE_CLOCK_PARAMETERS
SET_ENGINE_CLOCK_PS_ALLOCATION SET_ENGINE_CLOCK_PS_ALLOCATION_V1_2 SET_HWBLOCK_INSTANCE_PARAMETER_V2
SET_MEMORY_CLOCK_PARAMETERS SET_MEMORY_CLOCK_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION
SET_PIXEL_CLOCK_PS_ALLOCATION_V5 SET_PIXEL_CLOCK_PS_ALLOCATION_V6 SET_UP_HW_I2C_DATA_PARAMETERS
SET_VOLTAGE_PARAMETERS SET_VOLTAGE_PARAMETERS_V1_3 SET_VOLTAGE_PARAMETERS_V2
SET_VOLTAGE_PS_ALLOCATION SHA1_CTX SHA2_CTX
SH_MEM_ADDRESS_MODE SH_MEM_ALIGNMENT_MODE SH_MEM_RETRY_MODE
SID SIMPLEQ_HEAD SIMPLE_INPUT_INTERFACE
SIMPLE_TEXT_OUTPUT_INTERFACE SIMPLE_TEXT_OUTPUT_MODE SIPHASH_CTX
SIPHASH_KEY SISLANDS_SMC_HW_PERFORMANCE_LEVEL SISLANDS_SMC_MCLK_VALUE
SISLANDS_SMC_SCLK_VALUE SISLANDS_SMC_STATETABLE SISLANDS_SMC_SWSTATE
SISLANDS_SMC_VOLTAGEMASKTABLE SISLANDS_SMC_VOLTAGE_VALUE SLIST_HEAD
SMARTSHIFT_VERSION_e SMC_Evergreen_MCRegisterAddress SMC_Evergreen_MCRegisterSet
SMC_Evergreen_MCRegisters SMC_NISLANDS_MC_TPP_CAC_TABLE SMC_NISLANDS_SPLL_DIV_TABLE
SMC_NIslands_MCArbDramTimingRegisterSet SMC_NIslands_MCArbDramTimingRegisters SMC_NIslands_MCRegisterAddress
SMC_NIslands_MCRegisterSet SMC_NIslands_MCRegisters SMC_SISLANDS_SPLL_DIV_TABLE
SMC_SIslands_MCArbDramTimingRegisterSet SMC_SIslands_MCArbDramTimingRegisters SMC_SIslands_MCRegisterAddress
SMC_SIslands_MCRegisterSet SMC_SIslands_MCRegisters SMIO_Pattern
SMIO_Table SMU71_AcpiScoreboard SMU71_Discrete_ACPILevel
SMU71_Discrete_Cac_Collection_Table SMU71_Discrete_Cac_Verification_Table SMU71_Discrete_DpmTable
SMU71_Discrete_ExtClkLevel SMU71_Discrete_FanTable SMU71_Discrete_GraphicsLevel
SMU71_Discrete_LinkLevel SMU71_Discrete_Log_Cntl SMU71_Discrete_Log_Header_Table
SMU71_Discrete_MCArbDramTimingTable SMU71_Discrete_MCArbDramTimingTableEntry SMU71_Discrete_MCRegisterAddress
SMU71_Discrete_MCRegisterSet SMU71_Discrete_MCRegisters SMU71_Discrete_MemoryLevel
SMU71_Discrete_PmFuses SMU71_Discrete_StateInfo SMU71_Discrete_Ulv
SMU71_Discrete_UvdLevel SMU71_Discrete_VoltageLevel SMU71_Firmware_Header
SMU71_MclkDpmScoreboard SMU71_PIDController SMU71_SoftRegisters
SMU71_UlvScoreboard SMU71_VddGfxScoreboard SMU72_Discrete_ACPILevel
SMU72_Discrete_DpmTable SMU72_Discrete_ExtClkLevel SMU72_Discrete_FanTable
SMU72_Discrete_GraphicsLevel SMU72_Discrete_LinkLevel SMU72_Discrete_MCArbDramTimingTable
SMU72_Discrete_MCArbDramTimingTableEntry SMU72_Discrete_MCRegisterAddress SMU72_Discrete_MCRegisterSet
SMU72_Discrete_MCRegisters SMU72_Discrete_MemoryLevel SMU72_Discrete_PmFuses
SMU72_Discrete_StateInfo SMU72_Discrete_Ulv SMU72_Discrete_UvdLevel
SMU72_Firmware_Header SMU72_PIDController SMU72_SoftRegisters
SMU73_Discrete_ACPILevel SMU73_Discrete_DpmTable SMU73_Discrete_ExtClkLevel
SMU73_Discrete_FanTable SMU73_Discrete_GraphicsLevel SMU73_Discrete_LinkLevel
SMU73_Discrete_MCArbDramTimingTable SMU73_Discrete_MCArbDramTimingTableEntry SMU73_Discrete_MemoryLevel
SMU73_Discrete_PmFuses SMU73_Discrete_StateInfo SMU73_Discrete_Ulv
SMU73_Discrete_UvdLevel SMU73_Firmware_Header SMU73_PIDController
SMU73_SoftRegisters SMU74_Discrete_ACPILevel SMU74_Discrete_DpmTable
SMU74_Discrete_ExtClkLevel SMU74_Discrete_FanTable SMU74_Discrete_GraphicsLevel
SMU74_Discrete_LinkLevel SMU74_Discrete_MCArbDramTimingTable SMU74_Discrete_MCArbDramTimingTableEntry
SMU74_Discrete_MemoryLevel SMU74_Discrete_PmFuses SMU74_Discrete_StateInfo
SMU74_Discrete_Ulv SMU74_Discrete_UvdLevel SMU74_Firmware_Header
SMU74_PIDController SMU74_SoftRegisters SMU75_Discrete_ACPILevel
SMU75_Discrete_DpmTable SMU75_Discrete_ExtClkLevel SMU75_Discrete_FanTable
SMU75_Discrete_GraphicsLevel SMU75_Discrete_LinkLevel SMU75_Discrete_MCArbDramTimingTable
SMU75_Discrete_MCArbDramTimingTableEntry SMU75_Discrete_MemoryLevel SMU75_Discrete_PmFuses
SMU75_Discrete_StateInfo SMU75_Discrete_Ulv SMU75_Discrete_UvdLevel
SMU75_Firmware_Header SMU75_PIDController SMU75_SoftRegisters
SMU7_AcpiScoreboard SMU7_BapmScoreboard SMU7_Discrete_ACPILevel
SMU7_Discrete_AutoWattMan_Status_Table SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Verification_Table
SMU7_Discrete_DpmTable SMU7_Discrete_ExtClkLevel SMU7_Discrete_FanTable
SMU7_Discrete_GraphicsLevel SMU7_Discrete_LinkLevel SMU7_Discrete_Log_Cntl
SMU7_Discrete_Log_Header_Table SMU7_Discrete_MCArbDramTimingTable SMU7_Discrete_MCArbDramTimingTableEntry
SMU7_Discrete_MCRegisterAddress SMU7_Discrete_MCRegisterSet SMU7_Discrete_MCRegisters
SMU7_Discrete_MemoryLevel SMU7_Discrete_PmFuses SMU7_Discrete_Pm_Status_Table
SMU7_Discrete_StateInfo SMU7_Discrete_Ulv SMU7_Discrete_UvdLevel
SMU7_Discrete_VoltageLevel SMU7_Firmware_Header SMU7_Fusion_ACPILevel
SMU7_Fusion_DpmTable SMU7_Fusion_ExtClkLevel SMU7_Fusion_GIODpmTable
SMU7_Fusion_GIOLevel SMU7_Fusion_GraphicsLevel SMU7_Fusion_NbDpm
SMU7_Fusion_StateInfo SMU7_Fusion_UvdLevel SMU7_GfxCuPgScoreboard
SMU7_HystController_Data SMU7_LocalDpmScoreboard SMU7_Local_Cac
SMU7_Local_Cac_Table SMU7_MclkDpmScoreboard SMU7_PCIeLinkSpeedScoreboard
SMU7_PIDController SMU7_PkgPwrLimitScoreboard SMU7_Poly3rdOrder_Data
SMU7_PowerScoreboard SMU7_SoftRegisters SMU7_TdcLimitScoreboard
SMU7_ThermalScoreboard SMU7_UlvScoreboard SMU7_VddGfxScoreboard
SMU7_VoltageScoreboard SMU_CKS_LOOKUPTable SMU_CKS_LOOKUPTableEntry
SMU_ClockStretcherDataTable SMU_ClockStretcherDataTableEntry SMU_INTR
SMU_MetaData_Mode0 SMU_MetaData_Mode1 SMU_MetaData_Mode2
SMU_MetaData_Mode3 SMU_QuadraticCoeffs SMU_SclkSetting
SMU_Task SMU_VoltageLevel SOC21_FIRMWARE_ID
SOCParametersList SOFT_RESET SPDIF1_SOFT_RESET
SPDIF_INVERT_EN SPI_FOG_MODE SPI_LB_WAVES_SELECT
SPI_PERFCNT_SEL SPI_PNT_SPRITE_OVERRIDE SPI_PS_LDS_GROUP_SIZE
SPI_SAMPLE_CNTL SPI_SHADER_EX_FORMAT SPI_SHADER_FORMAT
SPM_PERFMON_STATE SQC_DATA_CACHE_POLICIES SQG_PERF_SEL
SQ_CAC_POWER_SEL SQ_DED_INFO_SOURCE SQ_EDC_INFO_SOURCE
SQ_IBUF_ST SQ_IMG_FILTER_TYPE SQ_IND_CMD_CMD
SQ_IND_CMD_MODE SQ_INST_STR_ST SQ_INST_TYPE
SQ_INTERRUPT_WORD_ENCODING SQ_LB_CTR_SEL_VALUES SQ_LLC_CTL
SQ_NO_INST_ISSUE SQ_OOB_SELECT SQ_PERF_SEL
SQ_ROUND_MODE SQ_RSRC_BUF_TYPE SQ_RSRC_FLAT_TYPE
SQ_RSRC_IMG_TYPE SQ_SEL_XYZW01 SQ_TEX_ANISO_RATIO
SQ_TEX_BORDER_COLOR SQ_TEX_CLAMP SQ_TEX_DEPTH_COMPARE
SQ_TEX_MIP_FILTER SQ_TEX_XY_FILTER SQ_TEX_Z_FILTER
SQ_THREAD_TRACE_CAPTURE_MODE SQ_THREAD_TRACE_INST_TYPE SQ_THREAD_TRACE_ISSUE
SQ_THREAD_TRACE_ISSUE_MASK SQ_THREAD_TRACE_MISC_TOKEN_TYPE SQ_THREAD_TRACE_MODE_SEL
SQ_THREAD_TRACE_REG_OP SQ_THREAD_TRACE_REG_TYPE SQ_THREAD_TRACE_TOKEN_TYPE
SQ_THREAD_TRACE_VM_ID_MASK SQ_THREAD_TRACE_WAVE_MASK SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX
SQ_TT_MODE SQ_TT_RT_FREQ SQ_TT_TOKEN_MASK_INST_EXCLUDE
SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT SQ_TT_TOKEN_MASK_REG_EXCLUDE SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT
SQ_TT_TOKEN_MASK_REG_INCLUDE SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT
SQ_TT_UTIL_TIMER SQ_TT_WAVESTART_MODE SQ_TT_WTYPE_INCLUDE
SQ_TT_WTYPE_INCLUDE_SHIFT SQ_WATCH_MODES SQ_WAVE_FWD_PROG_INTERVAL
SQ_WAVE_IB_ECC_ST SQ_WAVE_SCHED_MODES SQ_WAVE_TYPE
SRBM_GFX_CNTL_SEL SRBM_PERFCOUNT1_SEL STATIC_SCREEN_SMU_INTR
STREAM_0_SYNCHRONIZATION STREAM_10_SYNCHRONIZATION STREAM_11_SYNCHRONIZATION
STREAM_12_SYNCHRONIZATION STREAM_13_SYNCHRONIZATION STREAM_14_SYNCHRONIZATION
STREAM_15_SYNCHRONIZATION STREAM_1_SYNCHRONIZATION STREAM_2_SYNCHRONIZATION
STREAM_3_SYNCHRONIZATION STREAM_4_SYNCHRONIZATION STREAM_5_SYNCHRONIZATION
STREAM_6_SYNCHRONIZATION STREAM_7_SYNCHRONIZATION STREAM_8_SYNCHRONIZATION
STREAM_9_SYNCHRONIZATION SURFACE_DCC SURFACE_DCC_IND_128B
SURFACE_DCC_IND_64B SURFACE_DCC_IND_BLK SURFACE_FLIP_AWAY_INT_TYPE
SURFACE_FLIP_EXEC_DEBUG_MODE SURFACE_FLIP_INT_TYPE SURFACE_FLIP_IN_STEREOSYNC
SURFACE_FLIP_MODE_FOR_STEREOSYNC SURFACE_FLIP_STEREO_SELECT_DISABLE SURFACE_FLIP_STEREO_SELECT_POLARITY
SURFACE_FLIP_TYPE SURFACE_FLIP_VUPDATE_SKIP_NUM SURFACE_INUSE_RAED_NO_LATCH
SURFACE_PIXEL_FORMAT SURFACE_TMZ SURFACE_UPDATE_LOCK
SU_PERFCNT_SEL SVI_PLANE_e SVI_PSI_e
SWATH_HEIGHT SWIZZLE_MODE_ENUM SWIZZLE_TYPE_ENUM
SW_I2C_CNTL_DATA_PARAMETERS SW_I2C_IO_DATA_PARAMETERS SW_MODE
SX_BLEND_OPT SX_DOWNCONVERT_FORMAT SX_OPT_COMB_FCN
SX_PERFCOUNTER_VALS SYMCLK_FE_FORCE_EN SYMCLK_FE_FORCE_SRC
SYS_GRBM_GFX_INDEX_SEL SampleSplit SampleSplitBytes
ScMap ScUncertaintyRegionMode ScUncertaintyRegionMult
ScXsel ScYsel SeEnable
SeMap SePairMap SePairXsel
SePairYsel SeXsel SeYsel
ShaderEngineTileSize SkuTable_t Smc_SIslands_DTE_Configuration
SmuMetricsExternal_t SmuMetricsTable_t SmuMetrics_NV12_legacy_t
SmuMetrics_NV12_t SmuMetrics_NV1X_t SmuMetrics_V2_t
SmuMetrics_V3_t SmuMetrics_V4_t SmuMetrics_legacy_t
SmuMetrics_t SourceFormat StateArray
StencilFormat StencilOp SurfaceArray
SurfaceEndian SurfaceFormat SurfaceNumber
SurfaceSwap SurfaceTiling SviTelemetryScale_t
SwI2cCmd_t SwI2cRequestExternal_t SwI2cRequest_t
TAILQ_HEAD TA_PERFCOUNT_SEL TA_TC_ADDR_MODES
TA_TC_REQ_MODES TCA_PERF_SEL TCC_CACHE_POLICIES
TCC_MTYPE TCC_PERF_SEL TCP_CACHE_POLICIES
TCP_CACHE_STORE_POLICIES TCP_DSM_DATA_SEL TCP_DSM_INJECT_SEL
TCP_DSM_SINGLE_WRITE TCP_OPCODE_TYPE TCP_PERFCOUNT_SELECT
TCP_WATCH_MODES TCS_PERF_SEL TC_CHUB_REQ_CREDITS_ENUM
TC_EA_CID TC_MICRO_TILE_MODE TC_NACKS
TC_OP TC_OP_MASKS TDC_THROTTLER_e
TD_PERFCOUNT_SEL TEMP_TYPE_e TEMP_e
TEST_CLK_DIV_SEL TEST_CLK_SEL TEST_CLOCK_MUX_SELECT_ENUM
TEX_BC_SWIZZLE TEX_BORDER_COLOR_TYPE TEX_CHROMA_KEY
TEX_CLAMP TEX_COORD_TYPE TEX_DEPTH_COMPARE_FUNCTION
TEX_DIM TEX_FORMAT_COMP TEX_MAX_ANISO_RATIO
TEX_MIP_FILTER TEX_REQUEST_SIZE TEX_SAMPLER_TYPE
TEX_XY_FILTER TEX_Z_FILTER TILE_NUM_e
TILE_SPLIT TMDS_COLOR_FORMAT TMDS_CTL0_DATA_DELAY
TMDS_CTL0_DATA_INVERT TMDS_CTL0_DATA_MODULATION TMDS_CTL0_DATA_SEL
TMDS_CTL0_PATTERN_OUT_EN TMDS_CTL1_DATA_DELAY TMDS_CTL1_DATA_INVERT
TMDS_CTL1_DATA_MODULATION TMDS_CTL1_DATA_SEL TMDS_CTL1_PATTERN_OUT_EN
TMDS_CTL2_DATA_DELAY TMDS_CTL2_DATA_INVERT TMDS_CTL2_DATA_MODULATION
TMDS_CTL2_DATA_SEL TMDS_CTL2_PATTERN_OUT_EN TMDS_CTL3_DATA_DELAY
TMDS_CTL3_DATA_INVERT TMDS_CTL3_DATA_MODULATION TMDS_CTL3_DATA_SEL
TMDS_CTL3_PATTERN_OUT_EN TMDS_DATA_SYNCHRONIZATION_DSINTSEL TMDS_DVO_MUX_SELECT
TMDS_MUX_SELECT TMDS_PIXEL_ENCODING TMDS_REG_TEST_OUTPUTA_CNTLA
TMDS_REG_TEST_OUTPUTB_CNTLB TMDS_STEREOSYNC_CTL_SEL_REG TMDS_SYNC_PHASE
TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB TMDS_TRANSMITTER_CONTROL_IDSCKSELA
TMDS_TRANSMITTER_CONTROL_IDSCKSELB TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK
TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS
TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS TMDS_TRANSMITTER_ENABLE_HPD_MASK TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK
TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK TOM_FIRMWARE_CAPABILITY_ACCESS TOM_MODE_MISC_INFO_ACCESS
TOM_PPLIB_CAC_Leakage_Record TOM_VEGA12_ODSETTING_ID TOM_VEGA12_PPCLOCK_ID
TOM_VEGA20_ODSETTING_ID TOM_VEGA20_PPCLOCK_ID TSPCON
TS_GR TVX_DATA_FORMAT TVX_DST_SEL
TVX_ENDIAN_SWAP TVX_INST TVX_NUM_FORMAT_ALL
TVX_SRC_SEL TVX_SRF_MODE_ALL TVX_TYPE
TV_ENCODER_CONTROL_PARAMETERS TV_ENCODER_CONTROL_PS_ALLOCATION This
TileSplit TileType Time
UART_DEVICE_PATH UCHAR UCLK_DIV_e
UCLK_DPM_MODE_e UDP_PORT_t UEFI_ACPI_VFCT
UINT16 UINT32 UINT32_T
UINT64 UINT8 UINTN
ULONG UNKNOWN_DEVICE_VENDOR_DEVICE_PATH UNP_BUFFER_MODE
UNP_CRC_LINE_SEL UNP_CRC_SOURCE_SEL UNP_GRPH_ADDRESS_TRANSLATION_ENABLE
UNP_GRPH_BANK_HEIGHT UNP_GRPH_BANK_WIDTH UNP_GRPH_BLUE_CROSSBAR
UNP_GRPH_COLOR_EXPANSION_MODE UNP_GRPH_DEPTH UNP_GRPH_EN
UNP_GRPH_ENDIAN_SWAP UNP_GRPH_GREEN_CROSSBAR UNP_GRPH_MACRO_TILE_ASPECT
UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE UNP_GRPH_MODE_UPDATE_LOCKG UNP_GRPH_NUM_BANKS
UNP_GRPH_PRIVILEGED_ACCESS_ENABLE UNP_GRPH_RED_CROSSBAR UNP_GRPH_STACK_INTERLACE_FLIP_EN
UNP_GRPH_STACK_INTERLACE_FLIP_MODE UNP_GRPH_STEREOSYNC_FLIP_EN UNP_GRPH_STEREOSYNC_FLIP_MODE
UNP_GRPH_STEREOSYNC_SELECT_DISABLE UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK
UNP_GRPH_TILE_SPLIT UNP_PIXEL_DROP UNP_ROTATION_ANGLE
UNP_VIDEO_FORMAT USB_CLASS_DEVICE_PATH USB_DEVICE_PATH
USE_MALL_FOR_CURSOR USE_MALL_FOR_PSTATE_CHANGE USE_MALL_FOR_STATIC_SCREEN
USHORT UTCL0FaultType UTCL0RequestType
UTCL1FaultType UTCL1PerfSel UTCL1RequestType
UVDClockInfo UVDClockInfoArray UVDFirmwareCommand
UclkDpmChangeRange_t VBE_1_2_INFO_BLOCK_UPDATABLE VBE_2_0_INFO_BLOCK_UPDATABLE
VBE_FP_INFO VBE_INFO_BLOCK VBE_VERSION_UNION
VBIOS_ROM_HEADER VCEClockInfo VCEClockInfoArray
VENDOR_DEVICE_PATH VESA_MODE_INFO_BLOCK VFCT_IMAGE_HEADER
VFS_CksOff_AvfsGbv_t VFS_CksOff_BtcGbv_t VFS_CksOff_Gbv_t
VFS_D_e VFS_Margin_t VFS_Sclk_Offset_t
VFS_TEMP_e VFS_VOLTAGE_TYPE_e VFS_meanNsigma_t
VFT_CELL_t VFT_TABLE_t VGT_CACHE_INVALID_MODE
VGT_DETECT_ONE VGT_DETECT_ZERO VGT_DIST_MODE
VGT_DI_INDEX_SIZE VGT_DI_MAJOR_MODE_SELECT VGT_DI_PRIM_TYPE
VGT_DI_SOURCE_SELECT VGT_DMA_BUF_TYPE VGT_DMA_SWAP_MODE
VGT_EVENT_TYPE VGT_GROUP_CONV_SEL VGT_GRP_PRIM_ORDER
VGT_GRP_PRIM_TYPE VGT_GS_CUT_MODE VGT_GS_MODE_TYPE
VGT_GS_OUTPRIM_TYPE VGT_INDEX_TYPE_MODE VGT_OUTPATH_SELECT
VGT_OUT_PRIM_TYPE VGT_PERFCOUNT_SELECT VGT_RDREQ_POLICY
VGT_STAGES_ES_EN VGT_STAGES_GS_EN VGT_STAGES_HS_EN
VGT_STAGES_LS_EN VGT_STAGES_VS_EN VGT_TESS_PARTITION
VGT_TESS_TOPOLOGY VGT_TESS_TYPE VMEMCMD_RETURN_ORDER
VMPG_SIZE VM_GROUP_SIZE VOID
VOLTAGE_LUT_ENTRY VOLTAGE_LUT_ENTRY_V2 VOLTAGE_MODE_e
VPG_MEM_PWR_DIS_CTRL VPG_MEM_PWR_FORCE_CTRL VRSCombinerModeSC
VRSrate VSYNC_CNT_LATCH_MASK VSYNC_CNT_REFCLK_SEL
VSYNC_CNT_RESET_SEL VTX_CLAMP VTX_FETCH_TYPE
VTX_FORMAT_COMP_ALL VTX_MEM_REQUEST_SIZE VddgfxSavedRegisters
Vega10_PPTable_Generic_SubTable_Header WATERMARKS_FLAGS_e WATERMARK_MASK_CONTROL
WBSCL_BACKPRESSURE_CNT_EN_ENUM WBSCL_COEF_FILTER_TYPE_SEL WBSCL_COEF_RAM_FILTER_TYPE_ENUM
WBSCL_COEF_RAM_PHASE_ENUM WBSCL_COEF_RAM_RD_SEL_ENUM WBSCL_COEF_RAM_SEL_ENUM
WBSCL_COEF_RAM_TAP_COEF_EN_ENUM WBSCL_COEF_RAM_TAP_PAIR_IDX_ENUM WBSCL_DATA_OVERFLOW_INT_TYPE_ENUM
WBSCL_HOST_CONFLICT_INT_TYPE_ENUM WBSCL_LB_MEM_PWR_FORCE_ENUM WBSCL_LB_MEM_PWR_MODE_SEL_ENUM
WBSCL_LUT_MEM_PWR_STATE_ENUM WBSCL_MEM_PWR_STATE_ENUM WBSCL_MODE_SEL
WBSCL_NUM_OF_TAPS_ENUM WBSCL_OUTSIDE_PIX_STRATEGY_ENUM WBSCL_PIXEL_DEPTH
WBSCL_STATUS_ACK_ENUM WBSCL_STATUS_MASK_ENUM WBSCL_TEST_CRC_CONT_EN_ENUM
WBSCL_TEST_CRC_EN_ENUM WBSCL_TEST_CRC_MASK_ENUM WB_CLK_GATE_DIS_ENUM
WB_ENABLE_ENUM WB_MEM_PWR_DIS_ENUM WB_RAM_PW_SAVE_MODE_ENUM
WB_SOFT_RESET_ENUM WB_TEST_CLK_SEL_ENUM WCK_RATIO_e
WD_IA_DRAW_REG_XFER WD_IA_DRAW_SOURCE WD_IA_DRAW_TYPE
WD_PERFCOUNT_SELECT WM_CLOCK_e WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
WR_Command_Table WR_DFY_Section WatermarkRowGeneric_t
Watermarks WatermarksExternal_t Watermarks_t
WritePolicy XENV_STATUS_t XGMI_LINK_RATE_e
XGMI_LINK_WIDTH_e XNORM XSUM_CONTEXT_T
XTAL_REF_CLOCK_SOURCE_SEL XTAL_REF_SEL ZFormat
ZLimitSumm ZModeForce ZOrder
ZSamplePosition ZStates_e Z_U4
Z_U8 ZpassControl _ATOM_FIRMWARE_CAPABILITY_ACCESS
_ATOM_MODE_MISC_INFO_ACCESS _ATOM_PPLIB_CAC_Leakage_Record _AtomCtrl_EDCLeakgeTable
_AtomCtrl_HiLoLeakageOffsetTable _EFI_BLOCK_IO _EFI_CONSOLE_CONTROL_PROTOCOL
_EFI_DEVICE_IO_INTERFACE _EFI_FILE_HANDLE _EFI_PXE_BASE_CODE
_EFI_SIMPLE_NETWORK _SERIAL_IO_INTERFACE _SIMPLE_TEXT_OUTPUT_INTERFACE
__aligned __attribute__ __be16
__be32 __be64 __blkcnt_t
__blksize_t __builtin_va_alist_t __builtin_va_list
__clock_t __clockid_t __cpu_simple_lock_t
__cpuid_t __dev_t __double_t
__fd_mask __fixpt_t __float_t
__fsblkcnt_t __fsfilcnt_t __gid_t
__gnuc_va_list __id_t __in_addr_t
__in_port_t __ino_t __int16_t
__int32_t __int64_t __int8_t
__int_fast16_t __int_fast32_t __int_fast64_t
__int_fast8_t __int_least16_t __int_least32_t
__int_least64_t __int_least8_t __intmax_t
__intptr_t __kernel_size_t __key_t
__le16 __le32 __le64
__mbstate_t __mode_t __nlink_t
__off_t __packed __paddr_t
__pid_t __psize_t __ptrdiff_t
__register_t __rlim_t __rune_t
__s16 __s32 __s64
__s8 __sa_family_t __segsz_t
__size_t __socklen_t __ssize_t
__suseconds_t __time_t __timer_t
__u16 __u32 __u64
__u8 __uid_t __uint16_t
__uint32_t __uint64_t __uint8_t
__uint_fast16_t __uint_fast32_t __uint_fast64_t
__uint_fast8_t __uint_least16_t __uint_least32_t
__uint_least64_t __uint_least8_t __uintmax_t
__uintptr_t __useconds_t __va_list
__va_list_tag __vaddr_t __vsize_t
__wchar_t __wctrans_t __wctype_t
__wint_t _atomic_lock_t _bus_dma_segment
_bus_dma_tag _bus_dmamap _bus_space
_tulip_softc_t _vcs_dpi_display_arb_params_st _vcs_dpi_display_clocks_and_cfg_st
_vcs_dpi_display_data_rq_dlg_params_st _vcs_dpi_display_data_rq_misc_params_st _vcs_dpi_display_data_rq_regs_st
_vcs_dpi_display_data_rq_sizing_params_st _vcs_dpi_display_dlg_regs_st _vcs_dpi_display_dlg_sys_params_st
_vcs_dpi_display_e2e_pipe_params_st _vcs_dpi_display_output_params_st _vcs_dpi_display_pipe_dest_params_st
_vcs_dpi_display_pipe_params_st _vcs_dpi_display_pipe_source_params_st _vcs_dpi_display_rq_dlg_params_st
_vcs_dpi_display_rq_misc_params_st _vcs_dpi_display_rq_params_st _vcs_dpi_display_rq_regs_st
_vcs_dpi_display_rq_sizing_params_st _vcs_dpi_display_ttu_regs_st _vcs_dpi_ip_params_st
_vcs_dpi_scaler_ratio_depth_st _vcs_dpi_scaler_taps_st _vcs_dpi_soc_bounding_box_st
_vcs_dpi_voltage_scaling_st aac_lock_t ac_code
acpi_handle acpi_pwrreshead_t acpi_qhead_t
acpi_size acpi_status acpi_wakeqhead_t
ad1848_devmap_t adb_event_t adv_ccb
adw_carrier adw_ccb aes_key_wrap_ctx
ahc_bug ahc_callback_t ahc_chip
ahc_dev_softc_t ahc_feature ahc_flag
ahc_msg_type ahc_msgtype ahc_neg_type
ahc_patch_func_t ahc_power_state ahc_queue_alg
ahc_reg_parse_entry_t ahc_search_action ahc_softc
ahc_timer_t ahd_bug ahd_callback_t
ahd_chip ahd_dev_softc_t ahd_feature
ahd_flag ahd_mode ahd_mode_state
ahd_msg_flags ahd_msg_type ahd_msgtype
ahd_neg_type ahd_patch_func_t ahd_power_state
ahd_queue_alg ahd_reg_parse_entry_t ahd_search_action
ahd_softc aic_timer_t alpha_bus_dma_segment
alpha_bus_dma_tag alpha_bus_dmamap alpha_bus_space
alpha_bus_t alpha_eisa_chipset alpha_instruction
alpha_isa_chipset alpha_pci_chipset alpha_pt_entry_t
amdkfd_ioctl_t aml_node amode_t
apr_t ar5k_ar5210_dmasize_t ar5k_ar5211_dmasize_t
ar5k_ar5212_dmasize_t ar5k_attach_t ar5k_capabilities_t
arg arm32_bus_dma_segment arm32_bus_dma_tag
arm32_bus_dmamap arm32_pci_chipset async_cookie_t
atagettrace_t atareq_t ath_hal
ath_task_t atiixp_dma_desc_t atom_exec_context
atom_smu9_syspll0_clock_id atomic64_t atomic_long_t
atomic_t audio_device_t audio_mixer_name_t
audio_params audio_params_t azalia_dma_t
azalia_t batc_t bdlist_entry_t
bge_hostaddr binary_header bios32_entry_info_t
bios32_entry_t bios32_header_t bios_apminfo_t
bios_bootduid_t bios_bootmac_t bios_bootsr_t
bios_consdev_t bios_ddb_t bios_diskinfo_t
bios_efiinfo_t bios_memmap_t bios_oconsdev_t
bios_pciinfo_t bios_romheader_t bios_ucode_t
bits16 bits32 bits64
bits8 bktr_clip bktr_clip_t
bktr_ptr_t bktr_reg_t bktr_softc
blf_ctx blist_t blkcnt_t
blksize_t blmeta_t block_state
bool bool_t boolean_t
bootarg32_t bootarg_t bpf_int32
bpf_u_int32 bregister_t buf_table_t
bus_addr_t bus_dma_segment bus_dma_segment_t
bus_dma_tag bus_dma_tag_t bus_dmamap
bus_dmamap_t bus_size_t bus_space
bus_space_handle_t bus_space_t bus_space_tag_t
byte cac_lock_t caddr_t
cam_status cardbus_chipset_tag_t cardbus_devfunc_t
cardbus_function_t cardbus_function_tag_t cardbus_intr_handle_t
cardslot_softc cardslot_t cast_key
cc_t ccb_flags cdino_t
cell_t cgs_handle_t chacha_ctx
charf ciss_lock_t clock_t
clockid_t cmpci_dmanode cmpci_dmapool_t
cn30xxfpa_addr_t cn_t cnm_state_t
code codec_t codetype
commonNaNT comp_t config
convgroup_t convgroupset_t corb_entry_t
cpu_kcore_hdr_t cpuid_t cpurev_t
critical_section_t ct_data daddr32_t
daddr_t data data_128_t
data_64_t db_breakpoint_t db_expr_t
db_regs db_regs_t db_strategy_t
db_symtab_t db_watchpoint_t dbdma_command
dbdma_command_t dbdma_regmap dbdma_regmap_t
dbdma_t dbl_floating_point dbl_integer
dblwd deflate_state depot_stack_handle_t
des_cblock des_key_schedule detailed_cb
dev_t device df_pstate_t
di_int die_header die_info
digit dint disasm_interface_t
display_arb_params_st display_clocks_and_cfg_st display_data_rq_dlg_params_st
display_data_rq_misc_params_st display_data_rq_regs_st display_data_rq_sizing_params_st
display_dlg_regs_st display_dlg_sys_params_st display_e2e_pipe_params_st
display_output_params_st display_pipe_dest_params_st display_pipe_params_st
display_pipe_source_params_st display_rq_dlg_params_st display_rq_misc_params_st
display_rq_params_st display_rq_regs_st display_rq_sizing_params_st
display_ttu_regs_st dma_addr_t dmaposition_t
dmub_trace_code_t domid_t drm_agp_binding32_t
drm_agp_buffer32_t drm_agp_info32_t drm_agp_mode32_t
drm_buf_desc32_t drm_buf_free32_t drm_buf_info32_t
drm_buf_map32_t drm_buf_pub32_t drm_client32_t
drm_ctx_priv_map32_t drm_ctx_res32_t drm_dma32_t
drm_dma_handle_t drm_handle_t drm_i915_gem_object
drm_ioctl_compat_t drm_ioctl_t drm_local_map
drm_local_map_t drm_map32_t drm_mode_fb_cmd232_t
drm_scatter_gather32_t drm_stats32_t drm_unique32_t
drm_update_draw32_t drm_version32_t drm_wait_vblank32_t
du_int dvd_challenge dvd_key
dwc2_hsotg dwc2_softc_t efi_char
efi_diskinfo efi_diskinfo_t ehci_isoc_bufr_ptr_t
ehci_isoc_trans_t ehci_link_t ehci_physaddr_t
eisa_chipset_tag_t eisa_intr_handle_t eisa_slot_t
em_1000t_rx_status em_10bt_ext_dist_enable em_align_type
em_auto_x_mode em_bus_speed em_bus_type
em_bus_width em_cable_length em_downshift
em_dsp_config em_eeprom_type em_ffe_config
em_gg_cable_length em_igp_cable_length em_mac_type
em_media_type em_mng_mode em_ms_type
em_phy_type em_polarity_reversal em_rev_polarity
em_smart_speed em_speed_duplex_type emuxki_recsrc_t
errata_t evtchn_port_t expression_t
ext_accm fInt f_register_t
fau_op_size_t faultbuf fd_set
fe fe_loose fenv_t
fhandle fhandle_t fixed20_12
fixpt_t flag float128
float32 float64 floatx80
fn_mipi_elem_exec fp_except fp_rnd
fparg fsblkcnt_t fsfilcnt_t
fsid_t gen6_pte_t gen8_pte_t
gfp_t gid_t gmAvfsData_t
gpio_chipset_tag_t gpio_pin_t grant_entry_t
grant_ref_t harvest_info harvest_info_header
harvest_table hdcp head
hppa_bus_dma_segment hppa_bus_dma_tag hppa_bus_dmamap
hppa_bus_space_tag hppa_eisa_chipset hppa_hpa_t
hppa_isa_chipset hppa_pci_chipset_tag hppa_spa_t
i2c_addr_t i2c_bitbang_ops i2c_bitbang_ops_t
i2c_ioctl_exec_t i2c_op_t i2c_tag_t
i386_bus_space_ops i386_pci_tag_u i915_reg_t
id_t idtype_t iecewiseLinearDroopInt_t
ieee80211_countrycode ieee80211_iter_func ieee80211_opmode
ieee80211_regdomain_t ieee80211_state if_set
ifnet igt_create_fn in_addr_t
in_port_t include_type inflate_mode
ino_t instr_t int16
int32 int64 int8
int_fast16_t int_fast32_t int_fast64_t
int_fast8_t int_least16_t int_least32_t
int_least64_t int_least8_t intel_engine_mask_t
intel_sseu_ss_mask_t intel_wakeref_t intf
intmax_t intptr_t intr_establish_t
intrmask_t ioctl_cmd_t ip
ip_discovery_header ip_params_st ip_structure
ip_v3 ipe irq_handler_idx
irq_work irqframe_t irqreturn_t
isa_chipset_tag_t iso_directory_record iso_mnt
iso_node isr_autovec_list_t iwm_match_t
iwx_match_t ixgb_bus_speed ixgb_bus_type
ixgb_bus_width ixgb_fc_type ixgb_mac_type
ixgb_media_type ixgb_phy_type ixgb_xpak_vendor
ixgbe_autoneg_advertised ixgbe_link_speed ixgbe_mc_addr_itr
ixgbe_physical_layer kbd_t kcore_hdr_t
kcore_seg_t key_t keysym_t
ktime_t label_t lacp_port
llSetting_t loff_t luna88k_bus_space_tag
m88k_exception_vector_area mac_intr_handle_t machine_bus_dma_segment
machine_bus_dma_tag machine_bus_dmamap machine_pci_chipset
mc_cc_ev5 mc_cpu_ev6 mc_env_ev6
mc_hdr_avanti mc_hdr_ev5 mc_hdr_ev6
mc_sys_ev6 mc_todregs mc_uc_avanti
mc_uc_ev5 mcbus_softc_t mfInfo_t
mfi_evt_class_t mfi_evt_locale_t mfi_status_t
mifi_t mii_attach_args mii_attach_args_t
mii_bitbang_ops mii_bitbang_ops_t mii_data
mii_data_t mii_softc mii_softc_t
mips_bus_space mips_isa_chipset mips_pci_chipset
mips_space_t mips_xkseg_space_t mixer_ctrl_t
mixer_devinfo_t mixer_item_t mixer_level_t
mod_hdcp mod_hdcp_status mode_t
mp_float_t msg_loop_stat mutex
myx_bus_t n_long n_short
n_time nfds_t nfs_uquad
nfsfh nfsfh_t nfstime2
nfstime3 nfstype nfsuint64
nfsv2_time nfsv3_spec nfsv3_time
nfsv3spec nid_t nlink_t
ntfs_times_t ntfsino_t octeon_add_win_dec_t
octeon_add_win_dma_dec_t off_t ohci_physaddr_t
once_s once_t os
osf owerCalculatorData_t owerGatingMode_e
owerGatingSettings_e ower_Calculator_Data ower_Sharing_t
pa_space_t paddr_t pal_instruction
parser_exec_state patch_info_t patch_t
path_entry_t pci_attach_args pci_channel_state_t
pci_chipset_tag_t pci_class_t pci_ers_result_t
pci_interface_t pci_intr_handle_t pci_intr_line_t
pci_intr_pin_t pci_power_t pci_product_id_t
pci_revision_t pci_subclass_t pci_vendor_id_t
pciintr_icu pciintr_icu_handle_t pciintr_icu_tag_t
pcireg_t pcitag_t pckbc_slot_t
pckbc_tag_t pcmcia_chip_functions pcmcia_chipset_handle_t
pcmcia_chipset_tag_t pcmcia_mem_handle_t pcppi_tag_t
pctrval pd_entry_t pdcsoftc_t
pf_osfp_t pf_refcnt_t pf_tcpopts_t
pgoff_t pgprot_t phm_ppt_v1_clock_voltage_dependency_record
phm_ppt_v1_clock_voltage_dependency_table phm_ppt_v1_gpio_table phm_ppt_v1_mm_clock_voltage_dependency_record
phm_ppt_v1_mm_clock_voltage_dependency_table phm_ppt_v1_pcie_record phm_ppt_v1_pcie_table
phm_ppt_v1_voltage_lookup_record phm_ppt_v1_voltage_lookup_table phys_addr_t
phys_ram_seg_t physaddr physlen
pid_t pm_message_t pmap
pmap_statistics pmap_statistics_t pmap_t
pmon_off_t pmon_size_t pmon_ssize_t
pn_t pollfd_t poly1305_state
pool pool_t powerpc_bus_dma_segment
powerpc_bus_dma_tag powerpc_bus_dmamap pp_atomctrl_clock_dividers
pp_atomctrl_clock_dividers_ai pp_atomctrl_clock_dividers_ci pp_atomctrl_clock_dividers_kong
pp_atomctrl_clock_dividers_rv730 pp_atomctrl_clock_dividers_vi pp_atomctrl_gpio_pin_assignment
pp_atomctrl_internal_ss_info pp_atomctrl_kong_system_info pp_atomctrl_mc_reg_entry
pp_atomctrl_mc_reg_table pp_atomctrl_mc_register_address pp_atomctrl_memory_clock_param
pp_atomctrl_memory_clock_param_ai pp_atomctrl_memory_clock_range_table pp_atomctrl_memory_info
pp_atomctrl_s_mpll_fb_divider pp_atomctrl_spread_spectrum_mode pp_atomctrl_tcipll_fb_divider
pp_atomctrl_voltage_table pp_atomctrl_voltage_table_entry ppc64_pci_chipset
ppc_bus_space ppc_isa_bus ppc_pci_chipset
prom_return_t psize_t pt_entry_t
pte_t ptr_table ptrace_event_t
ptrace_state_t ptrdiff_t pv_addr_t
pv_entry pv_entry_t pxe_t
pxenv_t pz_device_t q_mmap
qp_entry qp_set qp_table
qshift_t quad_floating_point quad_integer
quad_t quadwd rbus_tag_t
rbustag rcu_head read_block_fn
refcnt refcount_t reg
register_t resource_size_t rijndael_ctx
rirb_entry_t rlim_t role_t
rwlock s s16
s32 s64 s8
s_float sa_family_t salloc_t
sbits16 sbits32 sbits64
sbits8 scaler_ratio_depth_st scaler_taps_st
scb_flag sclkFcwRange_t scope_t
scope_type scr_table_t scsireq_t
sdmmc_bitfield512_t sdmmc_chip_functions sdmmc_chipset_handle_t
sdmmc_chipset_tag_t sdmmc_response sdt_entry_t
sec seeprom_chip_t segsz_t
sense_addr_t seqcount_mutex_t seqcount_t
seqlock_t session sgl_floating_point
sgl_integer shmatt_t si_int
sig_atomic_t sigcontext siginfo_t
sigset_t size_t soc_bounding_box_st
socklen_t sparc_bus_dma_segment sparc_bus_dma_tag
sparc_bus_dmamap sparc_bus_space_tag sparc_pci_chipset
speed_t spi_tag_t spinlock_t
spmi_tag_t sr_t ssize_t
stack_t static_tree_desc static_tree_desc_s
sti_blkmvflags_t sti_blkmvin_t sti_blkmvout_t
sti_cfg_t sti_dmacflags_t sti_dmacin_t
sti_dmacout_t sti_ecfg_t sti_eexhdlin_t
sti_eexhdlout_t sti_einitin_t sti_einqconfout_t
sti_exhdlflags_t sti_exhdlin_t sti_exhdlint_t
sti_exhdlout_t sti_flowcflags_t sti_flowcin_t
sti_flowcout_t sti_initflags_t sti_initin_t
sti_initout_t sti_inqconfflags_t sti_inqconfin_t
sti_inqconfout_t sti_mgmtflags_t sti_mgmtin_t
sti_mgmtout_t sti_mon_t sti_pmgrflags_t
sti_pmgrin_t sti_pmgrout_t sti_scmentflags_t
sti_scmentin_t sti_scmentout_t sti_testflags_t
sti_testin_t sti_testout_t sti_unpmvflags_t
sti_unpmvin_t sti_unpmvout_t sti_utilflags_t
sti_utilin_t sti_utilout_t sti_utimingflags_t
sti_utimingin_t sti_utimingout_t stoeplitz_key
stp4020_regs_t stp4020_socket_csr_t stp4020_window_ctl_t
stream_t su_int sun4u_tte
suseconds_t swblk_t sy_call_t
symbol_node_t symbol_ref_t symbol_t
symlist_t symtype t_PXENV_GET_CACHED_INFO
t_PXENV_START_BASE t_PXENV_START_UNDI t_PXENV_STOP_BASE
t_PXENV_STOP_UNDI t_PXENV_TFTP_CLOSE t_PXENV_TFTP_GET_FSIZE
t_PXENV_TFTP_OPEN t_PXENV_TFTP_READ t_PXENV_TFTP_READ_FILE
t_PXENV_UDP_CLOSE t_PXENV_UDP_OPEN t_PXENV_UDP_READ
t_PXENV_UDP_WRITE t_PXENV_UNDI_CLEANUP t_PXENV_UNDI_CLEAR_STATISTICS
t_PXENV_UNDI_CLOSE t_PXENV_UNDI_FORCE_INTERRUPT t_PXENV_UNDI_GET_INFORMATION
t_PXENV_UNDI_GET_MCAST_ADDR t_PXENV_UNDI_GET_NDIS_INFO t_PXENV_UNDI_GET_NIC_TYPE
t_PXENV_UNDI_GET_STATISTICS t_PXENV_UNDI_INITIALIZE t_PXENV_UNDI_INITIATE_DIAGS
t_PXENV_UNDI_ISR t_PXENV_UNDI_MCAST_ADDRESS t_PXENV_UNDI_OPEN
t_PXENV_UNDI_RESET t_PXENV_UNDI_SET_MCAST_ADDR t_PXENV_UNDI_SET_PACKET_FILTER
t_PXENV_UNDI_SET_STATION_ADDR t_PXENV_UNDI_SHUTDOWN t_PXENV_UNDI_STARTUP
t_PXENV_UNDI_TBD t_PXENV_UNDI_TRANSMIT t_PXENV_UNLOAD_STACK
t_float ta_dtm_dio_output_type table
table_info tc_addr_t tc_offset_t
tc_padchar_t tcflag_t tcp_seq
tga_reg_t ti_hostaddr ti_i2cop_t
ti_int time_t timecounter_get_t
timecounter_pps_t timeout timer_t
tmpfs_dirent_t tmpfs_fid_t tmpfs_mount_t
tmpfs_node_t todr_chip_handle todr_chip_handle_t
tomCtrl_EDCLeakgeTable tomCtrl_HiLoLeakageOffsetTable tone_t
tpr_t tr trapframe
trapframe_t tree_desc tsp_config
tu_int tulip_board_t tulip_boardsw_t
tulip_chipid_t tulip_cycle_t tulip_desc_t
tulip_dot3_stats_t tulip_link_status_t tulip_media_info_t
tulip_media_t tulip_mediapoll_event_t tulip_phy_attr_t
tulip_phy_mode_t tulip_phy_modedata_t tulip_probe_state_t
tulip_regfile_t tulip_ringinfo_t tulip_softc_t
tulip_srom_adapter_info_t tulip_srom_connection_t tulip_srom_header_t
tulip_srom_media_t twe_lock_t twe_queue_head
twords u16 u16b
u32 u32b u64
u8 uByte uDWord
uInt uIntf uLong
uLongf uWord u_intptr_t
u_swblk_t uch uchf
ucontext_t udfino_t ufsino_t
uhci_physaddr_t uhci_soft_td_qh_t uid_t
uint uint16 uint32
uint64 uint8 uint_fast16_t
uint_fast32_t uint_fast64_t uint_fast8_t
uint_fixed_16_16_t uint_least16_t uint_least32_t
uint_least64_t uint_least8_t uintmax_t
ulg ulong umass_cbi_cbl_t
umass_cbi_sbl_t umass_softc unchar
unicode_t url_rxhdr_t usb_config_descriptor
usb_config_descriptor_t usb_descriptor usb_descriptor_t
usb_device_descriptor usb_device_descriptor_t usb_device_qualifier
usb_device_qualifier_t usb_device_request usb_device_request_t
usb_endpoint_descriptor usb_endpoint_descriptor_t usb_endpoint_ss_comp_descriptor
usb_endpoint_ss_comp_descriptor_t usb_hub_descriptor usb_hub_descriptor_t
usb_hub_ss_descriptor usb_hub_ss_descriptor_t usb_hub_status
usb_hub_status_t usb_interface_assoc_descriptor usb_interface_assoc_descriptor_t
usb_interface_descriptor usb_interface_descriptor_t usb_otg_descriptor
usb_otg_descriptor_t usb_port_status usb_port_status_t
usb_status usb_status_t usb_string_descriptor
usb_string_descriptor_t usbd_status useconds_t
ush ushf ushort
utwords uuid uuid_t
uvm_coredump_setup_cb uvm_coredump_walk_cb ux32Info
ux64Info v4l2_std_id va_list
vaddr_t vcn_clk_t vfsDcBtcParams_t
vfsDebugTableExternal_t vfsDebugTable_t vfsDebugTable_t_NV10
vfsDebugTable_t_NV14 vfsFuseOverrideExternal_t vfsFuseOverride_t
vfsTable_t vifbitmap_t vifi_t
vm_fault_t vm_inherit_t vm_map
vm_map_entry vm_map_entry_t vm_map_t
vm_page vm_page_t vm_prot_t
voff_t voidp voidpc
voidpf volgroup_t voltage_scaling_st
vsize_t vt100_handler vt_mode
vtmode_t wa_bb_func_t wait_queue_entry
wait_queue_entry_t wait_queue_head wait_queue_head_t
wchar wcreg_t wi_usb_usbin
widget_t word work_struct
wpreg_t wrConfig_e x86_bus_space_ops
xen_commandline_t xen_intr_handle_t xen_pfn_t
xen_ulong_t yds_dstype_t z_crc_t
z_size_t z_word_t

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