The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference

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[ typedefs ] [ structs ] [ enums ] [ unions ]

1941 definition(s) of union type

GmdgD3 VIA_ACE_CW _ia64_fpreg
_sata_sas_address aac_AifJobClient aac_statrequest
aapa acpi_battery_ioctl_arg acpi_parse_object
active_open_entry ahc_bus_softc allblk
amr_ccb aopen_entry asr_ccb
at91dci_hub_temp atmegadci_hub_temp auditon_udata
authctx avr32dci_hub_temp bgn
blkif_back_rings bootsector ccb
cd_mode_data_6_10 cd_pages cdu_context
cfi_taskinfo ciss_device_address ciss_statrequest
cma_ip_addr coda_downcalls ctl_be_block_bedata
ctl_ha_msg ctl_io ctl_lunreq_data
ctl_modepage_info ctl_priv ctl_softcs
cvmx_agl_gmx_bad_reg cvmx_agl_gmx_bist cvmx_agl_gmx_drv_ctl
cvmx_agl_gmx_inf_mode cvmx_agl_gmx_prtx_cfg cvmx_agl_gmx_rx_bp_dropx
cvmx_agl_gmx_rx_bp_offx cvmx_agl_gmx_rx_bp_onx cvmx_agl_gmx_rx_prt_info
cvmx_agl_gmx_rx_tx_status cvmx_agl_gmx_rxx_adr_cam0 cvmx_agl_gmx_rxx_adr_cam1
cvmx_agl_gmx_rxx_adr_cam2 cvmx_agl_gmx_rxx_adr_cam3 cvmx_agl_gmx_rxx_adr_cam4
cvmx_agl_gmx_rxx_adr_cam5 cvmx_agl_gmx_rxx_adr_cam_en cvmx_agl_gmx_rxx_adr_ctl
cvmx_agl_gmx_rxx_decision cvmx_agl_gmx_rxx_frm_chk cvmx_agl_gmx_rxx_frm_ctl
cvmx_agl_gmx_rxx_frm_max cvmx_agl_gmx_rxx_frm_min cvmx_agl_gmx_rxx_ifg
cvmx_agl_gmx_rxx_int_en cvmx_agl_gmx_rxx_int_reg cvmx_agl_gmx_rxx_jabber
cvmx_agl_gmx_rxx_pause_drop_time cvmx_agl_gmx_rxx_rx_inbnd cvmx_agl_gmx_rxx_stats_ctl
cvmx_agl_gmx_rxx_stats_octs cvmx_agl_gmx_rxx_stats_octs_ctl cvmx_agl_gmx_rxx_stats_octs_dmac
cvmx_agl_gmx_rxx_stats_octs_drp cvmx_agl_gmx_rxx_stats_pkts cvmx_agl_gmx_rxx_stats_pkts_bad
cvmx_agl_gmx_rxx_stats_pkts_ctl cvmx_agl_gmx_rxx_stats_pkts_dmac cvmx_agl_gmx_rxx_stats_pkts_drp
cvmx_agl_gmx_rxx_udd_skp cvmx_agl_gmx_smacx cvmx_agl_gmx_stat_bp
cvmx_agl_gmx_tx_bp cvmx_agl_gmx_tx_col_attempt cvmx_agl_gmx_tx_ifg
cvmx_agl_gmx_tx_int_en cvmx_agl_gmx_tx_int_reg cvmx_agl_gmx_tx_jam
cvmx_agl_gmx_tx_lfsr cvmx_agl_gmx_tx_ovr_bp cvmx_agl_gmx_tx_pause_pkt_dmac
cvmx_agl_gmx_tx_pause_pkt_type cvmx_agl_gmx_txx_append cvmx_agl_gmx_txx_clk
cvmx_agl_gmx_txx_ctl cvmx_agl_gmx_txx_min_pkt cvmx_agl_gmx_txx_pause_pkt_interval
cvmx_agl_gmx_txx_pause_pkt_time cvmx_agl_gmx_txx_pause_togo cvmx_agl_gmx_txx_pause_zero
cvmx_agl_gmx_txx_soft_pause cvmx_agl_gmx_txx_stat0 cvmx_agl_gmx_txx_stat1
cvmx_agl_gmx_txx_stat2 cvmx_agl_gmx_txx_stat3 cvmx_agl_gmx_txx_stat4
cvmx_agl_gmx_txx_stat5 cvmx_agl_gmx_txx_stat6 cvmx_agl_gmx_txx_stat7
cvmx_agl_gmx_txx_stat8 cvmx_agl_gmx_txx_stat9 cvmx_agl_gmx_txx_stats_ctl
cvmx_agl_gmx_txx_thresh cvmx_agl_prtx_ctl cvmx_asx0_dbg_data_drv
cvmx_asx0_dbg_data_enable cvmx_asxx_gmii_rx_clk_set cvmx_asxx_gmii_rx_dat_set
cvmx_asxx_int_en cvmx_asxx_int_reg cvmx_asxx_mii_rx_dat_set
cvmx_asxx_prt_loop cvmx_asxx_rld_bypass cvmx_asxx_rld_bypass_setting
cvmx_asxx_rld_comp cvmx_asxx_rld_data_drv cvmx_asxx_rld_fcram_mode
cvmx_asxx_rld_nctl_strong cvmx_asxx_rld_nctl_weak cvmx_asxx_rld_pctl_strong
cvmx_asxx_rld_pctl_weak cvmx_asxx_rld_setting cvmx_asxx_rx_clk_setx
cvmx_asxx_rx_prt_en cvmx_asxx_rx_wol cvmx_asxx_rx_wol_msk
cvmx_asxx_rx_wol_powok cvmx_asxx_rx_wol_sig cvmx_asxx_tx_clk_setx
cvmx_asxx_tx_comp_byp cvmx_asxx_tx_hi_waterx cvmx_asxx_tx_prt_en
cvmx_ciu_bist cvmx_ciu_block_int cvmx_ciu_dint
cvmx_ciu_fuse cvmx_ciu_gstop cvmx_ciu_int33_sum0
cvmx_ciu_int_dbg_sel cvmx_ciu_int_sum1 cvmx_ciu_intx_en0
cvmx_ciu_intx_en0_w1c cvmx_ciu_intx_en0_w1s cvmx_ciu_intx_en1
cvmx_ciu_intx_en1_w1c cvmx_ciu_intx_en1_w1s cvmx_ciu_intx_en4_0
cvmx_ciu_intx_en4_0_w1c cvmx_ciu_intx_en4_0_w1s cvmx_ciu_intx_en4_1
cvmx_ciu_intx_en4_1_w1c cvmx_ciu_intx_en4_1_w1s cvmx_ciu_intx_sum0
cvmx_ciu_intx_sum4 cvmx_ciu_mbox_clrx cvmx_ciu_mbox_setx
cvmx_ciu_nmi cvmx_ciu_pci_inta cvmx_ciu_pp_dbg
cvmx_ciu_pp_pokex cvmx_ciu_pp_rst cvmx_ciu_qlm0
cvmx_ciu_qlm1 cvmx_ciu_qlm2 cvmx_ciu_qlm_dcok
cvmx_ciu_qlm_jtgc cvmx_ciu_qlm_jtgd cvmx_ciu_soft_bist
cvmx_ciu_soft_prst cvmx_ciu_soft_prst1 cvmx_ciu_soft_rst
cvmx_ciu_timx cvmx_ciu_wdogx cvmx_dbg_data
cvmx_dfa_bist0 cvmx_dfa_bist1 cvmx_dfa_bst0
cvmx_dfa_bst1 cvmx_dfa_cfg cvmx_dfa_config
cvmx_dfa_control cvmx_dfa_dbell cvmx_dfa_ddr2_addr
cvmx_dfa_ddr2_bus cvmx_dfa_ddr2_cfg cvmx_dfa_ddr2_comp
cvmx_dfa_ddr2_emrs cvmx_dfa_ddr2_fcnt cvmx_dfa_ddr2_mrs
cvmx_dfa_ddr2_opt cvmx_dfa_ddr2_pll cvmx_dfa_ddr2_tmg
cvmx_dfa_debug0 cvmx_dfa_debug1 cvmx_dfa_debug2
cvmx_dfa_debug3 cvmx_dfa_difctl cvmx_dfa_difrdptr
cvmx_dfa_dtcfadr cvmx_dfa_eclkcfg cvmx_dfa_err
cvmx_dfa_error cvmx_dfa_intmsk cvmx_dfa_memcfg0
cvmx_dfa_memcfg1 cvmx_dfa_memcfg2 cvmx_dfa_memfadr
cvmx_dfa_memfcr cvmx_dfa_memhidat cvmx_dfa_memrld
cvmx_dfa_ncbctl cvmx_dfa_pfc0_cnt cvmx_dfa_pfc0_ctl
cvmx_dfa_pfc1_cnt cvmx_dfa_pfc1_ctl cvmx_dfa_pfc2_cnt
cvmx_dfa_pfc2_ctl cvmx_dfa_pfc3_cnt cvmx_dfa_pfc3_ctl
cvmx_dfa_pfc_gctl cvmx_dfa_rodt_comp_ctl cvmx_dfa_sbd_dbg0
cvmx_dfa_sbd_dbg1 cvmx_dfa_sbd_dbg2 cvmx_dfa_sbd_dbg3
cvmx_dfm_char_ctl cvmx_dfm_char_mask0 cvmx_dfm_char_mask2
cvmx_dfm_char_mask4 cvmx_dfm_comp_ctl2 cvmx_dfm_config
cvmx_dfm_control cvmx_dfm_dll_ctl2 cvmx_dfm_dll_ctl3
cvmx_dfm_fclk_cnt cvmx_dfm_fnt_bist cvmx_dfm_fnt_ctl
cvmx_dfm_fnt_iena cvmx_dfm_fnt_sclk cvmx_dfm_fnt_stat
cvmx_dfm_ifb_cnt cvmx_dfm_modereg_params0 cvmx_dfm_modereg_params1
cvmx_dfm_ops_cnt cvmx_dfm_phy_ctl cvmx_dfm_reset_ctl
cvmx_dfm_rlevel_ctl cvmx_dfm_rlevel_dbg cvmx_dfm_rlevel_rankx
cvmx_dfm_rodt_mask cvmx_dfm_slot_ctl0 cvmx_dfm_slot_ctl1
cvmx_dfm_timing_params0 cvmx_dfm_timing_params1 cvmx_dfm_wlevel_ctl
cvmx_dfm_wlevel_dbg cvmx_dfm_wlevel_rankx cvmx_dfm_wodt_mask
cvmx_dpi_bist_status cvmx_dpi_ctl cvmx_dpi_dma_control
cvmx_dpi_dma_engx_en cvmx_dpi_dmax_counts cvmx_dpi_dmax_dbell
cvmx_dpi_dmax_ibuff_saddr cvmx_dpi_dmax_naddr cvmx_dpi_dmax_reqbnk0
cvmx_dpi_dmax_reqbnk1 cvmx_dpi_engx_buf cvmx_dpi_info_reg
cvmx_dpi_int_en cvmx_dpi_int_reg cvmx_dpi_pint_info
cvmx_dpi_pkt_err_rsp cvmx_dpi_req_err_rsp cvmx_dpi_req_err_rsp_en
cvmx_dpi_req_err_rst cvmx_dpi_req_err_rst_en cvmx_dpi_req_gbl_en
cvmx_dpi_sli_prtx_cfg cvmx_dpi_sli_prtx_err cvmx_dpi_sli_prtx_err_info
cvmx_fpa_bist_status cvmx_fpa_ctl_status cvmx_fpa_fpf0_marks
cvmx_fpa_fpf0_size cvmx_fpa_fpfx_marks cvmx_fpa_fpfx_size
cvmx_fpa_int_enb cvmx_fpa_int_sum cvmx_fpa_packet_threshold
cvmx_fpa_poolx_threshold cvmx_fpa_que_act cvmx_fpa_que_exp
cvmx_fpa_quex_available cvmx_fpa_quex_page_index cvmx_fpa_wart_ctl
cvmx_fpa_wart_status cvmx_fpa_wqe_threshold cvmx_gmxx_bad_reg
cvmx_gmxx_bist cvmx_gmxx_clk_en cvmx_gmxx_hg2_control
cvmx_gmxx_inf_mode cvmx_gmxx_nxa_adr cvmx_gmxx_prtx_cbfc_ctl
cvmx_gmxx_prtx_cfg cvmx_gmxx_rx_bp_dropx cvmx_gmxx_rx_bp_offx
cvmx_gmxx_rx_bp_onx cvmx_gmxx_rx_hg2_status cvmx_gmxx_rx_pass_en
cvmx_gmxx_rx_pass_mapx cvmx_gmxx_rx_prt_info cvmx_gmxx_rx_prts
cvmx_gmxx_rx_tx_status cvmx_gmxx_rx_xaui_bad_col cvmx_gmxx_rx_xaui_ctl
cvmx_gmxx_rxx_adr_cam0 cvmx_gmxx_rxx_adr_cam1 cvmx_gmxx_rxx_adr_cam2
cvmx_gmxx_rxx_adr_cam3 cvmx_gmxx_rxx_adr_cam4 cvmx_gmxx_rxx_adr_cam5
cvmx_gmxx_rxx_adr_cam_en cvmx_gmxx_rxx_adr_ctl cvmx_gmxx_rxx_decision
cvmx_gmxx_rxx_frm_chk cvmx_gmxx_rxx_frm_ctl cvmx_gmxx_rxx_frm_max
cvmx_gmxx_rxx_frm_min cvmx_gmxx_rxx_ifg cvmx_gmxx_rxx_int_en
cvmx_gmxx_rxx_int_reg cvmx_gmxx_rxx_jabber cvmx_gmxx_rxx_pause_drop_time
cvmx_gmxx_rxx_rx_inbnd cvmx_gmxx_rxx_stats_ctl cvmx_gmxx_rxx_stats_octs
cvmx_gmxx_rxx_stats_octs_ctl cvmx_gmxx_rxx_stats_octs_dmac cvmx_gmxx_rxx_stats_octs_drp
cvmx_gmxx_rxx_stats_pkts cvmx_gmxx_rxx_stats_pkts_bad cvmx_gmxx_rxx_stats_pkts_ctl
cvmx_gmxx_rxx_stats_pkts_dmac cvmx_gmxx_rxx_stats_pkts_drp cvmx_gmxx_rxx_udd_skp
cvmx_gmxx_smacx cvmx_gmxx_soft_bist cvmx_gmxx_stat_bp
cvmx_gmxx_tx_bp cvmx_gmxx_tx_clk_mskx cvmx_gmxx_tx_col_attempt
cvmx_gmxx_tx_corrupt cvmx_gmxx_tx_hg2_reg1 cvmx_gmxx_tx_hg2_reg2
cvmx_gmxx_tx_ifg cvmx_gmxx_tx_int_en cvmx_gmxx_tx_int_reg
cvmx_gmxx_tx_jam cvmx_gmxx_tx_lfsr cvmx_gmxx_tx_ovr_bp
cvmx_gmxx_tx_pause_pkt_dmac cvmx_gmxx_tx_pause_pkt_type cvmx_gmxx_tx_prts
cvmx_gmxx_tx_spi_ctl cvmx_gmxx_tx_spi_drain cvmx_gmxx_tx_spi_max
cvmx_gmxx_tx_spi_roundx cvmx_gmxx_tx_spi_thresh cvmx_gmxx_tx_xaui_ctl
cvmx_gmxx_txx_append cvmx_gmxx_txx_burst cvmx_gmxx_txx_cbfc_xoff
cvmx_gmxx_txx_cbfc_xon cvmx_gmxx_txx_clk cvmx_gmxx_txx_ctl
cvmx_gmxx_txx_min_pkt cvmx_gmxx_txx_pause_pkt_interval cvmx_gmxx_txx_pause_pkt_time
cvmx_gmxx_txx_pause_togo cvmx_gmxx_txx_pause_zero cvmx_gmxx_txx_sgmii_ctl
cvmx_gmxx_txx_slot cvmx_gmxx_txx_soft_pause cvmx_gmxx_txx_stat0
cvmx_gmxx_txx_stat1 cvmx_gmxx_txx_stat2 cvmx_gmxx_txx_stat3
cvmx_gmxx_txx_stat4 cvmx_gmxx_txx_stat5 cvmx_gmxx_txx_stat6
cvmx_gmxx_txx_stat7 cvmx_gmxx_txx_stat8 cvmx_gmxx_txx_stat9
cvmx_gmxx_txx_stats_ctl cvmx_gmxx_txx_thresh cvmx_gmxx_xaui_ext_loopback
cvmx_gpio_bit_cfgx cvmx_gpio_boot_ena cvmx_gpio_clk_genx
cvmx_gpio_clk_qlmx cvmx_gpio_dbg_ena cvmx_gpio_int_clr
cvmx_gpio_rx_dat cvmx_gpio_tx_clr cvmx_gpio_tx_set
cvmx_gpio_xbit_cfgx cvmx_iob_bist_status cvmx_iob_ctl_status
cvmx_iob_dwb_pri_cnt cvmx_iob_fau_timeout cvmx_iob_i2c_pri_cnt
cvmx_iob_inb_control_match cvmx_iob_inb_control_match_enb cvmx_iob_inb_data_match
cvmx_iob_inb_data_match_enb cvmx_iob_int_enb cvmx_iob_int_sum
cvmx_iob_n2c_l2c_pri_cnt cvmx_iob_n2c_rsp_pri_cnt cvmx_iob_outb_com_pri_cnt
cvmx_iob_outb_control_match cvmx_iob_outb_control_match_enb cvmx_iob_outb_data_match
cvmx_iob_outb_data_match_enb cvmx_iob_outb_fpa_pri_cnt cvmx_iob_outb_req_pri_cnt
cvmx_iob_p2c_req_pri_cnt cvmx_iob_pkt_err cvmx_iob_to_cmb_credits
cvmx_ipd_1st_mbuff_skip cvmx_ipd_1st_next_ptr_back cvmx_ipd_2nd_next_ptr_back
cvmx_ipd_bist_status cvmx_ipd_bp_prt_red_end cvmx_ipd_clk_count
cvmx_ipd_ctl_status cvmx_ipd_int_enb cvmx_ipd_int_sum
cvmx_ipd_not_1st_mbuff_skip cvmx_ipd_packet_mbuff_size cvmx_ipd_pkt_ptr_valid
cvmx_ipd_port_bp_counters2_pairx cvmx_ipd_port_bp_counters3_pairx cvmx_ipd_port_bp_counters_pairx
cvmx_ipd_port_qos_int_enbx cvmx_ipd_port_qos_intx cvmx_ipd_port_qos_x_cnt
cvmx_ipd_portx_bp_page_cnt cvmx_ipd_portx_bp_page_cnt2 cvmx_ipd_portx_bp_page_cnt3
cvmx_ipd_prc_hold_ptr_fifo_ctl cvmx_ipd_prc_port_ptr_fifo_ctl cvmx_ipd_ptr_count
cvmx_ipd_pwp_ptr_fifo_ctl cvmx_ipd_qosx_red_marks cvmx_ipd_que0_free_page_cnt
cvmx_ipd_red_port_enable cvmx_ipd_red_port_enable2 cvmx_ipd_red_quex_param
cvmx_ipd_sub_port_bp_page_cnt cvmx_ipd_sub_port_fcs cvmx_ipd_sub_port_qos_cnt
cvmx_ipd_wqe_fpa_queue cvmx_ipd_wqe_ptr_valid cvmx_key_bist_reg
cvmx_key_ctl_status cvmx_key_int_enb cvmx_key_int_sum
cvmx_l2c_big_ctl cvmx_l2c_bst cvmx_l2c_bst0
cvmx_l2c_bst1 cvmx_l2c_bst2 cvmx_l2c_bst_memx
cvmx_l2c_bst_tdtx cvmx_l2c_bst_ttgx cvmx_l2c_cfg
cvmx_l2c_cop0_mapx cvmx_l2c_ctl cvmx_l2c_dbg
cvmx_l2c_dut cvmx_l2c_dut_mapx cvmx_l2c_err_tdtx
cvmx_l2c_err_ttgx cvmx_l2c_err_vbfx cvmx_l2c_err_xmc
cvmx_l2c_grpwrr0 cvmx_l2c_grpwrr1 cvmx_l2c_int_en
cvmx_l2c_int_ena cvmx_l2c_int_reg cvmx_l2c_int_stat
cvmx_l2c_iocx_pfc cvmx_l2c_iorx_pfc cvmx_l2c_lckbase
cvmx_l2c_lckoff cvmx_l2c_lfb0 cvmx_l2c_lfb1
cvmx_l2c_lfb2 cvmx_l2c_lfb3 cvmx_l2c_oob
cvmx_l2c_oob1 cvmx_l2c_oob2 cvmx_l2c_oob3
cvmx_l2c_pfctl cvmx_l2c_pfcx cvmx_l2c_ppgrp
cvmx_l2c_qos_iobx cvmx_l2c_qos_ppx cvmx_l2c_qos_wgt
cvmx_l2c_rscx_pfc cvmx_l2c_rsdx_pfc cvmx_l2c_spar0
cvmx_l2c_spar1 cvmx_l2c_spar2 cvmx_l2c_spar3
cvmx_l2c_spar4 cvmx_l2c_tadx_ecc0 cvmx_l2c_tadx_ecc1
cvmx_l2c_tadx_ien cvmx_l2c_tadx_int cvmx_l2c_tadx_pfc0
cvmx_l2c_tadx_pfc1 cvmx_l2c_tadx_pfc2 cvmx_l2c_tadx_pfc3
cvmx_l2c_tadx_prf cvmx_l2c_tadx_tag cvmx_l2c_ver_id
cvmx_l2c_ver_iob cvmx_l2c_ver_msc cvmx_l2c_ver_pp
cvmx_l2c_virtid_iobx cvmx_l2c_virtid_ppx cvmx_l2c_vrt_ctl
cvmx_l2c_vrt_memx cvmx_l2c_wpar_iobx cvmx_l2c_wpar_ppx
cvmx_l2c_xmc_cmd cvmx_l2c_xmcx_pfc cvmx_l2c_xmdx_pfc
cvmx_l2d_bst0 cvmx_l2d_bst1 cvmx_l2d_bst2
cvmx_l2d_bst3 cvmx_l2d_err cvmx_l2d_fadr
cvmx_l2d_fsyn0 cvmx_l2d_fsyn1 cvmx_l2d_fus0
cvmx_l2d_fus1 cvmx_l2d_fus2 cvmx_l2d_fus3
cvmx_l2t_err cvmx_led_blink cvmx_led_clk_phase
cvmx_led_cylon cvmx_led_dbg cvmx_led_en
cvmx_led_polarity cvmx_led_prt cvmx_led_prt_fmt
cvmx_led_prt_statusx cvmx_led_udd_cntx cvmx_led_udd_dat_clrx
cvmx_led_udd_dat_setx cvmx_led_udd_datx cvmx_lmcx_bist_ctl
cvmx_lmcx_bist_result cvmx_lmcx_char_ctl cvmx_lmcx_char_mask0
cvmx_lmcx_char_mask1 cvmx_lmcx_char_mask2 cvmx_lmcx_char_mask3
cvmx_lmcx_char_mask4 cvmx_lmcx_comp_ctl cvmx_lmcx_comp_ctl2
cvmx_lmcx_config cvmx_lmcx_control cvmx_lmcx_ctl
cvmx_lmcx_ctl1 cvmx_lmcx_dclk_cnt cvmx_lmcx_dclk_cnt_hi
cvmx_lmcx_dclk_cnt_lo cvmx_lmcx_dclk_ctl cvmx_lmcx_ddr2_ctl
cvmx_lmcx_ddr_pll_ctl cvmx_lmcx_delay_cfg cvmx_lmcx_dimm_ctl
cvmx_lmcx_dimmx_params cvmx_lmcx_dll_ctl cvmx_lmcx_dll_ctl2
cvmx_lmcx_dll_ctl3 cvmx_lmcx_dual_memcfg cvmx_lmcx_ecc_synd
cvmx_lmcx_fadr cvmx_lmcx_ifb_cnt cvmx_lmcx_ifb_cnt_hi
cvmx_lmcx_ifb_cnt_lo cvmx_lmcx_int cvmx_lmcx_int_en
cvmx_lmcx_mem_cfg0 cvmx_lmcx_mem_cfg1 cvmx_lmcx_modereg_params0
cvmx_lmcx_modereg_params1 cvmx_lmcx_nxm cvmx_lmcx_ops_cnt
cvmx_lmcx_ops_cnt_hi cvmx_lmcx_ops_cnt_lo cvmx_lmcx_phy_ctl
cvmx_lmcx_pll_bwctl cvmx_lmcx_pll_ctl cvmx_lmcx_pll_status
cvmx_lmcx_read_level_ctl cvmx_lmcx_read_level_dbg cvmx_lmcx_read_level_rankx
cvmx_lmcx_reset_ctl cvmx_lmcx_rlevel_ctl cvmx_lmcx_rlevel_dbg
cvmx_lmcx_rlevel_rankx cvmx_lmcx_rodt_comp_ctl cvmx_lmcx_rodt_ctl
cvmx_lmcx_rodt_mask cvmx_lmcx_slot_ctl0 cvmx_lmcx_slot_ctl1
cvmx_lmcx_slot_ctl2 cvmx_lmcx_timing_params0 cvmx_lmcx_timing_params1
cvmx_lmcx_tro_ctl cvmx_lmcx_tro_stat cvmx_lmcx_wlevel_ctl
cvmx_lmcx_wlevel_dbg cvmx_lmcx_wlevel_rankx cvmx_lmcx_wodt_ctl0
cvmx_lmcx_wodt_ctl1 cvmx_lmcx_wodt_mask cvmx_mio_boot_bist_stat
cvmx_mio_boot_comp cvmx_mio_boot_dma_cfgx cvmx_mio_boot_dma_int_enx
cvmx_mio_boot_dma_intx cvmx_mio_boot_dma_timx cvmx_mio_boot_err
cvmx_mio_boot_int cvmx_mio_boot_loc_adr cvmx_mio_boot_loc_cfgx
cvmx_mio_boot_loc_dat cvmx_mio_boot_pin_defs cvmx_mio_boot_reg_cfgx
cvmx_mio_boot_reg_timx cvmx_mio_boot_thr cvmx_mio_fus_bnk_datx
cvmx_mio_fus_dat0 cvmx_mio_fus_dat1 cvmx_mio_fus_dat2
cvmx_mio_fus_dat3 cvmx_mio_fus_ema cvmx_mio_fus_pdf
cvmx_mio_fus_pll cvmx_mio_fus_prog cvmx_mio_fus_prog_times
cvmx_mio_fus_rcmd cvmx_mio_fus_read_times cvmx_mio_fus_repair_res0
cvmx_mio_fus_repair_res1 cvmx_mio_fus_repair_res2 cvmx_mio_fus_spr_repair_res
cvmx_mio_fus_spr_repair_sum cvmx_mio_fus_unlock cvmx_mio_fus_wadr
cvmx_mio_gpio_comp cvmx_mio_ndf_dma_cfg cvmx_mio_ndf_dma_int
cvmx_mio_ndf_dma_int_en cvmx_mio_pll_ctl cvmx_mio_pll_setting
cvmx_mio_ptp_clock_cfg cvmx_mio_ptp_clock_comp cvmx_mio_ptp_clock_hi
cvmx_mio_ptp_clock_lo cvmx_mio_ptp_evt_cnt cvmx_mio_ptp_timestamp
cvmx_mio_rst_boot cvmx_mio_rst_cfg cvmx_mio_rst_ctlx
cvmx_mio_rst_delay cvmx_mio_rst_int cvmx_mio_rst_int_en
cvmx_mio_twsx_int cvmx_mio_twsx_sw_twsi cvmx_mio_twsx_sw_twsi_ext
cvmx_mio_twsx_twsi_sw cvmx_mio_uart2_dlh cvmx_mio_uart2_dll
cvmx_mio_uart2_far cvmx_mio_uart2_fcr cvmx_mio_uart2_htx
cvmx_mio_uart2_ier cvmx_mio_uart2_iir cvmx_mio_uart2_lcr
cvmx_mio_uart2_lsr cvmx_mio_uart2_mcr cvmx_mio_uart2_msr
cvmx_mio_uart2_rbr cvmx_mio_uart2_rfl cvmx_mio_uart2_rfw
cvmx_mio_uart2_sbcr cvmx_mio_uart2_scr cvmx_mio_uart2_sfe
cvmx_mio_uart2_srr cvmx_mio_uart2_srt cvmx_mio_uart2_srts
cvmx_mio_uart2_stt cvmx_mio_uart2_tfl cvmx_mio_uart2_tfr
cvmx_mio_uart2_thr cvmx_mio_uart2_usr cvmx_mio_uartx_dlh
cvmx_mio_uartx_dll cvmx_mio_uartx_far cvmx_mio_uartx_fcr
cvmx_mio_uartx_htx cvmx_mio_uartx_ier cvmx_mio_uartx_iir
cvmx_mio_uartx_lcr cvmx_mio_uartx_lsr cvmx_mio_uartx_mcr
cvmx_mio_uartx_msr cvmx_mio_uartx_rbr cvmx_mio_uartx_rfl
cvmx_mio_uartx_rfw cvmx_mio_uartx_sbcr cvmx_mio_uartx_scr
cvmx_mio_uartx_sfe cvmx_mio_uartx_srr cvmx_mio_uartx_srt
cvmx_mio_uartx_srts cvmx_mio_uartx_stt cvmx_mio_uartx_tfl
cvmx_mio_uartx_tfr cvmx_mio_uartx_thr cvmx_mio_uartx_usr
cvmx_mixx_bist cvmx_mixx_ctl cvmx_mixx_intena
cvmx_mixx_ircnt cvmx_mixx_irhwm cvmx_mixx_iring1
cvmx_mixx_iring2 cvmx_mixx_isr cvmx_mixx_orcnt
cvmx_mixx_orhwm cvmx_mixx_oring1 cvmx_mixx_oring2
cvmx_mixx_remcnt cvmx_mixx_tsctl cvmx_mixx_tstamp
cvmx_mpi_cfg cvmx_mpi_datx cvmx_mpi_sts
cvmx_mpi_tx cvmx_ndf_bt_pg_info cvmx_ndf_cmd
cvmx_ndf_drbell cvmx_ndf_ecc_cnt cvmx_ndf_int
cvmx_ndf_int_en cvmx_ndf_misc cvmx_ndf_st_reg
cvmx_npei_bar1_indexx cvmx_npei_bist_status cvmx_npei_bist_status2
cvmx_npei_ctl_port0 cvmx_npei_ctl_port1 cvmx_npei_ctl_status
cvmx_npei_ctl_status2 cvmx_npei_data_out_cnt cvmx_npei_dbg_data
cvmx_npei_dbg_select cvmx_npei_dma0_int_level cvmx_npei_dma1_int_level
cvmx_npei_dma_cnts cvmx_npei_dma_control cvmx_npei_dma_pcie_req_num
cvmx_npei_dma_state1 cvmx_npei_dma_state1_p1 cvmx_npei_dma_state2
cvmx_npei_dma_state2_p1 cvmx_npei_dma_state3_p1 cvmx_npei_dma_state4_p1
cvmx_npei_dma_state5_p1 cvmx_npei_dmax_counts cvmx_npei_dmax_dbell
cvmx_npei_dmax_ibuff_saddr cvmx_npei_dmax_naddr cvmx_npei_int_a_enb
cvmx_npei_int_a_enb2 cvmx_npei_int_a_sum cvmx_npei_int_enb
cvmx_npei_int_enb2 cvmx_npei_int_info cvmx_npei_int_sum
cvmx_npei_int_sum2 cvmx_npei_last_win_rdata0 cvmx_npei_last_win_rdata1
cvmx_npei_mem_access_ctl cvmx_npei_mem_access_subidx cvmx_npei_msi_enb0
cvmx_npei_msi_enb1 cvmx_npei_msi_enb2 cvmx_npei_msi_enb3
cvmx_npei_msi_rcv0 cvmx_npei_msi_rcv1 cvmx_npei_msi_rcv2
cvmx_npei_msi_rcv3 cvmx_npei_msi_rd_map cvmx_npei_msi_w1c_enb0
cvmx_npei_msi_w1c_enb1 cvmx_npei_msi_w1c_enb2 cvmx_npei_msi_w1c_enb3
cvmx_npei_msi_w1s_enb0 cvmx_npei_msi_w1s_enb1 cvmx_npei_msi_w1s_enb2
cvmx_npei_msi_w1s_enb3 cvmx_npei_msi_wr_map cvmx_npei_pcie_credit_cnt
cvmx_npei_pcie_msi_rcv cvmx_npei_pcie_msi_rcv_b1 cvmx_npei_pcie_msi_rcv_b2
cvmx_npei_pcie_msi_rcv_b3 cvmx_npei_pkt_cnt_int cvmx_npei_pkt_cnt_int_enb
cvmx_npei_pkt_data_out_es cvmx_npei_pkt_data_out_ns cvmx_npei_pkt_data_out_ror
cvmx_npei_pkt_dpaddr cvmx_npei_pkt_in_bp cvmx_npei_pkt_in_donex_cnts
cvmx_npei_pkt_in_instr_counts cvmx_npei_pkt_in_pcie_port cvmx_npei_pkt_input_control
cvmx_npei_pkt_instr_enb cvmx_npei_pkt_instr_rd_size cvmx_npei_pkt_instr_size
cvmx_npei_pkt_int_levels cvmx_npei_pkt_iptr cvmx_npei_pkt_out_bmode
cvmx_npei_pkt_out_enb cvmx_npei_pkt_output_wmark cvmx_npei_pkt_pcie_port
cvmx_npei_pkt_port_in_rst cvmx_npei_pkt_slist_es cvmx_npei_pkt_slist_id_size
cvmx_npei_pkt_slist_ns cvmx_npei_pkt_slist_ror cvmx_npei_pkt_time_int
cvmx_npei_pkt_time_int_enb cvmx_npei_pktx_cnts cvmx_npei_pktx_in_bp
cvmx_npei_pktx_instr_baddr cvmx_npei_pktx_instr_baoff_dbell cvmx_npei_pktx_instr_fifo_rsize
cvmx_npei_pktx_instr_header cvmx_npei_pktx_slist_baddr cvmx_npei_pktx_slist_baoff_dbell
cvmx_npei_pktx_slist_fifo_rsize cvmx_npei_rsl_int_blocks cvmx_npei_scratch_1
cvmx_npei_state1 cvmx_npei_state2 cvmx_npei_state3
cvmx_npei_win_rd_addr cvmx_npei_win_rd_data cvmx_npei_win_wr_addr
cvmx_npei_win_wr_data cvmx_npei_win_wr_mask cvmx_npei_window_ctl
cvmx_npi_base_addr_inputx cvmx_npi_base_addr_outputx cvmx_npi_bist_status
cvmx_npi_buff_size_outputx cvmx_npi_comp_ctl cvmx_npi_ctl_status
cvmx_npi_dbg_select cvmx_npi_dma_control cvmx_npi_dma_highp_counts
cvmx_npi_dma_highp_naddr cvmx_npi_dma_lowp_counts cvmx_npi_dma_lowp_naddr
cvmx_npi_highp_dbell cvmx_npi_highp_ibuff_saddr cvmx_npi_input_control
cvmx_npi_int_enb cvmx_npi_int_sum cvmx_npi_lowp_dbell
cvmx_npi_lowp_ibuff_saddr cvmx_npi_mem_access_subidx cvmx_npi_msi_rcv
cvmx_npi_num_desc_outputx cvmx_npi_output_control cvmx_npi_pci_burst_size
cvmx_npi_pci_int_arb_cfg cvmx_npi_pci_read_cmd cvmx_npi_port32_instr_hdr
cvmx_npi_port33_instr_hdr cvmx_npi_port34_instr_hdr cvmx_npi_port35_instr_hdr
cvmx_npi_port_bp_control cvmx_npi_px_dbpair_addr cvmx_npi_px_instr_addr
cvmx_npi_px_instr_cnts cvmx_npi_px_pair_cnts cvmx_npi_rsl_int_blocks
cvmx_npi_size_inputx cvmx_npi_win_read_to cvmx_pci_bar1_indexx
cvmx_pci_bist_reg cvmx_pci_cfg00 cvmx_pci_cfg01
cvmx_pci_cfg02 cvmx_pci_cfg03 cvmx_pci_cfg04
cvmx_pci_cfg05 cvmx_pci_cfg06 cvmx_pci_cfg07
cvmx_pci_cfg08 cvmx_pci_cfg09 cvmx_pci_cfg10
cvmx_pci_cfg11 cvmx_pci_cfg12 cvmx_pci_cfg13
cvmx_pci_cfg15 cvmx_pci_cfg16 cvmx_pci_cfg17
cvmx_pci_cfg18 cvmx_pci_cfg19 cvmx_pci_cfg20
cvmx_pci_cfg21 cvmx_pci_cfg22 cvmx_pci_cfg56
cvmx_pci_cfg57 cvmx_pci_cfg58 cvmx_pci_cfg59
cvmx_pci_cfg60 cvmx_pci_cfg61 cvmx_pci_cfg62
cvmx_pci_cfg63 cvmx_pci_cnt_reg cvmx_pci_ctl_status_2
cvmx_pci_dbellx cvmx_pci_dma_cntx cvmx_pci_dma_int_levx
cvmx_pci_dma_timex cvmx_pci_instr_countx cvmx_pci_int_enb
cvmx_pci_int_enb2 cvmx_pci_int_sum cvmx_pci_int_sum2
cvmx_pci_msi_rcv cvmx_pci_pkt_creditsx cvmx_pci_pkts_sent_int_levx
cvmx_pci_pkts_sent_timex cvmx_pci_pkts_sentx cvmx_pci_read_cmd_6
cvmx_pci_read_cmd_c cvmx_pci_read_cmd_e cvmx_pci_read_timeout
cvmx_pci_scm_reg cvmx_pci_tsr_reg cvmx_pci_win_rd_addr
cvmx_pci_win_rd_data cvmx_pci_win_wr_addr cvmx_pci_win_wr_data
cvmx_pci_win_wr_mask cvmx_pcieepx_cfg000 cvmx_pcieepx_cfg001
cvmx_pcieepx_cfg002 cvmx_pcieepx_cfg003 cvmx_pcieepx_cfg004
cvmx_pcieepx_cfg004_mask cvmx_pcieepx_cfg005 cvmx_pcieepx_cfg005_mask
cvmx_pcieepx_cfg006 cvmx_pcieepx_cfg006_mask cvmx_pcieepx_cfg007
cvmx_pcieepx_cfg007_mask cvmx_pcieepx_cfg008 cvmx_pcieepx_cfg008_mask
cvmx_pcieepx_cfg009 cvmx_pcieepx_cfg009_mask cvmx_pcieepx_cfg010
cvmx_pcieepx_cfg011 cvmx_pcieepx_cfg012 cvmx_pcieepx_cfg012_mask
cvmx_pcieepx_cfg013 cvmx_pcieepx_cfg015 cvmx_pcieepx_cfg016
cvmx_pcieepx_cfg017 cvmx_pcieepx_cfg020 cvmx_pcieepx_cfg021
cvmx_pcieepx_cfg022 cvmx_pcieepx_cfg023 cvmx_pcieepx_cfg028
cvmx_pcieepx_cfg029 cvmx_pcieepx_cfg030 cvmx_pcieepx_cfg031
cvmx_pcieepx_cfg032 cvmx_pcieepx_cfg033 cvmx_pcieepx_cfg034
cvmx_pcieepx_cfg037 cvmx_pcieepx_cfg038 cvmx_pcieepx_cfg039
cvmx_pcieepx_cfg040 cvmx_pcieepx_cfg041 cvmx_pcieepx_cfg042
cvmx_pcieepx_cfg064 cvmx_pcieepx_cfg065 cvmx_pcieepx_cfg066
cvmx_pcieepx_cfg067 cvmx_pcieepx_cfg068 cvmx_pcieepx_cfg069
cvmx_pcieepx_cfg070 cvmx_pcieepx_cfg071 cvmx_pcieepx_cfg072
cvmx_pcieepx_cfg073 cvmx_pcieepx_cfg074 cvmx_pcieepx_cfg448
cvmx_pcieepx_cfg449 cvmx_pcieepx_cfg450 cvmx_pcieepx_cfg451
cvmx_pcieepx_cfg452 cvmx_pcieepx_cfg453 cvmx_pcieepx_cfg454
cvmx_pcieepx_cfg455 cvmx_pcieepx_cfg456 cvmx_pcieepx_cfg458
cvmx_pcieepx_cfg459 cvmx_pcieepx_cfg460 cvmx_pcieepx_cfg461
cvmx_pcieepx_cfg462 cvmx_pcieepx_cfg463 cvmx_pcieepx_cfg464
cvmx_pcieepx_cfg465 cvmx_pcieepx_cfg466 cvmx_pcieepx_cfg467
cvmx_pcieepx_cfg468 cvmx_pcieepx_cfg490 cvmx_pcieepx_cfg491
cvmx_pcieepx_cfg492 cvmx_pcieepx_cfg515 cvmx_pcieepx_cfg516
cvmx_pcieepx_cfg517 cvmx_pciercx_cfg000 cvmx_pciercx_cfg001
cvmx_pciercx_cfg002 cvmx_pciercx_cfg003 cvmx_pciercx_cfg004
cvmx_pciercx_cfg005 cvmx_pciercx_cfg006 cvmx_pciercx_cfg007
cvmx_pciercx_cfg008 cvmx_pciercx_cfg009 cvmx_pciercx_cfg010
cvmx_pciercx_cfg011 cvmx_pciercx_cfg012 cvmx_pciercx_cfg013
cvmx_pciercx_cfg014 cvmx_pciercx_cfg015 cvmx_pciercx_cfg016
cvmx_pciercx_cfg017 cvmx_pciercx_cfg020 cvmx_pciercx_cfg021
cvmx_pciercx_cfg022 cvmx_pciercx_cfg023 cvmx_pciercx_cfg028
cvmx_pciercx_cfg029 cvmx_pciercx_cfg030 cvmx_pciercx_cfg031
cvmx_pciercx_cfg032 cvmx_pciercx_cfg033 cvmx_pciercx_cfg034
cvmx_pciercx_cfg035 cvmx_pciercx_cfg036 cvmx_pciercx_cfg037
cvmx_pciercx_cfg038 cvmx_pciercx_cfg039 cvmx_pciercx_cfg040
cvmx_pciercx_cfg041 cvmx_pciercx_cfg042 cvmx_pciercx_cfg064
cvmx_pciercx_cfg065 cvmx_pciercx_cfg066 cvmx_pciercx_cfg067
cvmx_pciercx_cfg068 cvmx_pciercx_cfg069 cvmx_pciercx_cfg070
cvmx_pciercx_cfg071 cvmx_pciercx_cfg072 cvmx_pciercx_cfg073
cvmx_pciercx_cfg074 cvmx_pciercx_cfg075 cvmx_pciercx_cfg076
cvmx_pciercx_cfg077 cvmx_pciercx_cfg448 cvmx_pciercx_cfg449
cvmx_pciercx_cfg450 cvmx_pciercx_cfg451 cvmx_pciercx_cfg452
cvmx_pciercx_cfg453 cvmx_pciercx_cfg454 cvmx_pciercx_cfg455
cvmx_pciercx_cfg456 cvmx_pciercx_cfg458 cvmx_pciercx_cfg459
cvmx_pciercx_cfg460 cvmx_pciercx_cfg461 cvmx_pciercx_cfg462
cvmx_pciercx_cfg463 cvmx_pciercx_cfg464 cvmx_pciercx_cfg465
cvmx_pciercx_cfg466 cvmx_pciercx_cfg467 cvmx_pciercx_cfg468
cvmx_pciercx_cfg490 cvmx_pciercx_cfg491 cvmx_pciercx_cfg492
cvmx_pciercx_cfg515 cvmx_pciercx_cfg516 cvmx_pciercx_cfg517
cvmx_pcm_clkx_cfg cvmx_pcm_clkx_dbg cvmx_pcm_clkx_gen
cvmx_pcmx_dma_cfg cvmx_pcmx_int_ena cvmx_pcmx_int_sum
cvmx_pcmx_rxaddr cvmx_pcmx_rxcnt cvmx_pcmx_rxmsk0
cvmx_pcmx_rxmsk1 cvmx_pcmx_rxmsk2 cvmx_pcmx_rxmsk3
cvmx_pcmx_rxmsk4 cvmx_pcmx_rxmsk5 cvmx_pcmx_rxmsk6
cvmx_pcmx_rxmsk7 cvmx_pcmx_rxstart cvmx_pcmx_tdm_cfg
cvmx_pcmx_tdm_dbg cvmx_pcmx_txaddr cvmx_pcmx_txcnt
cvmx_pcmx_txmsk0 cvmx_pcmx_txmsk1 cvmx_pcmx_txmsk2
cvmx_pcmx_txmsk3 cvmx_pcmx_txmsk4 cvmx_pcmx_txmsk5
cvmx_pcmx_txmsk6 cvmx_pcmx_txmsk7 cvmx_pcmx_txstart
cvmx_pcsx_anx_adv_reg cvmx_pcsx_anx_ext_st_reg cvmx_pcsx_anx_lp_abil_reg
cvmx_pcsx_anx_results_reg cvmx_pcsx_intx_en_reg cvmx_pcsx_intx_reg
cvmx_pcsx_linkx_timer_count_reg cvmx_pcsx_log_anlx_reg cvmx_pcsx_miscx_ctl_reg
cvmx_pcsx_mrx_control_reg cvmx_pcsx_mrx_status_reg cvmx_pcsx_rxx_states_reg
cvmx_pcsx_rxx_sync_reg cvmx_pcsx_sgmx_an_adv_reg cvmx_pcsx_sgmx_lp_adv_reg
cvmx_pcsx_tx_rxx_polarity_reg cvmx_pcsx_txx_states_reg cvmx_pcsxx_10gbx_status_reg
cvmx_pcsxx_bist_status_reg cvmx_pcsxx_bit_lock_status_reg cvmx_pcsxx_control1_reg
cvmx_pcsxx_control2_reg cvmx_pcsxx_int_en_reg cvmx_pcsxx_int_reg
cvmx_pcsxx_log_anl_reg cvmx_pcsxx_misc_ctl_reg cvmx_pcsxx_rx_sync_states_reg
cvmx_pcsxx_spd_abil_reg cvmx_pcsxx_status1_reg cvmx_pcsxx_status2_reg
cvmx_pcsxx_tx_rx_polarity_reg cvmx_pcsxx_tx_rx_states_reg cvmx_pemx_bar1_indexx
cvmx_pemx_bar_ctl cvmx_pemx_bist_status cvmx_pemx_bist_status2
cvmx_pemx_cfg_rd cvmx_pemx_cfg_wr cvmx_pemx_cpl_lut_valid
cvmx_pemx_ctl_status cvmx_pemx_dbg_info cvmx_pemx_dbg_info_en
cvmx_pemx_diag_status cvmx_pemx_int_enb cvmx_pemx_int_enb_int
cvmx_pemx_int_sum cvmx_pemx_p2n_bar0_start cvmx_pemx_p2n_bar1_start
cvmx_pemx_p2n_bar2_start cvmx_pemx_p2p_barx_end cvmx_pemx_p2p_barx_start
cvmx_pemx_tlp_credits cvmx_pescx_bist_status cvmx_pescx_bist_status2
cvmx_pescx_cfg_rd cvmx_pescx_cfg_wr cvmx_pescx_cpl_lut_valid
cvmx_pescx_ctl_status cvmx_pescx_ctl_status2 cvmx_pescx_dbg_info
cvmx_pescx_dbg_info_en cvmx_pescx_diag_status cvmx_pescx_p2n_bar0_start
cvmx_pescx_p2n_bar1_start cvmx_pescx_p2n_bar2_start cvmx_pescx_p2p_barx_end
cvmx_pescx_p2p_barx_start cvmx_pescx_tlp_credits cvmx_pip_bck_prs
cvmx_pip_bist_status cvmx_pip_clken cvmx_pip_crc_ctlx
cvmx_pip_crc_ivx cvmx_pip_dec_ipsecx cvmx_pip_dsa_src_grp
cvmx_pip_dsa_vid_grp cvmx_pip_frm_len_chkx cvmx_pip_gbl_cfg
cvmx_pip_gbl_ctl cvmx_pip_hg_pri_qos cvmx_pip_int_en
cvmx_pip_int_reg cvmx_pip_ip_offset cvmx_pip_prt_cfgx
cvmx_pip_prt_tagx cvmx_pip_qos_diffx cvmx_pip_qos_vlanx
cvmx_pip_qos_watchx cvmx_pip_raw_word cvmx_pip_sft_rst
cvmx_pip_stat0_prtx cvmx_pip_stat1_prtx cvmx_pip_stat2_prtx
cvmx_pip_stat3_prtx cvmx_pip_stat4_prtx cvmx_pip_stat5_prtx
cvmx_pip_stat6_prtx cvmx_pip_stat7_prtx cvmx_pip_stat8_prtx
cvmx_pip_stat9_prtx cvmx_pip_stat_ctl cvmx_pip_stat_inb_errsx
cvmx_pip_stat_inb_octsx cvmx_pip_stat_inb_pktsx cvmx_pip_tag_incx
cvmx_pip_tag_mask cvmx_pip_tag_secret cvmx_pip_todo_entry
cvmx_pip_xstat0_prtx cvmx_pip_xstat1_prtx cvmx_pip_xstat2_prtx
cvmx_pip_xstat3_prtx cvmx_pip_xstat4_prtx cvmx_pip_xstat5_prtx
cvmx_pip_xstat6_prtx cvmx_pip_xstat7_prtx cvmx_pip_xstat8_prtx
cvmx_pip_xstat9_prtx cvmx_pko_mem_count0 cvmx_pko_mem_count1
cvmx_pko_mem_debug0 cvmx_pko_mem_debug1 cvmx_pko_mem_debug10
cvmx_pko_mem_debug11 cvmx_pko_mem_debug12 cvmx_pko_mem_debug13
cvmx_pko_mem_debug14 cvmx_pko_mem_debug2 cvmx_pko_mem_debug3
cvmx_pko_mem_debug4 cvmx_pko_mem_debug5 cvmx_pko_mem_debug6
cvmx_pko_mem_debug7 cvmx_pko_mem_debug8 cvmx_pko_mem_debug9
cvmx_pko_mem_port_ptrs cvmx_pko_mem_port_qos cvmx_pko_mem_port_rate0
cvmx_pko_mem_port_rate1 cvmx_pko_mem_queue_ptrs cvmx_pko_mem_queue_qos
cvmx_pko_reg_bist_result cvmx_pko_reg_cmd_buf cvmx_pko_reg_crc_ctlx
cvmx_pko_reg_crc_enable cvmx_pko_reg_crc_ivx cvmx_pko_reg_debug0
cvmx_pko_reg_debug1 cvmx_pko_reg_debug2 cvmx_pko_reg_debug3
cvmx_pko_reg_engine_inflight cvmx_pko_reg_engine_thresh cvmx_pko_reg_error
cvmx_pko_reg_flags cvmx_pko_reg_gmx_port_mode cvmx_pko_reg_int_mask
cvmx_pko_reg_queue_mode cvmx_pko_reg_queue_ptrs1 cvmx_pko_reg_read_idx
cvmx_pko_reg_timestamp cvmx_pow_bist_stat cvmx_pow_ds_pc
cvmx_pow_ecc_err cvmx_pow_int_ctl cvmx_pow_iq_cntx
cvmx_pow_iq_com_cnt cvmx_pow_iq_int cvmx_pow_iq_int_en
cvmx_pow_iq_thrx cvmx_pow_nos_cnt cvmx_pow_nw_tim
cvmx_pow_pf_rst_msk cvmx_pow_pp_grp_mskx cvmx_pow_qos_rndx
cvmx_pow_qos_thrx cvmx_pow_ts_pc cvmx_pow_wa_com_pc
cvmx_pow_wa_pcx cvmx_pow_wq_int cvmx_pow_wq_int_cntx
cvmx_pow_wq_int_pc cvmx_pow_wq_int_thrx cvmx_pow_ws_pcx
cvmx_rad_mem_debug0 cvmx_rad_mem_debug1 cvmx_rad_mem_debug2
cvmx_rad_reg_bist_result cvmx_rad_reg_cmd_buf cvmx_rad_reg_ctl
cvmx_rad_reg_debug0 cvmx_rad_reg_debug1 cvmx_rad_reg_debug10
cvmx_rad_reg_debug11 cvmx_rad_reg_debug12 cvmx_rad_reg_debug2
cvmx_rad_reg_debug3 cvmx_rad_reg_debug4 cvmx_rad_reg_debug5
cvmx_rad_reg_debug6 cvmx_rad_reg_debug7 cvmx_rad_reg_debug8
cvmx_rad_reg_debug9 cvmx_rad_reg_error cvmx_rad_reg_int_mask
cvmx_rad_reg_polynomial cvmx_rad_reg_read_idx cvmx_rnm_bist_status
cvmx_rnm_ctl_status cvmx_rnm_eer_dbg cvmx_rnm_eer_key
cvmx_rnm_serial_num cvmx_sli_bist_status cvmx_sli_ctl_portx
cvmx_sli_ctl_status cvmx_sli_data_out_cnt cvmx_sli_dbg_data
cvmx_sli_dbg_select cvmx_sli_dmax_cnt cvmx_sli_dmax_int_level
cvmx_sli_dmax_tim cvmx_sli_int_enb_ciu cvmx_sli_int_enb_portx
cvmx_sli_int_sum cvmx_sli_last_win_rdata0 cvmx_sli_last_win_rdata1
cvmx_sli_mac_credit_cnt cvmx_sli_mac_number cvmx_sli_mem_access_ctl
cvmx_sli_mem_access_subidx cvmx_sli_msi_enb0 cvmx_sli_msi_enb1
cvmx_sli_msi_enb2 cvmx_sli_msi_enb3 cvmx_sli_msi_rcv0
cvmx_sli_msi_rcv1 cvmx_sli_msi_rcv2 cvmx_sli_msi_rcv3
cvmx_sli_msi_rd_map cvmx_sli_msi_w1c_enb0 cvmx_sli_msi_w1c_enb1
cvmx_sli_msi_w1c_enb2 cvmx_sli_msi_w1c_enb3 cvmx_sli_msi_w1s_enb0
cvmx_sli_msi_w1s_enb1 cvmx_sli_msi_w1s_enb2 cvmx_sli_msi_w1s_enb3
cvmx_sli_msi_wr_map cvmx_sli_pcie_msi_rcv cvmx_sli_pcie_msi_rcv_b1
cvmx_sli_pcie_msi_rcv_b2 cvmx_sli_pcie_msi_rcv_b3 cvmx_sli_pkt_cnt_int
cvmx_sli_pkt_cnt_int_enb cvmx_sli_pkt_ctl cvmx_sli_pkt_data_out_es
cvmx_sli_pkt_data_out_ns cvmx_sli_pkt_data_out_ror cvmx_sli_pkt_dpaddr
cvmx_sli_pkt_in_bp cvmx_sli_pkt_in_donex_cnts cvmx_sli_pkt_in_instr_counts
cvmx_sli_pkt_in_pcie_port cvmx_sli_pkt_input_control cvmx_sli_pkt_instr_enb
cvmx_sli_pkt_instr_rd_size cvmx_sli_pkt_instr_size cvmx_sli_pkt_int_levels
cvmx_sli_pkt_iptr cvmx_sli_pkt_out_bmode cvmx_sli_pkt_out_enb
cvmx_sli_pkt_output_wmark cvmx_sli_pkt_pcie_port cvmx_sli_pkt_port_in_rst
cvmx_sli_pkt_slist_es cvmx_sli_pkt_slist_ns cvmx_sli_pkt_slist_ror
cvmx_sli_pkt_time_int cvmx_sli_pkt_time_int_enb cvmx_sli_pktx_cnts
cvmx_sli_pktx_in_bp cvmx_sli_pktx_instr_baddr cvmx_sli_pktx_instr_baoff_dbell
cvmx_sli_pktx_instr_fifo_rsize cvmx_sli_pktx_instr_header cvmx_sli_pktx_out_size
cvmx_sli_pktx_slist_baddr cvmx_sli_pktx_slist_baoff_dbell cvmx_sli_pktx_slist_fifo_rsize
cvmx_sli_s2m_portx_ctl cvmx_sli_scratch_1 cvmx_sli_scratch_2
cvmx_sli_state1 cvmx_sli_state2 cvmx_sli_state3
cvmx_sli_win_rd_addr cvmx_sli_win_rd_data cvmx_sli_win_wr_addr
cvmx_sli_win_wr_data cvmx_sli_win_wr_mask cvmx_sli_window_ctl
cvmx_smi_drv_ctl cvmx_smix_clk cvmx_smix_cmd
cvmx_smix_en cvmx_smix_rd_dat cvmx_smix_wr_dat
cvmx_spx0_pll_bw_ctl cvmx_spx0_pll_setting cvmx_spxx_bckprs_cnt
cvmx_spxx_bist_stat cvmx_spxx_clk_ctl cvmx_spxx_clk_stat
cvmx_spxx_dbg_deskew_ctl cvmx_spxx_dbg_deskew_state cvmx_spxx_drv_ctl
cvmx_spxx_err_ctl cvmx_spxx_int_dat cvmx_spxx_int_msk
cvmx_spxx_int_reg cvmx_spxx_int_sync cvmx_spxx_tpa_acc
cvmx_spxx_tpa_max cvmx_spxx_tpa_sel cvmx_spxx_trn4_ctl
cvmx_sriomaintx_asmbly_id cvmx_sriomaintx_asmbly_info cvmx_sriomaintx_bar1_idxx
cvmx_sriomaintx_bell_status cvmx_sriomaintx_comp_tag cvmx_sriomaintx_core_enables
cvmx_sriomaintx_dev_id cvmx_sriomaintx_dev_rev cvmx_sriomaintx_dst_ops
cvmx_sriomaintx_erb_attr_capt cvmx_sriomaintx_erb_err_det cvmx_sriomaintx_erb_err_rate
cvmx_sriomaintx_erb_err_rate_en cvmx_sriomaintx_erb_err_rate_thr cvmx_sriomaintx_erb_hdr
cvmx_sriomaintx_erb_lt_addr_capt_h cvmx_sriomaintx_erb_lt_addr_capt_l cvmx_sriomaintx_erb_lt_ctrl_capt
cvmx_sriomaintx_erb_lt_dev_id cvmx_sriomaintx_erb_lt_dev_id_capt cvmx_sriomaintx_erb_lt_err_det
cvmx_sriomaintx_erb_lt_err_en cvmx_sriomaintx_erb_pack_capt_1 cvmx_sriomaintx_erb_pack_capt_2
cvmx_sriomaintx_erb_pack_capt_3 cvmx_sriomaintx_erb_pack_sym_capt cvmx_sriomaintx_hb_dev_id_lock
cvmx_sriomaintx_ir_buffer_config cvmx_sriomaintx_ir_buffer_config2 cvmx_sriomaintx_ir_pd_phy_ctrl
cvmx_sriomaintx_ir_pd_phy_stat cvmx_sriomaintx_ir_pi_phy_ctrl cvmx_sriomaintx_ir_pi_phy_stat
cvmx_sriomaintx_ir_sp_rx_ctrl cvmx_sriomaintx_ir_sp_rx_data cvmx_sriomaintx_ir_sp_rx_stat
cvmx_sriomaintx_ir_sp_tx_ctrl cvmx_sriomaintx_ir_sp_tx_data cvmx_sriomaintx_ir_sp_tx_stat
cvmx_sriomaintx_lane_x_status_0 cvmx_sriomaintx_lcs_ba0 cvmx_sriomaintx_lcs_ba1
cvmx_sriomaintx_m2s_bar0_start0 cvmx_sriomaintx_m2s_bar0_start1 cvmx_sriomaintx_m2s_bar1_start0
cvmx_sriomaintx_m2s_bar1_start1 cvmx_sriomaintx_m2s_bar2_start cvmx_sriomaintx_mac_ctrl
cvmx_sriomaintx_pe_feat cvmx_sriomaintx_pe_llc cvmx_sriomaintx_port_0_ctl
cvmx_sriomaintx_port_0_ctl2 cvmx_sriomaintx_port_0_err_stat cvmx_sriomaintx_port_0_link_req
cvmx_sriomaintx_port_0_link_resp cvmx_sriomaintx_port_0_local_ackid cvmx_sriomaintx_port_gen_ctl
cvmx_sriomaintx_port_lt_ctl cvmx_sriomaintx_port_mbh0 cvmx_sriomaintx_port_rt_ctl
cvmx_sriomaintx_port_ttl_ctl cvmx_sriomaintx_pri_dev_id cvmx_sriomaintx_sec_dev_ctrl
cvmx_sriomaintx_sec_dev_id cvmx_sriomaintx_serial_lane_hdr cvmx_sriomaintx_src_ops
cvmx_sriomaintx_tx_drop cvmx_sriox_acc_ctrl cvmx_sriox_asmbly_id
cvmx_sriox_asmbly_info cvmx_sriox_bell_resp_ctrl cvmx_sriox_bist_status
cvmx_sriox_imsg_ctrl cvmx_sriox_imsg_inst_hdrx cvmx_sriox_imsg_qos_grpx
cvmx_sriox_imsg_statusx cvmx_sriox_imsg_vport_thr cvmx_sriox_int2_enable
cvmx_sriox_int2_reg cvmx_sriox_int_enable cvmx_sriox_int_info0
cvmx_sriox_int_info1 cvmx_sriox_int_info2 cvmx_sriox_int_info3
cvmx_sriox_int_reg cvmx_sriox_ip_feature cvmx_sriox_mac_buffers
cvmx_sriox_maint_op cvmx_sriox_maint_rd_data cvmx_sriox_mce_tx_ctl
cvmx_sriox_mem_op_ctrl cvmx_sriox_omsg_ctrlx cvmx_sriox_omsg_done_countsx
cvmx_sriox_omsg_fmp_mrx cvmx_sriox_omsg_nmp_mrx cvmx_sriox_omsg_portx
cvmx_sriox_omsg_silo_thr cvmx_sriox_omsg_sp_mrx cvmx_sriox_priox_in_use
cvmx_sriox_rx_bell cvmx_sriox_rx_bell_seq cvmx_sriox_rx_status
cvmx_sriox_s2m_typex cvmx_sriox_seq cvmx_sriox_status_reg
cvmx_sriox_tag_ctrl cvmx_sriox_tlp_credits cvmx_sriox_tx_bell
cvmx_sriox_tx_bell_info cvmx_sriox_tx_ctrl cvmx_sriox_tx_emphasis
cvmx_sriox_tx_status cvmx_sriox_wr_done_counts cvmx_srxx_com_ctl
cvmx_srxx_ign_rx_full cvmx_srxx_spi4_calx cvmx_srxx_spi4_stat
cvmx_srxx_sw_tick_ctl cvmx_srxx_sw_tick_dat cvmx_stxx_arb_ctl
cvmx_stxx_bckprs_cnt cvmx_stxx_com_ctl cvmx_stxx_dip_cnt
cvmx_stxx_ign_cal cvmx_stxx_int_msk cvmx_stxx_int_reg
cvmx_stxx_int_sync cvmx_stxx_min_bst cvmx_stxx_spi4_calx
cvmx_stxx_spi4_dat cvmx_stxx_spi4_stat cvmx_stxx_stat_bytes_hi
cvmx_stxx_stat_bytes_lo cvmx_stxx_stat_ctl cvmx_stxx_stat_pkt_xmt
cvmx_tim_mem_debug0 cvmx_tim_mem_debug1 cvmx_tim_mem_debug2
cvmx_tim_mem_ring0 cvmx_tim_mem_ring1 cvmx_tim_reg_bist_result
cvmx_tim_reg_error cvmx_tim_reg_flags cvmx_tim_reg_int_mask
cvmx_tim_reg_read_idx cvmx_tra_bist_status cvmx_tra_ctl
cvmx_tra_cycles_since cvmx_tra_cycles_since1 cvmx_tra_filt_adr_adr
cvmx_tra_filt_adr_msk cvmx_tra_filt_cmd cvmx_tra_filt_did
cvmx_tra_filt_sid cvmx_tra_int_status cvmx_tra_read_dat
cvmx_tra_read_dat_hi cvmx_tra_trig0_adr_adr cvmx_tra_trig0_adr_msk
cvmx_tra_trig0_cmd cvmx_tra_trig0_did cvmx_tra_trig0_sid
cvmx_tra_trig1_adr_adr cvmx_tra_trig1_adr_msk cvmx_tra_trig1_cmd
cvmx_tra_trig1_did cvmx_tra_trig1_sid cvmx_uahcx_ehci_asynclistaddr
cvmx_uahcx_ehci_configflag cvmx_uahcx_ehci_ctrldssegment cvmx_uahcx_ehci_frindex
cvmx_uahcx_ehci_hccapbase cvmx_uahcx_ehci_hccparams cvmx_uahcx_ehci_hcsparams
cvmx_uahcx_ehci_insnreg00 cvmx_uahcx_ehci_insnreg03 cvmx_uahcx_ehci_insnreg04
cvmx_uahcx_ehci_insnreg06 cvmx_uahcx_ehci_insnreg07 cvmx_uahcx_ehci_periodiclistbase
cvmx_uahcx_ehci_portscx cvmx_uahcx_ehci_usbcmd cvmx_uahcx_ehci_usbintr
cvmx_uahcx_ehci_usbsts cvmx_uahcx_ohci0_hcbulkcurrented cvmx_uahcx_ohci0_hcbulkheaded
cvmx_uahcx_ohci0_hccommandstatus cvmx_uahcx_ohci0_hccontrol cvmx_uahcx_ohci0_hccontrolcurrented
cvmx_uahcx_ohci0_hccontrolheaded cvmx_uahcx_ohci0_hcdonehead cvmx_uahcx_ohci0_hcfminterval
cvmx_uahcx_ohci0_hcfmnumber cvmx_uahcx_ohci0_hcfmremaining cvmx_uahcx_ohci0_hchcca
cvmx_uahcx_ohci0_hcinterruptdisable cvmx_uahcx_ohci0_hcinterruptenable cvmx_uahcx_ohci0_hcinterruptstatus
cvmx_uahcx_ohci0_hclsthreshold cvmx_uahcx_ohci0_hcperiodcurrented cvmx_uahcx_ohci0_hcperiodicstart
cvmx_uahcx_ohci0_hcrevision cvmx_uahcx_ohci0_hcrhdescriptora cvmx_uahcx_ohci0_hcrhdescriptorb
cvmx_uahcx_ohci0_hcrhportstatusx cvmx_uahcx_ohci0_hcrhstatus cvmx_uahcx_ohci0_insnreg06
cvmx_uahcx_ohci0_insnreg07 cvmx_uctlx_bist_status cvmx_uctlx_clk_rst_ctl
cvmx_uctlx_ehci_ctl cvmx_uctlx_ehci_fla cvmx_uctlx_erto_ctl
cvmx_uctlx_if_ena cvmx_uctlx_int_ena cvmx_uctlx_int_reg
cvmx_uctlx_ohci_ctl cvmx_uctlx_orto_ctl cvmx_uctlx_ppaf_wm
cvmx_uctlx_uphy_ctl_status cvmx_uctlx_uphy_portx_ctl_status cvmx_usbcx_daint
cvmx_usbcx_daintmsk cvmx_usbcx_dcfg cvmx_usbcx_dctl
cvmx_usbcx_diepctlx cvmx_usbcx_diepintx cvmx_usbcx_diepmsk
cvmx_usbcx_dieptsizx cvmx_usbcx_doepctlx cvmx_usbcx_doepintx
cvmx_usbcx_doepmsk cvmx_usbcx_doeptsizx cvmx_usbcx_dptxfsizx
cvmx_usbcx_dsts cvmx_usbcx_dtknqr1 cvmx_usbcx_dtknqr2
cvmx_usbcx_dtknqr3 cvmx_usbcx_dtknqr4 cvmx_usbcx_gahbcfg
cvmx_usbcx_ghwcfg1 cvmx_usbcx_ghwcfg2 cvmx_usbcx_ghwcfg3
cvmx_usbcx_ghwcfg4 cvmx_usbcx_gintmsk cvmx_usbcx_gintsts
cvmx_usbcx_gnptxfsiz cvmx_usbcx_gnptxsts cvmx_usbcx_gotgctl
cvmx_usbcx_gotgint cvmx_usbcx_grstctl cvmx_usbcx_grxfsiz
cvmx_usbcx_grxstspd cvmx_usbcx_grxstsph cvmx_usbcx_grxstsrd
cvmx_usbcx_grxstsrh cvmx_usbcx_gsnpsid cvmx_usbcx_gusbcfg
cvmx_usbcx_haint cvmx_usbcx_haintmsk cvmx_usbcx_hccharx
cvmx_usbcx_hcfg cvmx_usbcx_hcintmskx cvmx_usbcx_hcintx
cvmx_usbcx_hcspltx cvmx_usbcx_hctsizx cvmx_usbcx_hfir
cvmx_usbcx_hfnum cvmx_usbcx_hprt cvmx_usbcx_hptxfsiz
cvmx_usbcx_hptxsts cvmx_usbcx_nptxdfifox cvmx_usbcx_pcgcctl
cvmx_usbnx_bist_status cvmx_usbnx_clk_ctl cvmx_usbnx_ctl_status
cvmx_usbnx_dma0_inb_chn0 cvmx_usbnx_dma0_inb_chn1 cvmx_usbnx_dma0_inb_chn2
cvmx_usbnx_dma0_inb_chn3 cvmx_usbnx_dma0_inb_chn4 cvmx_usbnx_dma0_inb_chn5
cvmx_usbnx_dma0_inb_chn6 cvmx_usbnx_dma0_inb_chn7 cvmx_usbnx_dma0_outb_chn0
cvmx_usbnx_dma0_outb_chn1 cvmx_usbnx_dma0_outb_chn2 cvmx_usbnx_dma0_outb_chn3
cvmx_usbnx_dma0_outb_chn4 cvmx_usbnx_dma0_outb_chn5 cvmx_usbnx_dma0_outb_chn6
cvmx_usbnx_dma0_outb_chn7 cvmx_usbnx_dma_test cvmx_usbnx_int_enb
cvmx_usbnx_int_sum cvmx_usbnx_usbp_ctl_status cvmx_zip_cmd_bist_result
cvmx_zip_cmd_buf cvmx_zip_cmd_ctl cvmx_zip_constants
cvmx_zip_debug0 cvmx_zip_error cvmx_zip_int_mask
cvmx_zip_throttle db_prod des_block
desc_value descriptor disk_pages
drm_savage_cmd_header drm_wait_vblank dscrptr
e1000_adv_rx_desc e1000_adv_tx_desc e1000_rx_desc_extended
e1000_rx_desc_packet_split ehci_hub_desc eth_ramrod_data
eth_rx_cqe eth_specific_data eth_tx_bd_types
flentryp fw_encap fw_self_id
ib_gid icb ich8_hws_flash_ctrl
ich8_hws_flash_regacc ich8_hws_flash_status ieee_double_u
ieee_single_u igu_consprod_reg init_op
initiator_data inot_private_data inputArgs
ins_formats instr ipdu_u
ipv4_flow ipv6_flow ipx_host
ipx_net ipx_net_u ixgbe_adv_rx_desc
ixgbe_adv_tx_desc ixgbe_atr_hash_dword ixgbe_atr_input
jrec l_semun l_util
linux_cdrom_addr listen_entry mac_stats
match_pattern match_result mcp_pso_or_cumlen
mfi_bbu_status_detail mfi_frame mfi_mpi2_reply_descriptor
mfi_mpi2_request_descriptor mfi_statrequest mlx4_ext_av
mly_command_address mly_command_packet mly_command_transfer
mly_devinfo mly_health_region mly_ioctl_devconfinfo
mly_ioctl_param mly_status_packet msf_lba
msrinfo mterrstat mthca_buf
musbotg_hub_temp nb_tran nd_opts
nethostaddr nfs_quadconvert nfsfh
octusb_hub_desc ohci_hub_desc opcode_info
opcode_tid outputArgs packet
padlock_cw patch_val pccard_funce
pdu pf_rule_ptr pmc_md_op_pmcallocate
pmc_md_pmc pmclog_entry ppb_insarg
q_util qualhack rdma_protocol_stats
rx_tx_desc sa_route_union savefpu
scheduling_data scheduling_parameters sctpChunkOfInt
sctp_notification sctp_sockstore semun
semun32 semun_old seqno
serv_entry sigval sigval32
slist_header sockaddr_union sockunion
t3_wr t3_wrid tag_TAU32_tsc
tw_cl_command_7k twe_statrequest tws_command_giga
udf_pmap uhci_hub_desc uni_ieall
uni_msgall uniapi_all uniq
usbd_urb uss820_hub_temp uu
vac vcpu_ar_regs vcpu_cr_regs
vdc vm_map_object vmcs_arbytes
x86_register x86emu_register xb_statrequest
xbb_backend_data xenfb_in_event xenfb_out_event
xenkbd_in_event xenkbd_out_event xhci_hub_desc

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